xref: /openbmc/u-boot/include/configs/cyrus.h (revision 66928afb6b55647a446560d32427a032e674301f)
1  /*
2   * Based on corenet_ds.h
3   *
4   * SPDX-License-Identifier:	GPL-2.0+
5   */
6  
7  #ifndef __CONFIG_H
8  #define __CONFIG_H
9  
10  #define CONFIG_CYRUS
11  
12  #if !defined(CONFIG_ARCH_P5020) && !defined(CONFIG_ARCH_P5040)
13  #error Must call Cyrus CONFIG with a specific CPU enabled.
14  #endif
15  
16  #define CONFIG_SDCARD
17  #define CONFIG_FSL_SATA_V2
18  #define CONFIG_PCIE3
19  #define CONFIG_PCIE4
20  #ifdef CONFIG_ARCH_P5020
21  #define CONFIG_SYS_FSL_RAID_ENGINE
22  #define CONFIG_SYS_DPAA_RMAN
23  #endif
24  #define CONFIG_SYS_DPAA_PME
25  
26  /*
27   * Corenet DS style board configuration file
28   */
29  #define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
30  #define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
31  #define CONFIG_SYS_FSL_PBL_PBI board/varisys/cyrus/pbi.cfg
32  #if defined(CONFIG_ARCH_P5020)
33  #define CONFIG_SYS_CLK_FREQ 133000000
34  #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg
35  #elif defined(CONFIG_ARCH_P5040)
36  #define CONFIG_SYS_CLK_FREQ 100000000
37  #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg
38  #endif
39  
40  /* High Level Configuration Options */
41  #define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
42  #define CONFIG_MP			/* support multiple processors */
43  
44  #define CONFIG_SYS_MMC_MAX_DEVICE     1
45  
46  #ifndef CONFIG_SYS_TEXT_BASE
47  #define CONFIG_SYS_TEXT_BASE	0xeff40000
48  #endif
49  
50  #define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
51  #define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
52  #define CONFIG_PCIE1			/* PCIE controller 1 */
53  #define CONFIG_PCIE2			/* PCIE controller 2 */
54  #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
55  #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
56  
57  #define CONFIG_ENV_OVERWRITE
58  
59  #if defined(CONFIG_SDCARD)
60  #define CONFIG_SYS_EXTRA_ENV_RELOC
61  #define CONFIG_ENV_IS_IN_MMC
62  #define CONFIG_FSL_FIXED_MMC_LOCATION
63  #define CONFIG_SYS_MMC_ENV_DEV          0
64  #define CONFIG_ENV_SIZE			0x2000
65  #define CONFIG_ENV_OFFSET		(512 * 1658)
66  #endif
67  
68  /*
69   * These can be toggled for performance analysis, otherwise use default.
70   */
71  #define CONFIG_SYS_CACHE_STASHING
72  #define CONFIG_BACKSIDE_L2_CACHE
73  #define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
74  #define CONFIG_BTB			/* toggle branch predition */
75  #define	CONFIG_DDR_ECC
76  #ifdef CONFIG_DDR_ECC
77  #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
78  #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
79  #endif
80  
81  #define CONFIG_ENABLE_36BIT_PHYS
82  
83  #ifdef CONFIG_PHYS_64BIT
84  #define CONFIG_ADDR_MAP
85  #define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
86  #endif
87  
88  /* test POST memory test */
89  #undef CONFIG_POST
90  #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
91  #define CONFIG_SYS_MEMTEST_END		0x00400000
92  #define CONFIG_SYS_ALT_MEMTEST
93  #define CONFIG_PANIC_HANG	/* do not reset board on panic */
94  
95  /*
96   *  Config the L3 Cache as L3 SRAM
97   */
98  #define CONFIG_SYS_INIT_L3_ADDR		CONFIG_RAMBOOT_TEXT_BASE
99  #ifdef CONFIG_PHYS_64BIT
100  #define CONFIG_SYS_INIT_L3_ADDR_PHYS	(0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
101  #else
102  #define CONFIG_SYS_INIT_L3_ADDR_PHYS	CONFIG_SYS_INIT_L3_ADDR
103  #endif
104  #define CONFIG_SYS_L3_SIZE		(1024 << 10)
105  #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
106  
107  #ifdef CONFIG_PHYS_64BIT
108  #define CONFIG_SYS_DCSRBAR		0xf0000000
109  #define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
110  #endif
111  
112  /*
113   * DDR Setup
114   */
115  #define CONFIG_VERY_BIG_RAM
116  #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
117  #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
118  
119  #define CONFIG_DIMM_SLOTS_PER_CTLR	1
120  #define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
121  
122  #define CONFIG_DDR_SPD
123  
124  #define CONFIG_SYS_SPD_BUS_NUM	1
125  #define SPD_EEPROM_ADDRESS1	0x51
126  #define SPD_EEPROM_ADDRESS2	0x52
127  #define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
128  
129  /*
130   * Local Bus Definitions
131   */
132  
133  #define CONFIG_SYS_LBC0_BASE		0xe0000000 /* Start of LBC Registers */
134  #ifdef CONFIG_PHYS_64BIT
135  #define CONFIG_SYS_LBC0_BASE_PHYS	0xfe0000000ull
136  #else
137  #define CONFIG_SYS_LBC0_BASE_PHYS	CONFIG_SYS_LBC0_BASE
138  #endif
139  
140  #define CONFIG_SYS_LBC1_BASE		0xe1000000 /* Start of LBC Registers */
141  #ifdef CONFIG_PHYS_64BIT
142  #define CONFIG_SYS_LBC1_BASE_PHYS	0xfe1000000ull
143  #else
144  #define CONFIG_SYS_LBC1_BASE_PHYS	CONFIG_SYS_LBC1_BASE
145  #endif
146  
147  /* Set the local bus clock 1/16 of platform clock */
148  #define CONFIG_SYS_LBC_LCRR		(LCRR_CLKDIV_16 | LCRR_EADC_1)
149  
150  #define CONFIG_SYS_BR0_PRELIM \
151  (BR_PHYS_ADDR(CONFIG_SYS_LBC0_BASE_PHYS) | BR_PS_16 | BR_V)
152  #define CONFIG_SYS_BR1_PRELIM \
153  (BR_PHYS_ADDR(CONFIG_SYS_LBC1_BASE_PHYS) | BR_PS_16 | BR_V)
154  
155  #define CONFIG_SYS_OR0_PRELIM	0xfff00010
156  #define CONFIG_SYS_OR1_PRELIM	0xfff00010
157  
158  #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE	/* start of monitor */
159  
160  #if defined(CONFIG_RAMBOOT_PBL)
161  #define CONFIG_SYS_RAMBOOT
162  #endif
163  
164  #define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
165  #define CONFIG_MISC_INIT_R
166  
167  #define CONFIG_HWCONFIG
168  
169  /* define to use L1 as initial stack */
170  #define CONFIG_L1_INIT_RAM
171  #define CONFIG_SYS_INIT_RAM_LOCK
172  #define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
173  #ifdef CONFIG_PHYS_64BIT
174  #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
175  #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
176  /* The assembler doesn't like typecast */
177  #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
178  	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
179  	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
180  #else
181  #define CONFIG_SYS_INIT_RAM_ADDR_PHYS	CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
182  #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
183  #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
184  #endif
185  #define CONFIG_SYS_INIT_RAM_SIZE		0x00004000	/* Size of used area in RAM */
186  
187  #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
188  #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
189  
190  #define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
191  #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
192  
193  /* Serial Port - controlled on board with jumper J8
194   * open - index 2
195   * shorted - index 1
196   */
197  #define CONFIG_CONS_INDEX	1
198  #define CONFIG_SYS_NS16550_SERIAL
199  #define CONFIG_SYS_NS16550_REG_SIZE	1
200  #define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
201  
202  #define CONFIG_SYS_BAUDRATE_TABLE	\
203  {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
204  
205  #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
206  #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
207  #define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
208  #define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
209  
210  /* I2C */
211  #define CONFIG_SYS_I2C
212  #define CONFIG_SYS_I2C_FSL
213  #define CONFIG_I2C_MULTI_BUS
214  #define CONFIG_I2C_CMD_TREE
215  #define CONFIG_SYS_FSL_I2C_SPEED		400000	/* I2C speed and slave address */
216  #define CONFIG_SYS_FSL_I2C_SLAVE		0x7F
217  #define CONFIG_SYS_FSL_I2C_OFFSET		0x118000
218  #define CONFIG_SYS_FSL_I2C2_SPEED		400000	/* I2C speed and slave address */
219  #define CONFIG_SYS_FSL_I2C2_SLAVE		0x7F
220  #define CONFIG_SYS_FSL_I2C2_OFFSET		0x118100
221  #define CONFIG_SYS_FSL_I2C3_SPEED		400000	/* I2C speed and slave address */
222  #define CONFIG_SYS_FSL_I2C3_SLAVE		0x7F
223  #define CONFIG_SYS_FSL_I2C3_OFFSET		0x119000
224  #define CONFIG_SYS_FSL_I2C4_SPEED		400000	/* I2C speed and slave address */
225  #define CONFIG_SYS_FSL_I2C4_SLAVE		0x7F
226  #define CONFIG_SYS_FSL_I2C4_OFFSET		0x119100
227  
228  #define CONFIG_ID_EEPROM
229  #define CONFIG_SYS_I2C_EEPROM_NXID
230  #define CONFIG_SYS_EEPROM_BUS_NUM	0
231  #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
232  #define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
233  
234  #define CONFIG_SYS_I2C_GENERIC_MAC
235  #define CONFIG_SYS_I2C_MAC1_BUS 3
236  #define CONFIG_SYS_I2C_MAC1_CHIP_ADDR 0x57
237  #define CONFIG_SYS_I2C_MAC1_DATA_ADDR 0xf2
238  #define CONFIG_SYS_I2C_MAC2_BUS 0
239  #define CONFIG_SYS_I2C_MAC2_CHIP_ADDR 0x50
240  #define CONFIG_SYS_I2C_MAC2_DATA_ADDR 0xfa
241  
242  #define CONFIG_RTC_MCP79411		1
243  #define CONFIG_SYS_RTC_BUS_NUM		3
244  #define CONFIG_SYS_I2C_RTC_ADDR		0x6f
245  
246  /*
247   * eSPI - Enhanced SPI
248   */
249  
250  /*
251   * General PCI
252   * Memory space is mapped 1-1, but I/O space must start from 0.
253   */
254  
255  /* controller 1, direct to uli, tgtid 3, Base address 20000 */
256  #define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
257  #ifdef CONFIG_PHYS_64BIT
258  #define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
259  #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
260  #else
261  #define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
262  #define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
263  #endif
264  #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
265  #define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
266  #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
267  #ifdef CONFIG_PHYS_64BIT
268  #define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
269  #else
270  #define CONFIG_SYS_PCIE1_IO_PHYS	0xf8000000
271  #endif
272  #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
273  
274  /* controller 2, Slot 2, tgtid 2, Base address 201000 */
275  #define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
276  #ifdef CONFIG_PHYS_64BIT
277  #define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
278  #define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
279  #else
280  #define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
281  #define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
282  #endif
283  #define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
284  #define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
285  #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
286  #ifdef CONFIG_PHYS_64BIT
287  #define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
288  #else
289  #define CONFIG_SYS_PCIE2_IO_PHYS	0xf8010000
290  #endif
291  #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
292  
293  /* controller 3, Slot 1, tgtid 1, Base address 202000 */
294  #define CONFIG_SYS_PCIE3_MEM_VIRT	0xc0000000
295  #ifdef CONFIG_PHYS_64BIT
296  #define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
297  #define CONFIG_SYS_PCIE3_MEM_PHYS	0xc40000000ull
298  #else
299  #define CONFIG_SYS_PCIE3_MEM_BUS	0xc0000000
300  #define CONFIG_SYS_PCIE3_MEM_PHYS	0xc0000000
301  #endif
302  #define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
303  #define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
304  #define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
305  #ifdef CONFIG_PHYS_64BIT
306  #define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
307  #else
308  #define CONFIG_SYS_PCIE3_IO_PHYS	0xf8020000
309  #endif
310  #define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
311  
312  /* controller 4, Base address 203000 */
313  #define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
314  #define CONFIG_SYS_PCIE4_MEM_PHYS	0xc60000000ull
315  #define CONFIG_SYS_PCIE4_MEM_SIZE	0x20000000	/* 512M */
316  #define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
317  #define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
318  #define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
319  
320  /* Qman/Bman */
321  #define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
322  #define CONFIG_SYS_BMAN_NUM_PORTALS	10
323  #define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
324  #ifdef CONFIG_PHYS_64BIT
325  #define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
326  #else
327  #define CONFIG_SYS_BMAN_MEM_PHYS	CONFIG_SYS_BMAN_MEM_BASE
328  #endif
329  #define CONFIG_SYS_BMAN_MEM_SIZE	0x00200000
330  #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
331  #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
332  #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
333  #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
334  #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
335  					 CONFIG_SYS_BMAN_CENA_SIZE)
336  #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
337  #define CONFIG_SYS_BMAN_SWP_ISDR_REG   0xE08
338  #define CONFIG_SYS_QMAN_NUM_PORTALS	10
339  #define CONFIG_SYS_QMAN_MEM_BASE	0xf4200000
340  #ifdef CONFIG_PHYS_64BIT
341  #define CONFIG_SYS_QMAN_MEM_PHYS	0xff4200000ull
342  #else
343  #define CONFIG_SYS_QMAN_MEM_PHYS	CONFIG_SYS_QMAN_MEM_BASE
344  #endif
345  #define CONFIG_SYS_QMAN_MEM_SIZE	0x00200000
346  #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
347  #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
348  #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
349  #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
350  #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
351  					  CONFIG_SYS_QMAN_CENA_SIZE)
352  #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
353  #define CONFIG_SYS_QMAN_SWP_ISDR_REG   0xE08
354  
355  #define CONFIG_SYS_DPAA_FMAN
356  /* Default address of microcode for the Linux Fman driver */
357  /*
358   * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
359   * about 825KB (1650 blocks), Env is stored after the image, and the env size is
360   * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
361   */
362  #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
363  #define CONFIG_SYS_FMAN_FW_ADDR	(512 * 1680)
364  
365  #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
366  #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
367  
368  #ifdef CONFIG_SYS_DPAA_FMAN
369  #define CONFIG_FMAN_ENET
370  #define CONFIG_PHY_MICREL
371  #define CONFIG_PHY_MICREL_KSZ9021
372  #endif
373  
374  #ifdef CONFIG_PCI
375  #define CONFIG_PCI_INDIRECT_BRIDGE
376  #define CONFIG_NET_MULTI
377  
378  #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
379  #endif	/* CONFIG_PCI */
380  
381  /* SATA */
382  #ifdef CONFIG_FSL_SATA_V2
383  #define CONFIG_LIBATA
384  #define CONFIG_FSL_SATA
385  
386  #define CONFIG_SYS_SATA_MAX_DEVICE	2
387  #define CONFIG_SATA1
388  #define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
389  #define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
390  #define CONFIG_SATA2
391  #define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
392  #define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
393  
394  #define CONFIG_LBA48
395  #define CONFIG_CMD_SATA
396  #endif
397  
398  #ifdef CONFIG_FMAN_ENET
399  #define CONFIG_SYS_TBIPA_VALUE	8
400  #define CONFIG_MII		/* MII PHY management */
401  #define CONFIG_ETHPRIME		"FM1@DTSEC4"
402  #define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
403  #endif
404  
405  /*
406   * Environment
407   */
408  #define CONFIG_LOADS_ECHO		/* echo on for serial download */
409  #define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
410  
411  /*
412   * Command line configuration.
413   */
414  #define CONFIG_CMD_ERRATA
415  #define CONFIG_CMD_IRQ
416  #define CONFIG_CMD_REGINFO
417  
418  #ifdef CONFIG_PCI
419  #define CONFIG_CMD_PCI
420  #endif
421  
422  /*
423   * USB
424   */
425  #define CONFIG_HAS_FSL_DR_USB
426  #define CONFIG_HAS_FSL_MPH_USB
427  
428  #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
429  #define CONFIG_USB_EHCI
430  #define CONFIG_USB_EHCI_FSL
431  #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
432  #define CONFIG_EHCI_IS_TDI
433  #define CONFIG_SYS_USB_EVENT_POLL
434   /* _VIA_CONTROL_EP  */
435  #endif
436  
437  #ifdef CONFIG_MMC
438  #define CONFIG_FSL_ESDHC
439  #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
440  #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
441  #endif
442  
443  /*
444   * Miscellaneous configurable options
445   */
446  #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
447  #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
448  #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
449  #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
450  #ifdef CONFIG_CMD_KGDB
451  #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
452  #else
453  #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
454  #endif
455  #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
456  #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
457  #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
458  
459  /*
460   * For booting Linux, the board info and command line data
461   * have to be in the first 64 MB of memory, since this is
462   * the maximum mapped by the Linux kernel during initialization.
463   */
464  #define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
465  #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
466  
467  #ifdef CONFIG_CMD_KGDB
468  #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
469  #endif
470  
471  /*
472   * Environment Configuration
473   */
474  #define CONFIG_ROOTPATH		"/opt/nfsroot"
475  #define CONFIG_BOOTFILE		"uImage"
476  #define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
477  
478  /* default location for tftp and bootm */
479  #define CONFIG_LOADADDR		1000000
480  
481  #define __USB_PHY_TYPE	utmi
482  
483  #define	CONFIG_EXTRA_ENV_SETTINGS \
484  "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"		\
485  "bank_intlv=cs0_cs1;"					\
486  "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
487  "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
488  "netdev=eth0\0"						\
489  "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
490  "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"			\
491  "consoledev=ttyS0\0"					\
492  "ramdiskaddr=2000000\0"					\
493  "fdtaddr=1e00000\0"					\
494  "bdev=sda3\0"
495  
496  #define CONFIG_HDBOOT					\
497  "setenv bootargs root=/dev/$bdev rw "		\
498  "console=$consoledev,$baudrate $othbootargs;"	\
499  "tftp $loadaddr $bootfile;"			\
500  "tftp $fdtaddr $fdtfile;"			\
501  "bootm $loadaddr - $fdtaddr"
502  
503  #define CONFIG_NFSBOOTCOMMAND			\
504  "setenv bootargs root=/dev/nfs rw "	\
505  "nfsroot=$serverip:$rootpath "		\
506  "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
507  "console=$consoledev,$baudrate $othbootargs;"	\
508  "tftp $loadaddr $bootfile;"		\
509  "tftp $fdtaddr $fdtfile;"		\
510  "bootm $loadaddr - $fdtaddr"
511  
512  #define CONFIG_RAMBOOTCOMMAND				\
513  "setenv bootargs root=/dev/ram rw "		\
514  "console=$consoledev,$baudrate $othbootargs;"	\
515  "tftp $ramdiskaddr $ramdiskfile;"		\
516  "tftp $loadaddr $bootfile;"			\
517  "tftp $fdtaddr $fdtfile;"			\
518  "bootm $loadaddr $ramdiskaddr $fdtaddr"
519  
520  #define CONFIG_BOOTCOMMAND		CONFIG_HDBOOT
521  
522  #include <asm/fsl_secure_boot.h>
523  
524  #ifdef CONFIG_SECURE_BOOT
525  #endif
526  
527  #endif	/* __CONFIG_H */
528