1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Based on corenet_ds.h 4 */ 5 6 #ifndef __CONFIG_H 7 #define __CONFIG_H 8 9 #if !defined(CONFIG_ARCH_P5020) && !defined(CONFIG_ARCH_P5040) 10 #error Must call Cyrus CONFIG with a specific CPU enabled. 11 #endif 12 13 #define CONFIG_SDCARD 14 #define CONFIG_FSL_SATA_V2 15 #define CONFIG_PCIE3 16 #define CONFIG_PCIE4 17 #ifdef CONFIG_ARCH_P5020 18 #define CONFIG_SYS_FSL_RAID_ENGINE 19 #define CONFIG_SYS_DPAA_RMAN 20 #endif 21 #define CONFIG_SYS_DPAA_PME 22 23 /* 24 * Corenet DS style board configuration file 25 */ 26 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 27 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 28 #define CONFIG_SYS_FSL_PBL_PBI board/varisys/cyrus/pbi.cfg 29 #if defined(CONFIG_ARCH_P5020) 30 #define CONFIG_SYS_CLK_FREQ 133000000 31 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg 32 #elif defined(CONFIG_ARCH_P5040) 33 #define CONFIG_SYS_CLK_FREQ 100000000 34 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg 35 #endif 36 37 /* High Level Configuration Options */ 38 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 39 #define CONFIG_MP /* support multiple processors */ 40 41 #define CONFIG_SYS_MMC_MAX_DEVICE 1 42 43 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 44 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 45 #define CONFIG_PCIE1 /* PCIE controller 1 */ 46 #define CONFIG_PCIE2 /* PCIE controller 2 */ 47 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 48 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 49 50 #define CONFIG_ENV_OVERWRITE 51 52 #if defined(CONFIG_SDCARD) 53 #define CONFIG_SYS_EXTRA_ENV_RELOC 54 #define CONFIG_FSL_FIXED_MMC_LOCATION 55 #define CONFIG_SYS_MMC_ENV_DEV 0 56 #define CONFIG_ENV_SIZE 0x2000 57 #define CONFIG_ENV_OFFSET (512 * 1658) 58 #endif 59 60 /* 61 * These can be toggled for performance analysis, otherwise use default. 62 */ 63 #define CONFIG_SYS_CACHE_STASHING 64 #define CONFIG_BACKSIDE_L2_CACHE 65 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 66 #define CONFIG_BTB /* toggle branch predition */ 67 #define CONFIG_DDR_ECC 68 #ifdef CONFIG_DDR_ECC 69 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 70 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 71 #endif 72 73 #define CONFIG_ENABLE_36BIT_PHYS 74 75 #ifdef CONFIG_PHYS_64BIT 76 #define CONFIG_ADDR_MAP 77 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 78 #endif 79 80 /* test POST memory test */ 81 #undef CONFIG_POST 82 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 83 #define CONFIG_SYS_MEMTEST_END 0x00400000 84 85 /* 86 * Config the L3 Cache as L3 SRAM 87 */ 88 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 89 #ifdef CONFIG_PHYS_64BIT 90 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) 91 #else 92 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 93 #endif 94 #define CONFIG_SYS_L3_SIZE (1024 << 10) 95 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 96 97 #ifdef CONFIG_PHYS_64BIT 98 #define CONFIG_SYS_DCSRBAR 0xf0000000 99 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 100 #endif 101 102 /* 103 * DDR Setup 104 */ 105 #define CONFIG_VERY_BIG_RAM 106 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 107 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 108 109 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 110 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 111 112 #define CONFIG_DDR_SPD 113 114 #define CONFIG_SYS_SPD_BUS_NUM 1 115 #define SPD_EEPROM_ADDRESS1 0x51 116 #define SPD_EEPROM_ADDRESS2 0x52 117 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 118 119 /* 120 * Local Bus Definitions 121 */ 122 123 #define CONFIG_SYS_LBC0_BASE 0xe0000000 /* Start of LBC Registers */ 124 #ifdef CONFIG_PHYS_64BIT 125 #define CONFIG_SYS_LBC0_BASE_PHYS 0xfe0000000ull 126 #else 127 #define CONFIG_SYS_LBC0_BASE_PHYS CONFIG_SYS_LBC0_BASE 128 #endif 129 130 #define CONFIG_SYS_LBC1_BASE 0xe1000000 /* Start of LBC Registers */ 131 #ifdef CONFIG_PHYS_64BIT 132 #define CONFIG_SYS_LBC1_BASE_PHYS 0xfe1000000ull 133 #else 134 #define CONFIG_SYS_LBC1_BASE_PHYS CONFIG_SYS_LBC1_BASE 135 #endif 136 137 /* Set the local bus clock 1/16 of platform clock */ 138 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_16 | LCRR_EADC_1) 139 140 #define CONFIG_SYS_BR0_PRELIM \ 141 (BR_PHYS_ADDR(CONFIG_SYS_LBC0_BASE_PHYS) | BR_PS_16 | BR_V) 142 #define CONFIG_SYS_BR1_PRELIM \ 143 (BR_PHYS_ADDR(CONFIG_SYS_LBC1_BASE_PHYS) | BR_PS_16 | BR_V) 144 145 #define CONFIG_SYS_OR0_PRELIM 0xfff00010 146 #define CONFIG_SYS_OR1_PRELIM 0xfff00010 147 148 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 149 150 #if defined(CONFIG_RAMBOOT_PBL) 151 #define CONFIG_SYS_RAMBOOT 152 #endif 153 154 #define CONFIG_MISC_INIT_R 155 156 #define CONFIG_HWCONFIG 157 158 /* define to use L1 as initial stack */ 159 #define CONFIG_L1_INIT_RAM 160 #define CONFIG_SYS_INIT_RAM_LOCK 161 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 162 #ifdef CONFIG_PHYS_64BIT 163 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 164 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 165 /* The assembler doesn't like typecast */ 166 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 167 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 168 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 169 #else 170 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ 171 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 172 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 173 #endif 174 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 175 176 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 177 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 178 179 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 180 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 181 182 /* Serial Port - controlled on board with jumper J8 183 * open - index 2 184 * shorted - index 1 185 */ 186 #define CONFIG_SYS_NS16550_SERIAL 187 #define CONFIG_SYS_NS16550_REG_SIZE 1 188 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 189 190 #define CONFIG_SYS_BAUDRATE_TABLE \ 191 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 192 193 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 194 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 195 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 196 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 197 198 /* I2C */ 199 #define CONFIG_SYS_I2C 200 #define CONFIG_SYS_I2C_FSL 201 #define CONFIG_I2C_MULTI_BUS 202 #define CONFIG_I2C_CMD_TREE 203 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ 204 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 205 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 206 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed and slave address */ 207 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 208 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 209 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 /* I2C speed and slave address */ 210 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 211 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 212 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 /* I2C speed and slave address */ 213 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 214 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 215 216 #define CONFIG_ID_EEPROM 217 #define CONFIG_SYS_I2C_EEPROM_NXID 218 #define CONFIG_SYS_EEPROM_BUS_NUM 0 219 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 220 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 221 222 #define CONFIG_SYS_I2C_GENERIC_MAC 223 #define CONFIG_SYS_I2C_MAC1_BUS 3 224 #define CONFIG_SYS_I2C_MAC1_CHIP_ADDR 0x57 225 #define CONFIG_SYS_I2C_MAC1_DATA_ADDR 0xf2 226 #define CONFIG_SYS_I2C_MAC2_BUS 0 227 #define CONFIG_SYS_I2C_MAC2_CHIP_ADDR 0x50 228 #define CONFIG_SYS_I2C_MAC2_DATA_ADDR 0xfa 229 230 #define CONFIG_RTC_MCP79411 1 231 #define CONFIG_SYS_RTC_BUS_NUM 3 232 #define CONFIG_SYS_I2C_RTC_ADDR 0x6f 233 234 /* 235 * eSPI - Enhanced SPI 236 */ 237 238 /* 239 * General PCI 240 * Memory space is mapped 1-1, but I/O space must start from 0. 241 */ 242 243 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 244 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 245 #ifdef CONFIG_PHYS_64BIT 246 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 247 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 248 #else 249 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 250 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 251 #endif 252 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 253 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 254 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 255 #ifdef CONFIG_PHYS_64BIT 256 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 257 #else 258 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 259 #endif 260 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 261 262 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 263 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 264 #ifdef CONFIG_PHYS_64BIT 265 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 266 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 267 #else 268 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 269 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 270 #endif 271 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 272 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 273 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 274 #ifdef CONFIG_PHYS_64BIT 275 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 276 #else 277 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 278 #endif 279 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 280 281 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 282 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 283 #ifdef CONFIG_PHYS_64BIT 284 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 285 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 286 #else 287 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 288 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 289 #endif 290 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 291 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 292 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 293 #ifdef CONFIG_PHYS_64BIT 294 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 295 #else 296 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 297 #endif 298 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 299 300 /* controller 4, Base address 203000 */ 301 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 302 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 303 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 304 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 305 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 306 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 307 308 /* Qman/Bman */ 309 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 310 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 311 #ifdef CONFIG_PHYS_64BIT 312 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 313 #else 314 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 315 #endif 316 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 317 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 318 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 319 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 320 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 321 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 322 CONFIG_SYS_BMAN_CENA_SIZE) 323 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 324 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 325 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 326 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 327 #ifdef CONFIG_PHYS_64BIT 328 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 329 #else 330 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 331 #endif 332 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 333 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 334 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 335 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 336 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 337 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 338 CONFIG_SYS_QMAN_CENA_SIZE) 339 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 340 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 341 342 #define CONFIG_SYS_DPAA_FMAN 343 /* Default address of microcode for the Linux Fman driver */ 344 /* 345 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 346 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 347 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 348 */ 349 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 350 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 351 352 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 353 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 354 355 #ifdef CONFIG_SYS_DPAA_FMAN 356 #define CONFIG_FMAN_ENET 357 #endif 358 359 #ifdef CONFIG_PCI 360 #define CONFIG_PCI_INDIRECT_BRIDGE 361 362 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 363 #endif /* CONFIG_PCI */ 364 365 /* SATA */ 366 #ifdef CONFIG_FSL_SATA_V2 367 #define CONFIG_SYS_SATA_MAX_DEVICE 2 368 #define CONFIG_SATA1 369 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 370 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 371 #define CONFIG_SATA2 372 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 373 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 374 375 #define CONFIG_LBA48 376 #endif 377 378 #ifdef CONFIG_FMAN_ENET 379 #define CONFIG_SYS_TBIPA_VALUE 8 380 #define CONFIG_MII /* MII PHY management */ 381 #define CONFIG_ETHPRIME "FM1@DTSEC4" 382 #endif 383 384 /* 385 * Environment 386 */ 387 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 388 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 389 390 /* 391 * USB 392 */ 393 #define CONFIG_HAS_FSL_DR_USB 394 #define CONFIG_HAS_FSL_MPH_USB 395 396 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 397 #define CONFIG_USB_EHCI_FSL 398 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 399 #define CONFIG_EHCI_IS_TDI 400 /* _VIA_CONTROL_EP */ 401 #endif 402 403 #ifdef CONFIG_MMC 404 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 405 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 406 #endif 407 408 /* 409 * Miscellaneous configurable options 410 */ 411 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 412 413 /* 414 * For booting Linux, the board info and command line data 415 * have to be in the first 64 MB of memory, since this is 416 * the maximum mapped by the Linux kernel during initialization. 417 */ 418 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 419 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 420 421 #ifdef CONFIG_CMD_KGDB 422 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 423 #endif 424 425 /* 426 * Environment Configuration 427 */ 428 #define CONFIG_ROOTPATH "/opt/nfsroot" 429 #define CONFIG_BOOTFILE "uImage" 430 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 431 432 /* default location for tftp and bootm */ 433 #define CONFIG_LOADADDR 1000000 434 435 #define __USB_PHY_TYPE utmi 436 437 #define CONFIG_EXTRA_ENV_SETTINGS \ 438 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 439 "bank_intlv=cs0_cs1;" \ 440 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 441 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 442 "netdev=eth0\0" \ 443 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 444 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 445 "consoledev=ttyS0\0" \ 446 "ramdiskaddr=2000000\0" \ 447 "fdtaddr=1e00000\0" \ 448 "bdev=sda3\0" 449 450 #define CONFIG_HDBOOT \ 451 "setenv bootargs root=/dev/$bdev rw " \ 452 "console=$consoledev,$baudrate $othbootargs;" \ 453 "tftp $loadaddr $bootfile;" \ 454 "tftp $fdtaddr $fdtfile;" \ 455 "bootm $loadaddr - $fdtaddr" 456 457 #define CONFIG_NFSBOOTCOMMAND \ 458 "setenv bootargs root=/dev/nfs rw " \ 459 "nfsroot=$serverip:$rootpath " \ 460 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 461 "console=$consoledev,$baudrate $othbootargs;" \ 462 "tftp $loadaddr $bootfile;" \ 463 "tftp $fdtaddr $fdtfile;" \ 464 "bootm $loadaddr - $fdtaddr" 465 466 #define CONFIG_RAMBOOTCOMMAND \ 467 "setenv bootargs root=/dev/ram rw " \ 468 "console=$consoledev,$baudrate $othbootargs;" \ 469 "tftp $ramdiskaddr $ramdiskfile;" \ 470 "tftp $loadaddr $bootfile;" \ 471 "tftp $fdtaddr $fdtfile;" \ 472 "bootm $loadaddr $ramdiskaddr $fdtaddr" 473 474 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 475 476 #include <asm/fsl_secure_boot.h> 477 478 #ifdef CONFIG_SECURE_BOOT 479 #endif 480 481 #endif /* __CONFIG_H */ 482