1 /* 2 * Based on corenet_ds.h 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_CYRUS 11 12 #if !defined(CONFIG_PPC_P5020) && !defined(CONFIG_PPC_P5040) 13 #error Must call Cyrus CONFIG with a specific CPU enabled. 14 #endif 15 16 #define CONFIG_MMC 17 #define CONFIG_SDCARD 18 #define CONFIG_FSL_SATA_V2 19 #define CONFIG_PCIE3 20 #define CONFIG_PCIE4 21 #ifdef CONFIG_PPC_P5020 22 #define CONFIG_SYS_FSL_RAID_ENGINE 23 #define CONFIG_SYS_DPAA_RMAN 24 #endif 25 #define CONFIG_SYS_DPAA_PME 26 27 /* 28 * Corenet DS style board configuration file 29 */ 30 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 31 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 32 #define CONFIG_SYS_FSL_PBL_PBI board/varisys/cyrus/pbi.cfg 33 #if defined(CONFIG_PPC_P5020) 34 #define CONFIG_SYS_CLK_FREQ 133000000 35 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg 36 #elif defined(CONFIG_PPC_P5040) 37 #define CONFIG_SYS_CLK_FREQ 100000000 38 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg 39 #endif 40 41 /* High Level Configuration Options */ 42 #define CONFIG_BOOKE 43 #define CONFIG_E500 /* BOOKE e500 family */ 44 #define CONFIG_E500MC /* BOOKE e500mc family */ 45 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 46 #define CONFIG_MP /* support multiple processors */ 47 48 #define CONFIG_SYS_MMC_MAX_DEVICE 1 49 50 #ifndef CONFIG_SYS_TEXT_BASE 51 #define CONFIG_SYS_TEXT_BASE 0xeff40000 52 #endif 53 54 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 55 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 56 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 57 #define CONFIG_PCI /* Enable PCI/PCIE */ 58 #define CONFIG_PCIE1 /* PCIE controller 1 */ 59 #define CONFIG_PCIE2 /* PCIE controller 2 */ 60 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 61 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 62 63 #define CONFIG_FSL_LAW /* Use common FSL init code */ 64 65 #define CONFIG_ENV_OVERWRITE 66 67 #define CONFIG_SYS_NO_FLASH 68 69 #if defined(CONFIG_SDCARD) 70 #define CONFIG_SYS_EXTRA_ENV_RELOC 71 #define CONFIG_ENV_IS_IN_MMC 72 #define CONFIG_FSL_FIXED_MMC_LOCATION 73 #define CONFIG_SYS_MMC_ENV_DEV 0 74 #define CONFIG_ENV_SIZE 0x2000 75 #define CONFIG_ENV_OFFSET (512 * 1658) 76 #endif 77 78 /* 79 * These can be toggled for performance analysis, otherwise use default. 80 */ 81 #define CONFIG_SYS_CACHE_STASHING 82 #define CONFIG_BACKSIDE_L2_CACHE 83 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 84 #define CONFIG_BTB /* toggle branch predition */ 85 #define CONFIG_DDR_ECC 86 #ifdef CONFIG_DDR_ECC 87 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 88 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 89 #endif 90 91 #define CONFIG_ENABLE_36BIT_PHYS 92 93 #ifdef CONFIG_PHYS_64BIT 94 #define CONFIG_ADDR_MAP 95 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 96 #endif 97 98 /* test POST memory test */ 99 #undef CONFIG_POST 100 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 101 #define CONFIG_SYS_MEMTEST_END 0x00400000 102 #define CONFIG_SYS_ALT_MEMTEST 103 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 104 105 /* 106 * Config the L3 Cache as L3 SRAM 107 */ 108 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 109 #ifdef CONFIG_PHYS_64BIT 110 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) 111 #else 112 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 113 #endif 114 #define CONFIG_SYS_L3_SIZE (1024 << 10) 115 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 116 117 #ifdef CONFIG_PHYS_64BIT 118 #define CONFIG_SYS_DCSRBAR 0xf0000000 119 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 120 #endif 121 122 /* 123 * DDR Setup 124 */ 125 #define CONFIG_VERY_BIG_RAM 126 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 127 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 128 129 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 130 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 131 132 #define CONFIG_DDR_SPD 133 #define CONFIG_SYS_FSL_DDR3 134 135 #define CONFIG_SYS_SPD_BUS_NUM 1 136 #define SPD_EEPROM_ADDRESS1 0x51 137 #define SPD_EEPROM_ADDRESS2 0x52 138 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 139 140 /* 141 * Local Bus Definitions 142 */ 143 144 #define CONFIG_SYS_LBC0_BASE 0xe0000000 /* Start of LBC Registers */ 145 #ifdef CONFIG_PHYS_64BIT 146 #define CONFIG_SYS_LBC0_BASE_PHYS 0xfe0000000ull 147 #else 148 #define CONFIG_SYS_LBC0_BASE_PHYS CONFIG_SYS_LBC0_BASE 149 #endif 150 151 #define CONFIG_SYS_LBC1_BASE 0xe1000000 /* Start of LBC Registers */ 152 #ifdef CONFIG_PHYS_64BIT 153 #define CONFIG_SYS_LBC1_BASE_PHYS 0xfe1000000ull 154 #else 155 #define CONFIG_SYS_LBC1_BASE_PHYS CONFIG_SYS_LBC1_BASE 156 #endif 157 158 /* Set the local bus clock 1/16 of platform clock */ 159 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_16 | LCRR_EADC_1) 160 161 #define CONFIG_SYS_BR0_PRELIM \ 162 (BR_PHYS_ADDR(CONFIG_SYS_LBC0_BASE_PHYS) | BR_PS_16 | BR_V) 163 #define CONFIG_SYS_BR1_PRELIM \ 164 (BR_PHYS_ADDR(CONFIG_SYS_LBC1_BASE_PHYS) | BR_PS_16 | BR_V) 165 166 #define CONFIG_SYS_OR0_PRELIM 0xfff00010 167 #define CONFIG_SYS_OR1_PRELIM 0xfff00010 168 169 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 170 171 #if defined(CONFIG_RAMBOOT_PBL) 172 #define CONFIG_SYS_RAMBOOT 173 #endif 174 175 #define CONFIG_BOARD_EARLY_INIT_F 176 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 177 #define CONFIG_MISC_INIT_R 178 179 #define CONFIG_HWCONFIG 180 181 /* define to use L1 as initial stack */ 182 #define CONFIG_L1_INIT_RAM 183 #define CONFIG_SYS_INIT_RAM_LOCK 184 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 185 #ifdef CONFIG_PHYS_64BIT 186 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 187 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 188 /* The assembler doesn't like typecast */ 189 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 190 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 191 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 192 #else 193 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ 194 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 195 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 196 #endif 197 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 198 199 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 200 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 201 202 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 203 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 204 205 /* Serial Port - controlled on board with jumper J8 206 * open - index 2 207 * shorted - index 1 208 */ 209 #define CONFIG_CONS_INDEX 1 210 #define CONFIG_SYS_NS16550_SERIAL 211 #define CONFIG_SYS_NS16550_REG_SIZE 1 212 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 213 214 #define CONFIG_SYS_BAUDRATE_TABLE \ 215 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 216 217 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 218 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 219 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 220 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 221 222 /* I2C */ 223 #define CONFIG_SYS_I2C 224 #define CONFIG_SYS_I2C_FSL 225 #define CONFIG_I2C_MULTI_BUS 226 #define CONFIG_I2C_CMD_TREE 227 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ 228 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 229 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 230 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed and slave address */ 231 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 232 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 233 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 /* I2C speed and slave address */ 234 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 235 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 236 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 /* I2C speed and slave address */ 237 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 238 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 239 240 #define CONFIG_ID_EEPROM 241 #define CONFIG_SYS_I2C_EEPROM_NXID 242 #define CONFIG_SYS_EEPROM_BUS_NUM 0 243 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 244 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 245 246 #define CONFIG_SYS_I2C_GENERIC_MAC 247 #define CONFIG_SYS_I2C_MAC1_BUS 3 248 #define CONFIG_SYS_I2C_MAC1_CHIP_ADDR 0x57 249 #define CONFIG_SYS_I2C_MAC1_DATA_ADDR 0xf2 250 #define CONFIG_SYS_I2C_MAC2_BUS 0 251 #define CONFIG_SYS_I2C_MAC2_CHIP_ADDR 0x50 252 #define CONFIG_SYS_I2C_MAC2_DATA_ADDR 0xfa 253 254 #define CONFIG_CMD_DATE 1 255 #define CONFIG_RTC_MCP79411 1 256 #define CONFIG_SYS_RTC_BUS_NUM 3 257 #define CONFIG_SYS_I2C_RTC_ADDR 0x6f 258 259 /* 260 * eSPI - Enhanced SPI 261 */ 262 263 /* 264 * General PCI 265 * Memory space is mapped 1-1, but I/O space must start from 0. 266 */ 267 268 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 269 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 270 #ifdef CONFIG_PHYS_64BIT 271 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 272 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 273 #else 274 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 275 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 276 #endif 277 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 278 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 279 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 280 #ifdef CONFIG_PHYS_64BIT 281 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 282 #else 283 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 284 #endif 285 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 286 287 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 288 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 289 #ifdef CONFIG_PHYS_64BIT 290 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 291 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 292 #else 293 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 294 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 295 #endif 296 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 297 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 298 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 299 #ifdef CONFIG_PHYS_64BIT 300 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 301 #else 302 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 303 #endif 304 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 305 306 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 307 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 308 #ifdef CONFIG_PHYS_64BIT 309 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 310 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 311 #else 312 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 313 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 314 #endif 315 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 316 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 317 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 318 #ifdef CONFIG_PHYS_64BIT 319 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 320 #else 321 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 322 #endif 323 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 324 325 /* controller 4, Base address 203000 */ 326 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 327 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 328 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 329 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 330 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 331 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 332 333 /* Qman/Bman */ 334 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 335 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 336 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 337 #ifdef CONFIG_PHYS_64BIT 338 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 339 #else 340 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 341 #endif 342 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 343 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 344 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 345 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 346 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 347 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 348 CONFIG_SYS_BMAN_CENA_SIZE) 349 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 350 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 351 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 352 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 353 #ifdef CONFIG_PHYS_64BIT 354 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 355 #else 356 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 357 #endif 358 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 359 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 360 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 361 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 362 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 363 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 364 CONFIG_SYS_QMAN_CENA_SIZE) 365 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 366 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 367 368 #define CONFIG_SYS_DPAA_FMAN 369 /* Default address of microcode for the Linux Fman driver */ 370 /* 371 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 372 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 373 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 374 */ 375 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 376 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 377 378 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 379 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 380 381 #ifdef CONFIG_SYS_DPAA_FMAN 382 #define CONFIG_FMAN_ENET 383 #define CONFIG_PHY_MICREL 384 #define CONFIG_PHY_MICREL_KSZ9021 385 #endif 386 387 #ifdef CONFIG_PCI 388 #define CONFIG_PCI_INDIRECT_BRIDGE 389 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 390 #define CONFIG_NET_MULTI 391 392 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 393 #define CONFIG_DOS_PARTITION 394 #endif /* CONFIG_PCI */ 395 396 /* SATA */ 397 #ifdef CONFIG_FSL_SATA_V2 398 #define CONFIG_LIBATA 399 #define CONFIG_FSL_SATA 400 401 #define CONFIG_SYS_SATA_MAX_DEVICE 2 402 #define CONFIG_SATA1 403 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 404 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 405 #define CONFIG_SATA2 406 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 407 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 408 409 #define CONFIG_LBA48 410 #define CONFIG_CMD_SATA 411 #define CONFIG_DOS_PARTITION 412 #endif 413 414 #ifdef CONFIG_FMAN_ENET 415 #define CONFIG_SYS_TBIPA_VALUE 8 416 #define CONFIG_MII /* MII PHY management */ 417 #define CONFIG_ETHPRIME "FM1@DTSEC4" 418 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 419 #endif 420 421 /* 422 * Environment 423 */ 424 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 425 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 426 427 /* 428 * Command line configuration. 429 */ 430 #define CONFIG_CMD_ERRATA 431 #define CONFIG_CMD_IRQ 432 #define CONFIG_CMD_REGINFO 433 434 #ifdef CONFIG_PCI 435 #define CONFIG_CMD_PCI 436 #endif 437 438 /* 439 * USB 440 */ 441 #define CONFIG_HAS_FSL_DR_USB 442 #define CONFIG_HAS_FSL_MPH_USB 443 444 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 445 #define CONFIG_USB_EHCI 446 #define CONFIG_USB_EHCI_FSL 447 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 448 #define CONFIG_EHCI_IS_TDI 449 #define CONFIG_SYS_USB_EVENT_POLL 450 /* _VIA_CONTROL_EP */ 451 #endif 452 453 #ifdef CONFIG_MMC 454 #define CONFIG_FSL_ESDHC 455 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 456 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 457 #define CONFIG_GENERIC_MMC 458 #define CONFIG_DOS_PARTITION 459 #endif 460 461 /* 462 * Miscellaneous configurable options 463 */ 464 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 465 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 466 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 467 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 468 #ifdef CONFIG_CMD_KGDB 469 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 470 #else 471 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 472 #endif 473 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 474 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 475 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 476 477 /* 478 * For booting Linux, the board info and command line data 479 * have to be in the first 64 MB of memory, since this is 480 * the maximum mapped by the Linux kernel during initialization. 481 */ 482 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 483 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 484 485 #ifdef CONFIG_CMD_KGDB 486 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 487 #endif 488 489 /* 490 * Environment Configuration 491 */ 492 #define CONFIG_ROOTPATH "/opt/nfsroot" 493 #define CONFIG_BOOTFILE "uImage" 494 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 495 496 /* default location for tftp and bootm */ 497 #define CONFIG_LOADADDR 1000000 498 499 500 #define CONFIG_BAUDRATE 115200 501 502 #define __USB_PHY_TYPE utmi 503 504 #define CONFIG_EXTRA_ENV_SETTINGS \ 505 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 506 "bank_intlv=cs0_cs1;" \ 507 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 508 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 509 "netdev=eth0\0" \ 510 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 511 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 512 "consoledev=ttyS0\0" \ 513 "ramdiskaddr=2000000\0" \ 514 "fdtaddr=1e00000\0" \ 515 "bdev=sda3\0" 516 517 #define CONFIG_HDBOOT \ 518 "setenv bootargs root=/dev/$bdev rw " \ 519 "console=$consoledev,$baudrate $othbootargs;" \ 520 "tftp $loadaddr $bootfile;" \ 521 "tftp $fdtaddr $fdtfile;" \ 522 "bootm $loadaddr - $fdtaddr" 523 524 #define CONFIG_NFSBOOTCOMMAND \ 525 "setenv bootargs root=/dev/nfs rw " \ 526 "nfsroot=$serverip:$rootpath " \ 527 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 528 "console=$consoledev,$baudrate $othbootargs;" \ 529 "tftp $loadaddr $bootfile;" \ 530 "tftp $fdtaddr $fdtfile;" \ 531 "bootm $loadaddr - $fdtaddr" 532 533 #define CONFIG_RAMBOOTCOMMAND \ 534 "setenv bootargs root=/dev/ram rw " \ 535 "console=$consoledev,$baudrate $othbootargs;" \ 536 "tftp $ramdiskaddr $ramdiskfile;" \ 537 "tftp $loadaddr $bootfile;" \ 538 "tftp $fdtaddr $fdtfile;" \ 539 "bootm $loadaddr $ramdiskaddr $fdtaddr" 540 541 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 542 543 #include <asm/fsl_secure_boot.h> 544 545 #ifdef CONFIG_SECURE_BOOT 546 #endif 547 548 #endif /* __CONFIG_H */ 549