1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Based on corenet_ds.h 4 */ 5 6 #ifndef __CONFIG_H 7 #define __CONFIG_H 8 9 #if !defined(CONFIG_ARCH_P5020) && !defined(CONFIG_ARCH_P5040) 10 #error Must call Cyrus CONFIG with a specific CPU enabled. 11 #endif 12 13 #define CONFIG_SDCARD 14 #define CONFIG_FSL_SATA_V2 15 #define CONFIG_PCIE3 16 #define CONFIG_PCIE4 17 #ifdef CONFIG_ARCH_P5020 18 #define CONFIG_SYS_FSL_RAID_ENGINE 19 #define CONFIG_SYS_DPAA_RMAN 20 #endif 21 #define CONFIG_SYS_DPAA_PME 22 23 /* 24 * Corenet DS style board configuration file 25 */ 26 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 27 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 28 #define CONFIG_SYS_FSL_PBL_PBI board/varisys/cyrus/pbi.cfg 29 #if defined(CONFIG_ARCH_P5020) 30 #define CONFIG_SYS_CLK_FREQ 133000000 31 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg 32 #elif defined(CONFIG_ARCH_P5040) 33 #define CONFIG_SYS_CLK_FREQ 100000000 34 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg 35 #endif 36 37 /* High Level Configuration Options */ 38 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 39 40 #define CONFIG_SYS_MMC_MAX_DEVICE 1 41 42 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 43 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 44 #define CONFIG_PCIE1 /* PCIE controller 1 */ 45 #define CONFIG_PCIE2 /* PCIE controller 2 */ 46 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 47 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 48 49 #define CONFIG_ENV_OVERWRITE 50 51 #if defined(CONFIG_SDCARD) 52 #define CONFIG_SYS_EXTRA_ENV_RELOC 53 #define CONFIG_FSL_FIXED_MMC_LOCATION 54 #define CONFIG_SYS_MMC_ENV_DEV 0 55 #define CONFIG_ENV_SIZE 0x2000 56 #define CONFIG_ENV_OFFSET (512 * 1658) 57 #endif 58 59 /* 60 * These can be toggled for performance analysis, otherwise use default. 61 */ 62 #define CONFIG_SYS_CACHE_STASHING 63 #define CONFIG_BACKSIDE_L2_CACHE 64 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 65 #define CONFIG_BTB /* toggle branch predition */ 66 #define CONFIG_DDR_ECC 67 #ifdef CONFIG_DDR_ECC 68 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 69 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 70 #endif 71 72 #define CONFIG_ENABLE_36BIT_PHYS 73 74 #ifdef CONFIG_PHYS_64BIT 75 #define CONFIG_ADDR_MAP 76 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 77 #endif 78 79 /* test POST memory test */ 80 #undef CONFIG_POST 81 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 82 #define CONFIG_SYS_MEMTEST_END 0x00400000 83 84 /* 85 * Config the L3 Cache as L3 SRAM 86 */ 87 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 88 #ifdef CONFIG_PHYS_64BIT 89 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) 90 #else 91 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 92 #endif 93 #define CONFIG_SYS_L3_SIZE (1024 << 10) 94 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 95 96 #ifdef CONFIG_PHYS_64BIT 97 #define CONFIG_SYS_DCSRBAR 0xf0000000 98 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 99 #endif 100 101 /* 102 * DDR Setup 103 */ 104 #define CONFIG_VERY_BIG_RAM 105 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 106 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 107 108 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 109 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 110 111 #define CONFIG_DDR_SPD 112 113 #define CONFIG_SYS_SPD_BUS_NUM 1 114 #define SPD_EEPROM_ADDRESS1 0x51 115 #define SPD_EEPROM_ADDRESS2 0x52 116 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 117 118 /* 119 * Local Bus Definitions 120 */ 121 122 #define CONFIG_SYS_LBC0_BASE 0xe0000000 /* Start of LBC Registers */ 123 #ifdef CONFIG_PHYS_64BIT 124 #define CONFIG_SYS_LBC0_BASE_PHYS 0xfe0000000ull 125 #else 126 #define CONFIG_SYS_LBC0_BASE_PHYS CONFIG_SYS_LBC0_BASE 127 #endif 128 129 #define CONFIG_SYS_LBC1_BASE 0xe1000000 /* Start of LBC Registers */ 130 #ifdef CONFIG_PHYS_64BIT 131 #define CONFIG_SYS_LBC1_BASE_PHYS 0xfe1000000ull 132 #else 133 #define CONFIG_SYS_LBC1_BASE_PHYS CONFIG_SYS_LBC1_BASE 134 #endif 135 136 /* Set the local bus clock 1/16 of platform clock */ 137 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_16 | LCRR_EADC_1) 138 139 #define CONFIG_SYS_BR0_PRELIM \ 140 (BR_PHYS_ADDR(CONFIG_SYS_LBC0_BASE_PHYS) | BR_PS_16 | BR_V) 141 #define CONFIG_SYS_BR1_PRELIM \ 142 (BR_PHYS_ADDR(CONFIG_SYS_LBC1_BASE_PHYS) | BR_PS_16 | BR_V) 143 144 #define CONFIG_SYS_OR0_PRELIM 0xfff00010 145 #define CONFIG_SYS_OR1_PRELIM 0xfff00010 146 147 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 148 149 #if defined(CONFIG_RAMBOOT_PBL) 150 #define CONFIG_SYS_RAMBOOT 151 #endif 152 153 #define CONFIG_HWCONFIG 154 155 /* define to use L1 as initial stack */ 156 #define CONFIG_L1_INIT_RAM 157 #define CONFIG_SYS_INIT_RAM_LOCK 158 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 159 #ifdef CONFIG_PHYS_64BIT 160 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 161 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 162 /* The assembler doesn't like typecast */ 163 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 164 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 165 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 166 #else 167 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ 168 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 169 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 170 #endif 171 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 172 173 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 174 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 175 176 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 177 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 178 179 /* Serial Port - controlled on board with jumper J8 180 * open - index 2 181 * shorted - index 1 182 */ 183 #define CONFIG_SYS_NS16550_SERIAL 184 #define CONFIG_SYS_NS16550_REG_SIZE 1 185 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 186 187 #define CONFIG_SYS_BAUDRATE_TABLE \ 188 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 189 190 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 191 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 192 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 193 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 194 195 /* I2C */ 196 #define CONFIG_SYS_I2C 197 #define CONFIG_SYS_I2C_FSL 198 #define CONFIG_I2C_MULTI_BUS 199 #define CONFIG_I2C_CMD_TREE 200 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ 201 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 202 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 203 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed and slave address */ 204 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 205 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 206 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 /* I2C speed and slave address */ 207 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 208 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 209 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 /* I2C speed and slave address */ 210 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 211 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 212 213 #define CONFIG_ID_EEPROM 214 #define CONFIG_SYS_I2C_EEPROM_NXID 215 #define CONFIG_SYS_EEPROM_BUS_NUM 0 216 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 217 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 218 219 #define CONFIG_SYS_I2C_GENERIC_MAC 220 #define CONFIG_SYS_I2C_MAC1_BUS 3 221 #define CONFIG_SYS_I2C_MAC1_CHIP_ADDR 0x57 222 #define CONFIG_SYS_I2C_MAC1_DATA_ADDR 0xf2 223 #define CONFIG_SYS_I2C_MAC2_BUS 0 224 #define CONFIG_SYS_I2C_MAC2_CHIP_ADDR 0x50 225 #define CONFIG_SYS_I2C_MAC2_DATA_ADDR 0xfa 226 227 #define CONFIG_RTC_MCP79411 1 228 #define CONFIG_SYS_RTC_BUS_NUM 3 229 #define CONFIG_SYS_I2C_RTC_ADDR 0x6f 230 231 /* 232 * eSPI - Enhanced SPI 233 */ 234 235 /* 236 * General PCI 237 * Memory space is mapped 1-1, but I/O space must start from 0. 238 */ 239 240 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 241 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 242 #ifdef CONFIG_PHYS_64BIT 243 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 244 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 245 #else 246 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 247 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 248 #endif 249 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 250 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 251 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 252 #ifdef CONFIG_PHYS_64BIT 253 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 254 #else 255 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 256 #endif 257 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 258 259 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 260 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 261 #ifdef CONFIG_PHYS_64BIT 262 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 263 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 264 #else 265 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 266 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 267 #endif 268 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 269 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 270 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 271 #ifdef CONFIG_PHYS_64BIT 272 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 273 #else 274 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 275 #endif 276 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 277 278 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 279 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 280 #ifdef CONFIG_PHYS_64BIT 281 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 282 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 283 #else 284 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 285 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 286 #endif 287 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 288 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 289 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 290 #ifdef CONFIG_PHYS_64BIT 291 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 292 #else 293 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 294 #endif 295 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 296 297 /* controller 4, Base address 203000 */ 298 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 299 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 300 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 301 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 302 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 303 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 304 305 /* Qman/Bman */ 306 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 307 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 308 #ifdef CONFIG_PHYS_64BIT 309 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 310 #else 311 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 312 #endif 313 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 314 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 315 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 316 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 317 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 318 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 319 CONFIG_SYS_BMAN_CENA_SIZE) 320 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 321 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 322 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 323 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 324 #ifdef CONFIG_PHYS_64BIT 325 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 326 #else 327 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 328 #endif 329 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 330 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 331 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 332 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 333 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 334 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 335 CONFIG_SYS_QMAN_CENA_SIZE) 336 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 337 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 338 339 #define CONFIG_SYS_DPAA_FMAN 340 /* Default address of microcode for the Linux Fman driver */ 341 /* 342 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 343 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 344 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 345 */ 346 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 347 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 348 349 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 350 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 351 352 #ifdef CONFIG_SYS_DPAA_FMAN 353 #define CONFIG_FMAN_ENET 354 #endif 355 356 #ifdef CONFIG_PCI 357 #define CONFIG_PCI_INDIRECT_BRIDGE 358 359 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 360 #endif /* CONFIG_PCI */ 361 362 /* SATA */ 363 #ifdef CONFIG_FSL_SATA_V2 364 #define CONFIG_SYS_SATA_MAX_DEVICE 2 365 #define CONFIG_SATA1 366 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 367 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 368 #define CONFIG_SATA2 369 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 370 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 371 372 #define CONFIG_LBA48 373 #endif 374 375 #ifdef CONFIG_FMAN_ENET 376 #define CONFIG_SYS_TBIPA_VALUE 8 377 #define CONFIG_ETHPRIME "FM1@DTSEC4" 378 #endif 379 380 /* 381 * Environment 382 */ 383 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 384 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 385 386 /* 387 * USB 388 */ 389 #define CONFIG_HAS_FSL_DR_USB 390 #define CONFIG_HAS_FSL_MPH_USB 391 392 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 393 #define CONFIG_USB_EHCI_FSL 394 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 395 #define CONFIG_EHCI_IS_TDI 396 /* _VIA_CONTROL_EP */ 397 #endif 398 399 #ifdef CONFIG_MMC 400 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 401 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 402 #endif 403 404 /* 405 * Miscellaneous configurable options 406 */ 407 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 408 409 /* 410 * For booting Linux, the board info and command line data 411 * have to be in the first 64 MB of memory, since this is 412 * the maximum mapped by the Linux kernel during initialization. 413 */ 414 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 415 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 416 417 #ifdef CONFIG_CMD_KGDB 418 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 419 #endif 420 421 /* 422 * Environment Configuration 423 */ 424 #define CONFIG_ROOTPATH "/opt/nfsroot" 425 #define CONFIG_BOOTFILE "uImage" 426 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 427 428 /* default location for tftp and bootm */ 429 #define CONFIG_LOADADDR 1000000 430 431 #define __USB_PHY_TYPE utmi 432 433 #define CONFIG_EXTRA_ENV_SETTINGS \ 434 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 435 "bank_intlv=cs0_cs1;" \ 436 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 437 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 438 "netdev=eth0\0" \ 439 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 440 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 441 "consoledev=ttyS0\0" \ 442 "ramdiskaddr=2000000\0" \ 443 "fdtaddr=1e00000\0" \ 444 "bdev=sda3\0" 445 446 #define CONFIG_HDBOOT \ 447 "setenv bootargs root=/dev/$bdev rw " \ 448 "console=$consoledev,$baudrate $othbootargs;" \ 449 "tftp $loadaddr $bootfile;" \ 450 "tftp $fdtaddr $fdtfile;" \ 451 "bootm $loadaddr - $fdtaddr" 452 453 #define CONFIG_NFSBOOTCOMMAND \ 454 "setenv bootargs root=/dev/nfs rw " \ 455 "nfsroot=$serverip:$rootpath " \ 456 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 457 "console=$consoledev,$baudrate $othbootargs;" \ 458 "tftp $loadaddr $bootfile;" \ 459 "tftp $fdtaddr $fdtfile;" \ 460 "bootm $loadaddr - $fdtaddr" 461 462 #define CONFIG_RAMBOOTCOMMAND \ 463 "setenv bootargs root=/dev/ram rw " \ 464 "console=$consoledev,$baudrate $othbootargs;" \ 465 "tftp $ramdiskaddr $ramdiskfile;" \ 466 "tftp $loadaddr $bootfile;" \ 467 "tftp $fdtaddr $fdtfile;" \ 468 "bootm $loadaddr $ramdiskaddr $fdtaddr" 469 470 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 471 472 #include <asm/fsl_secure_boot.h> 473 474 #endif /* __CONFIG_H */ 475