1 /* 2 * Common board functions for siemens AT91SAM9G45 based boards 3 * (C) Copyright 2013 Siemens AG 4 * 5 * Based on: 6 * U-Boot file: include/configs/at91sam9m10g45ek.h 7 * (C) Copyright 2007-2008 8 * Stelian Pop <stelian@popies.net> 9 * Lead Tech Design <www.leadtechdesign.com> 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #ifndef __CONFIG_H 15 #define __CONFIG_H 16 17 #include <asm/hardware.h> 18 19 #define CONFIG_SYS_GENERIC_BOARD 20 /* 21 * Warning: changing CONFIG_SYS_TEXT_BASE requires 22 * adapting the initial boot program. 23 * Since the linker has to swallow that define, we must use a pure 24 * hex number here! 25 */ 26 27 #define CONFIG_SYS_TEXT_BASE 0x72000000 28 29 #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ 30 31 /* ARM asynchronous clock */ 32 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 33 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ 34 35 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 36 #define CONFIG_SETUP_MEMORY_TAGS 37 #define CONFIG_INITRD_TAG 38 #define CONFIG_SKIP_LOWLEVEL_INIT 39 #define CONFIG_BOARD_EARLY_INIT_F 40 #define CONFIG_DISPLAY_CPUINFO 41 42 #define CONFIG_CMD_BOOTZ 43 #define CONFIG_OF_LIBFDT 44 45 /* general purpose I/O */ 46 #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ 47 #define CONFIG_AT91_GPIO 48 #define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */ 49 50 /* serial console */ 51 #define CONFIG_ATMEL_USART 52 #define CONFIG_USART_BASE ATMEL_BASE_DBGU 53 #define CONFIG_USART_ID ATMEL_ID_SYS 54 55 /* LED */ 56 #define CONFIG_AT91_LED 57 #define CONFIG_RED_LED AT91_PIN_PD31 /* this is the user1 led */ 58 #define CONFIG_GREEN_LED AT91_PIN_PD0 /* this is the user2 led */ 59 60 #define CONFIG_BOOTDELAY 3 61 62 /* 63 * BOOTP options 64 */ 65 #define CONFIG_BOOTP_BOOTFILESIZE 66 #define CONFIG_BOOTP_BOOTPATH 67 #define CONFIG_BOOTP_GATEWAY 68 #define CONFIG_BOOTP_HOSTNAME 69 70 /* 71 * Command line configuration. 72 */ 73 #include <config_cmd_default.h> 74 #undef CONFIG_CMD_BDI 75 #undef CONFIG_CMD_FPGA 76 #undef CONFIG_CMD_IMI 77 #undef CONFIG_CMD_IMLS 78 #undef CONFIG_CMD_LOADS 79 80 #define CONFIG_CMD_PING 81 #define CONFIG_CMD_DHCP 82 #define CONFIG_CMD_NAND 83 #define CONFIG_CMD_USB 84 85 /* SDRAM */ 86 #define CONFIG_NR_DRAM_BANKS 1 87 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6 88 #define CONFIG_SYS_SDRAM_SIZE 0x08000000 89 90 #define CONFIG_SYS_INIT_SP_ADDR \ 91 (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) 92 93 /* No NOR flash */ 94 #define CONFIG_SYS_NO_FLASH 95 96 /* NAND flash */ 97 #ifdef CONFIG_CMD_NAND 98 #define CONFIG_NAND_ATMEL 99 #define CONFIG_SYS_MAX_NAND_DEVICE 1 100 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 101 #define CONFIG_SYS_NAND_DBW_8 102 /* our ALE is AD21 */ 103 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 104 /* our CLE is AD22 */ 105 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 106 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 107 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8 108 #endif 109 110 /* Ethernet */ 111 #define CONFIG_MACB 112 #define CONFIG_RMII 113 #define CONFIG_NET_RETRY_COUNT 20 114 #define CONFIG_AT91_WANTS_COMMON_PHY 115 116 /* USB */ 117 #define CONFIG_USB_EHCI 118 #define CONFIG_USB_EHCI_ATMEL 119 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 120 #define CONFIG_DOS_PARTITION 121 #define CONFIG_USB_STORAGE 122 123 #define CONFIG_SYS_LOAD_ADDR 0x72000000 /* load address */ 124 125 /* bootstrap + u-boot + env in nandflash */ 126 #define CONFIG_ENV_IS_IN_NAND 127 #define CONFIG_ENV_OFFSET 0x100000 128 #define CONFIG_ENV_OFFSET_REDUND 0x180000 129 #define CONFIG_ENV_SIZE 0x20000 130 131 #define CONFIG_BOOTCOMMAND \ 132 "nand read 0x70000000 0x200000 0x300000;" \ 133 "bootm 0x70000000" 134 #define CONFIG_BOOTARGS \ 135 "console=ttyS0,115200 earlyprintk " \ 136 "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ 137 "256k(env),256k(env_redundant),256k(spare)," \ 138 "512k(dtb),6M(kernel)ro,-(rootfs) " \ 139 "root=/dev/mtdblock7 rw rootfstype=jffs2" 140 141 #define CONFIG_BAUDRATE 115200 142 143 #define CONFIG_SYS_PROMPT "U-Boot> " 144 #define CONFIG_SYS_CBSIZE 256 145 #define CONFIG_SYS_MAXARGS 16 146 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 147 sizeof(CONFIG_SYS_PROMPT) + 16) 148 #define CONFIG_SYS_LONGHELP 149 #define CONFIG_CMDLINE_EDITING 150 #define CONFIG_AUTO_COMPLETE 151 #define CONFIG_SYS_HUSH_PARSER 152 153 /* 154 * Size of malloc() pool 155 */ 156 #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \ 157 128*1024, 0x1000) 158 /* Defines for SPL */ 159 #define CONFIG_SPL_FRAMEWORK 160 #define CONFIG_SPL_TEXT_BASE 0x300000 161 #define CONFIG_SPL_MAX_SIZE (12 * 1024) 162 #define CONFIG_SPL_STACK (16 * 1024) 163 164 #define CONFIG_SPL_BSS_START_ADDR CONFIG_SPL_MAX_SIZE 165 #define CONFIG_SPL_BSS_MAX_SIZE (2 * 1024) 166 167 #define CONFIG_SPL_LIBCOMMON_SUPPORT 168 #define CONFIG_SPL_LIBGENERIC_SUPPORT 169 #define CONFIG_SPL_SERIAL_SUPPORT 170 171 #define CONFIG_SPL_BOARD_INIT 172 #define CONFIG_SPL_GPIO_SUPPORT 173 #define CONFIG_SPL_NAND_SUPPORT 174 #define CONFIG_SPL_NAND_DRIVERS 175 #define CONFIG_SPL_NAND_BASE 176 #define CONFIG_SPL_NAND_ECC 177 #define CONFIG_SPL_NAND_RAW_ONLY 178 #define CONFIG_SPL_NAND_SOFTECC 179 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 180 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 181 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 182 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 183 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 184 185 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 186 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 187 #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ 188 CONFIG_SYS_NAND_PAGE_SIZE) 189 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 190 #define CONFIG_SYS_NAND_ECCSIZE 256 191 #define CONFIG_SYS_NAND_ECCBYTES 3 192 #define CONFIG_SYS_NAND_OOBSIZE 64 193 #define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ 194 48, 49, 50, 51, 52, 53, 54, 55, \ 195 56, 57, 58, 59, 60, 61, 62, 63, } 196 197 #define CONFIG_SPL_ATMEL_SIZE 198 #define CONFIG_SYS_MASTER_CLOCK 132096000 199 #define AT91_PLL_LOCK_TIMEOUT 1000000 200 #define CONFIG_SYS_AT91_PLLA 0x20c73f03 201 #define CONFIG_SYS_MCKR 0x1301 202 #define CONFIG_SYS_MCKR_CSS 0x1302 203 204 #define ATMEL_BASE_MPDDRC ATMEL_BASE_DDRSDRC0 205 206 #endif 207