1 /* 2 * Copyright 2009-2012 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * Corenet DS style board configuration file 25 */ 26 #ifndef __CONFIG_H 27 #define __CONFIG_H 28 29 #include "../board/freescale/common/ics307_clk.h" 30 31 #ifdef CONFIG_RAMBOOT_PBL 32 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 33 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 34 #define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg 35 #if defined(CONFIG_P3041DS) 36 #define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p3041ds.cfg 37 #elif defined(CONFIG_P4080DS) 38 #define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p4080ds.cfg 39 #elif defined(CONFIG_P5020DS) 40 #define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p5020ds.cfg 41 #elif defined(CONFIG_P5040DS) 42 #define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p5040ds.cfg 43 #endif 44 #endif 45 46 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 47 /* Set 1M boot space */ 48 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 49 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 50 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 51 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 52 #define CONFIG_SYS_NO_FLASH 53 #endif 54 55 /* High Level Configuration Options */ 56 #define CONFIG_BOOKE 57 #define CONFIG_E500 /* BOOKE e500 family */ 58 #define CONFIG_E500MC /* BOOKE e500mc family */ 59 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 60 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ 61 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 62 #define CONFIG_MP /* support multiple processors */ 63 64 #ifndef CONFIG_SYS_TEXT_BASE 65 #define CONFIG_SYS_TEXT_BASE 0xeff80000 66 #endif 67 68 #ifndef CONFIG_RESET_VECTOR_ADDRESS 69 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 70 #endif 71 72 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 73 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 74 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 75 #define CONFIG_PCI /* Enable PCI/PCIE */ 76 #define CONFIG_PCIE1 /* PCIE controler 1 */ 77 #define CONFIG_PCIE2 /* PCIE controler 2 */ 78 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 79 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 80 81 #define CONFIG_FSL_LAW /* Use common FSL init code */ 82 83 #define CONFIG_ENV_OVERWRITE 84 85 #ifdef CONFIG_SYS_NO_FLASH 86 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) 87 #define CONFIG_ENV_IS_NOWHERE 88 #endif 89 #else 90 #define CONFIG_FLASH_CFI_DRIVER 91 #define CONFIG_SYS_FLASH_CFI 92 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 93 #endif 94 95 #if defined(CONFIG_SPIFLASH) 96 #define CONFIG_SYS_EXTRA_ENV_RELOC 97 #define CONFIG_ENV_IS_IN_SPI_FLASH 98 #define CONFIG_ENV_SPI_BUS 0 99 #define CONFIG_ENV_SPI_CS 0 100 #define CONFIG_ENV_SPI_MAX_HZ 10000000 101 #define CONFIG_ENV_SPI_MODE 0 102 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 103 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 104 #define CONFIG_ENV_SECT_SIZE 0x10000 105 #elif defined(CONFIG_SDCARD) 106 #define CONFIG_SYS_EXTRA_ENV_RELOC 107 #define CONFIG_ENV_IS_IN_MMC 108 #define CONFIG_FSL_FIXED_MMC_LOCATION 109 #define CONFIG_SYS_MMC_ENV_DEV 0 110 #define CONFIG_ENV_SIZE 0x2000 111 #define CONFIG_ENV_OFFSET (512 * 1097) 112 #elif defined(CONFIG_NAND) 113 #define CONFIG_SYS_EXTRA_ENV_RELOC 114 #define CONFIG_ENV_IS_IN_NAND 115 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 116 #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 117 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 118 #define CONFIG_ENV_IS_IN_REMOTE 119 #define CONFIG_ENV_ADDR 0xffe20000 120 #define CONFIG_ENV_SIZE 0x2000 121 #elif defined(CONFIG_ENV_IS_NOWHERE) 122 #define CONFIG_ENV_SIZE 0x2000 123 #else 124 #define CONFIG_ENV_IS_IN_FLASH 125 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 126 #define CONFIG_ENV_SIZE 0x2000 127 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 128 #endif 129 130 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 131 132 /* 133 * These can be toggled for performance analysis, otherwise use default. 134 */ 135 #define CONFIG_SYS_CACHE_STASHING 136 #define CONFIG_BACKSIDE_L2_CACHE 137 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 138 #define CONFIG_BTB /* toggle branch predition */ 139 #define CONFIG_DDR_ECC 140 #ifdef CONFIG_DDR_ECC 141 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 142 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 143 #endif 144 145 #define CONFIG_ENABLE_36BIT_PHYS 146 147 #ifdef CONFIG_PHYS_64BIT 148 #define CONFIG_ADDR_MAP 149 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 150 #endif 151 152 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 153 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 154 #define CONFIG_SYS_MEMTEST_END 0x00400000 155 #define CONFIG_SYS_ALT_MEMTEST 156 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 157 158 /* 159 * Config the L3 Cache as L3 SRAM 160 */ 161 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 162 #ifdef CONFIG_PHYS_64BIT 163 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) 164 #else 165 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 166 #endif 167 #define CONFIG_SYS_L3_SIZE (1024 << 10) 168 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 169 170 #ifdef CONFIG_PHYS_64BIT 171 #define CONFIG_SYS_DCSRBAR 0xf0000000 172 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 173 #endif 174 175 /* EEPROM */ 176 #define CONFIG_ID_EEPROM 177 #define CONFIG_SYS_I2C_EEPROM_NXID 178 #define CONFIG_SYS_EEPROM_BUS_NUM 0 179 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 180 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 181 182 /* 183 * DDR Setup 184 */ 185 #define CONFIG_VERY_BIG_RAM 186 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 187 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 188 189 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 190 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 191 192 #define CONFIG_DDR_SPD 193 #define CONFIG_FSL_DDR3 194 195 #define CONFIG_SYS_SPD_BUS_NUM 1 196 #define SPD_EEPROM_ADDRESS1 0x51 197 #define SPD_EEPROM_ADDRESS2 0x52 198 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 199 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 200 201 /* 202 * Local Bus Definitions 203 */ 204 205 /* Set the local bus clock 1/8 of platform clock */ 206 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 207 208 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */ 209 #ifdef CONFIG_PHYS_64BIT 210 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 211 #else 212 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 213 #endif 214 215 #define CONFIG_SYS_FLASH_BR_PRELIM \ 216 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \ 217 | BR_PS_16 | BR_V) 218 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 219 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 220 221 #define CONFIG_SYS_BR1_PRELIM \ 222 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 223 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 224 225 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 226 #ifdef CONFIG_PHYS_64BIT 227 #define PIXIS_BASE_PHYS 0xfffdf0000ull 228 #else 229 #define PIXIS_BASE_PHYS PIXIS_BASE 230 #endif 231 232 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 233 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 234 235 #define PIXIS_LBMAP_SWITCH 7 236 #define PIXIS_LBMAP_MASK 0xf0 237 #define PIXIS_LBMAP_SHIFT 4 238 #define PIXIS_LBMAP_ALTBANK 0x40 239 240 #define CONFIG_SYS_FLASH_QUIET_TEST 241 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 242 243 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 244 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 245 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 246 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 247 248 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 249 250 #if defined(CONFIG_RAMBOOT_PBL) 251 #define CONFIG_SYS_RAMBOOT 252 #endif 253 254 /* Nand Flash */ 255 #ifdef CONFIG_NAND_FSL_ELBC 256 #define CONFIG_SYS_NAND_BASE 0xffa00000 257 #ifdef CONFIG_PHYS_64BIT 258 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 259 #else 260 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 261 #endif 262 263 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 264 #define CONFIG_SYS_MAX_NAND_DEVICE 1 265 #define CONFIG_MTD_NAND_VERIFY_WRITE 266 #define CONFIG_CMD_NAND 267 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 268 269 /* NAND flash config */ 270 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 271 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 272 | BR_PS_8 /* Port Size = 8 bit */ \ 273 | BR_MS_FCM /* MSEL = FCM */ \ 274 | BR_V) /* valid */ 275 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 276 | OR_FCM_PGS /* Large Page*/ \ 277 | OR_FCM_CSCT \ 278 | OR_FCM_CST \ 279 | OR_FCM_CHT \ 280 | OR_FCM_SCY_1 \ 281 | OR_FCM_TRLX \ 282 | OR_FCM_EHTR) 283 284 #ifdef CONFIG_NAND 285 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 286 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 287 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 288 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 289 #else 290 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 291 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 292 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 293 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 294 #endif 295 #else 296 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 297 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 298 #endif /* CONFIG_NAND_FSL_ELBC */ 299 300 #define CONFIG_SYS_FLASH_EMPTY_INFO 301 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 302 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 303 304 #define CONFIG_BOARD_EARLY_INIT_F 305 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 306 #define CONFIG_MISC_INIT_R 307 308 #define CONFIG_HWCONFIG 309 310 /* define to use L1 as initial stack */ 311 #define CONFIG_L1_INIT_RAM 312 #define CONFIG_SYS_INIT_RAM_LOCK 313 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 314 #ifdef CONFIG_PHYS_64BIT 315 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 316 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 317 /* The assembler doesn't like typecast */ 318 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 319 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 320 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 321 #else 322 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ 323 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 324 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 325 #endif 326 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 327 328 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 329 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 330 331 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 332 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 333 334 /* Serial Port - controlled on board with jumper J8 335 * open - index 2 336 * shorted - index 1 337 */ 338 #define CONFIG_CONS_INDEX 1 339 #define CONFIG_SYS_NS16550 340 #define CONFIG_SYS_NS16550_SERIAL 341 #define CONFIG_SYS_NS16550_REG_SIZE 1 342 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 343 344 #define CONFIG_SYS_BAUDRATE_TABLE \ 345 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 346 347 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 348 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 349 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 350 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 351 352 /* Use the HUSH parser */ 353 #define CONFIG_SYS_HUSH_PARSER 354 355 /* pass open firmware flat tree */ 356 #define CONFIG_OF_LIBFDT 357 #define CONFIG_OF_BOARD_SETUP 358 #define CONFIG_OF_STDOUT_VIA_ALIAS 359 360 /* new uImage format support */ 361 #define CONFIG_FIT 362 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 363 364 /* I2C */ 365 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 366 #define CONFIG_HARD_I2C /* I2C with hardware support */ 367 #define CONFIG_I2C_MULTI_BUS 368 #define CONFIG_I2C_CMD_TREE 369 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 370 #define CONFIG_SYS_I2C_SLAVE 0x7F 371 #define CONFIG_SYS_I2C_OFFSET 0x118000 372 #define CONFIG_SYS_I2C2_OFFSET 0x118100 373 374 /* 375 * RapidIO 376 */ 377 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 378 #ifdef CONFIG_PHYS_64BIT 379 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 380 #else 381 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 382 #endif 383 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 384 385 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 386 #ifdef CONFIG_PHYS_64BIT 387 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 388 #else 389 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 390 #endif 391 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 392 393 /* 394 * for slave u-boot IMAGE instored in master memory space, 395 * PHYS must be aligned based on the SIZE 396 */ 397 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull 398 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull 399 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */ 400 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull 401 /* 402 * for slave UCODE and ENV instored in master memory space, 403 * PHYS must be aligned based on the SIZE 404 */ 405 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull 406 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 407 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 408 409 /* slave core release by master*/ 410 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 411 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 412 413 /* 414 * SRIO_PCIE_BOOT - SLAVE 415 */ 416 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 417 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 418 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 419 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 420 #endif 421 422 /* 423 * eSPI - Enhanced SPI 424 */ 425 #define CONFIG_FSL_ESPI 426 #define CONFIG_SPI_FLASH 427 #define CONFIG_SPI_FLASH_SPANSION 428 #define CONFIG_CMD_SF 429 #define CONFIG_SF_DEFAULT_SPEED 10000000 430 #define CONFIG_SF_DEFAULT_MODE 0 431 432 /* 433 * General PCI 434 * Memory space is mapped 1-1, but I/O space must start from 0. 435 */ 436 437 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 438 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 439 #ifdef CONFIG_PHYS_64BIT 440 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 441 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 442 #else 443 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 444 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 445 #endif 446 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 447 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 448 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 449 #ifdef CONFIG_PHYS_64BIT 450 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 451 #else 452 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 453 #endif 454 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 455 456 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 457 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 458 #ifdef CONFIG_PHYS_64BIT 459 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 460 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 461 #else 462 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 463 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 464 #endif 465 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 466 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 467 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 468 #ifdef CONFIG_PHYS_64BIT 469 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 470 #else 471 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 472 #endif 473 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 474 475 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 476 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 477 #ifdef CONFIG_PHYS_64BIT 478 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 479 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 480 #else 481 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 482 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 483 #endif 484 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 485 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 486 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 487 #ifdef CONFIG_PHYS_64BIT 488 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 489 #else 490 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 491 #endif 492 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 493 494 /* controller 4, Base address 203000 */ 495 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 496 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 497 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 498 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 499 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 500 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 501 502 /* Qman/Bman */ 503 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 504 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 505 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 506 #ifdef CONFIG_PHYS_64BIT 507 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 508 #else 509 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 510 #endif 511 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 512 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 513 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 514 #ifdef CONFIG_PHYS_64BIT 515 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 516 #else 517 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 518 #endif 519 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 520 521 #define CONFIG_SYS_DPAA_FMAN 522 #define CONFIG_SYS_DPAA_PME 523 /* Default address of microcode for the Linux Fman driver */ 524 #if defined(CONFIG_SPIFLASH) 525 /* 526 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 527 * env, so we got 0x110000. 528 */ 529 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 530 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 531 #elif defined(CONFIG_SDCARD) 532 /* 533 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 534 * about 545KB (1089 blocks), Env is stored after the image, and the env size is 535 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. 536 */ 537 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 538 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) 539 #elif defined(CONFIG_NAND) 540 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 541 #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) 542 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 543 /* 544 * Slave has no ucode locally, it can fetch this from remote. When implementing 545 * in two corenet boards, slave's ucode could be stored in master's memory 546 * space, the address can be mapped from slave TLB->slave LAW-> 547 * slave SRIO or PCIE outbound window->master inbound window-> 548 * master LAW->the ucode address in master's memory space. 549 */ 550 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 551 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 552 #else 553 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 554 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 555 #endif 556 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 557 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 558 559 #ifdef CONFIG_SYS_DPAA_FMAN 560 #define CONFIG_FMAN_ENET 561 #define CONFIG_PHYLIB_10G 562 #define CONFIG_PHY_VITESSE 563 #define CONFIG_PHY_TERANETICS 564 #endif 565 566 #ifdef CONFIG_PCI 567 #define CONFIG_PCI_INDIRECT_BRIDGE 568 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 569 #define CONFIG_E1000 570 571 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 572 #define CONFIG_DOS_PARTITION 573 #endif /* CONFIG_PCI */ 574 575 /* SATA */ 576 #ifdef CONFIG_FSL_SATA_V2 577 #define CONFIG_LIBATA 578 #define CONFIG_FSL_SATA 579 580 #define CONFIG_SYS_SATA_MAX_DEVICE 2 581 #define CONFIG_SATA1 582 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 583 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 584 #define CONFIG_SATA2 585 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 586 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 587 588 #define CONFIG_LBA48 589 #define CONFIG_CMD_SATA 590 #define CONFIG_DOS_PARTITION 591 #define CONFIG_CMD_EXT2 592 #endif 593 594 #ifdef CONFIG_FMAN_ENET 595 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c 596 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d 597 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e 598 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f 599 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 600 601 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c 602 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d 603 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e 604 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f 605 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0 606 607 #define CONFIG_SYS_TBIPA_VALUE 8 608 #define CONFIG_MII /* MII PHY management */ 609 #define CONFIG_ETHPRIME "FM1@DTSEC1" 610 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 611 #endif 612 613 /* 614 * Environment 615 */ 616 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 617 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 618 619 /* 620 * Command line configuration. 621 */ 622 #include <config_cmd_default.h> 623 624 #define CONFIG_CMD_DHCP 625 #define CONFIG_CMD_ELF 626 #define CONFIG_CMD_ERRATA 627 #define CONFIG_CMD_GREPENV 628 #define CONFIG_CMD_IRQ 629 #define CONFIG_CMD_I2C 630 #define CONFIG_CMD_MII 631 #define CONFIG_CMD_PING 632 #define CONFIG_CMD_SETEXPR 633 #define CONFIG_CMD_REGINFO 634 635 #ifdef CONFIG_PCI 636 #define CONFIG_CMD_PCI 637 #define CONFIG_CMD_NET 638 #endif 639 640 /* 641 * USB 642 */ 643 #define CONFIG_HAS_FSL_DR_USB 644 #define CONFIG_HAS_FSL_MPH_USB 645 646 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 647 #define CONFIG_CMD_USB 648 #define CONFIG_USB_STORAGE 649 #define CONFIG_USB_EHCI 650 #define CONFIG_USB_EHCI_FSL 651 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 652 #define CONFIG_CMD_EXT2 653 #endif 654 655 #ifdef CONFIG_MMC 656 #define CONFIG_FSL_ESDHC 657 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 658 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 659 #define CONFIG_CMD_MMC 660 #define CONFIG_GENERIC_MMC 661 #define CONFIG_CMD_EXT2 662 #define CONFIG_CMD_FAT 663 #define CONFIG_DOS_PARTITION 664 #endif 665 666 /* 667 * Miscellaneous configurable options 668 */ 669 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 670 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 671 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 672 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 673 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 674 #ifdef CONFIG_CMD_KGDB 675 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 676 #else 677 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 678 #endif 679 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 680 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 681 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 682 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 683 684 /* 685 * For booting Linux, the board info and command line data 686 * have to be in the first 64 MB of memory, since this is 687 * the maximum mapped by the Linux kernel during initialization. 688 */ 689 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 690 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 691 692 #ifdef CONFIG_CMD_KGDB 693 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 694 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 695 #endif 696 697 /* 698 * Environment Configuration 699 */ 700 #define CONFIG_ROOTPATH "/opt/nfsroot" 701 #define CONFIG_BOOTFILE "uImage" 702 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 703 704 /* default location for tftp and bootm */ 705 #define CONFIG_LOADADDR 1000000 706 707 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 708 709 #define CONFIG_BAUDRATE 115200 710 711 #ifdef CONFIG_P4080DS 712 #define __USB_PHY_TYPE ulpi 713 #else 714 #define __USB_PHY_TYPE utmi 715 #endif 716 717 #define CONFIG_EXTRA_ENV_SETTINGS \ 718 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 719 "bank_intlv=cs0_cs1;" \ 720 "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 721 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 722 "netdev=eth0\0" \ 723 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 724 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 725 "tftpflash=tftpboot $loadaddr $uboot && " \ 726 "protect off $ubootaddr +$filesize && " \ 727 "erase $ubootaddr +$filesize && " \ 728 "cp.b $loadaddr $ubootaddr $filesize && " \ 729 "protect on $ubootaddr +$filesize && " \ 730 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 731 "consoledev=ttyS0\0" \ 732 "ramdiskaddr=2000000\0" \ 733 "ramdiskfile=p4080ds/ramdisk.uboot\0" \ 734 "fdtaddr=c00000\0" \ 735 "fdtfile=p4080ds/p4080ds.dtb\0" \ 736 "bdev=sda3\0" \ 737 "c=ffe\0" 738 739 #define CONFIG_HDBOOT \ 740 "setenv bootargs root=/dev/$bdev rw " \ 741 "console=$consoledev,$baudrate $othbootargs;" \ 742 "tftp $loadaddr $bootfile;" \ 743 "tftp $fdtaddr $fdtfile;" \ 744 "bootm $loadaddr - $fdtaddr" 745 746 #define CONFIG_NFSBOOTCOMMAND \ 747 "setenv bootargs root=/dev/nfs rw " \ 748 "nfsroot=$serverip:$rootpath " \ 749 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 750 "console=$consoledev,$baudrate $othbootargs;" \ 751 "tftp $loadaddr $bootfile;" \ 752 "tftp $fdtaddr $fdtfile;" \ 753 "bootm $loadaddr - $fdtaddr" 754 755 #define CONFIG_RAMBOOTCOMMAND \ 756 "setenv bootargs root=/dev/ram rw " \ 757 "console=$consoledev,$baudrate $othbootargs;" \ 758 "tftp $ramdiskaddr $ramdiskfile;" \ 759 "tftp $loadaddr $bootfile;" \ 760 "tftp $fdtaddr $fdtfile;" \ 761 "bootm $loadaddr $ramdiskaddr $fdtaddr" 762 763 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 764 765 #ifdef CONFIG_SECURE_BOOT 766 #include <asm/fsl_secure_boot.h> 767 #endif 768 769 #endif /* __CONFIG_H */ 770