1 /* 2 * Copyright 2009-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * Corenet DS style board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #include "../board/freescale/common/ics307_clk.h" 14 15 #ifdef CONFIG_RAMBOOT_PBL 16 #ifdef CONFIG_SECURE_BOOT 17 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 18 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 19 #ifdef CONFIG_NAND 20 #define CONFIG_RAMBOOT_NAND 21 #endif 22 #define CONFIG_BOOTSCRIPT_COPY_RAM 23 #else 24 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 25 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 26 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg 27 #if defined(CONFIG_TARGET_P3041DS) 28 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg 29 #elif defined(CONFIG_TARGET_P4080DS) 30 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg 31 #elif defined(CONFIG_TARGET_P5020DS) 32 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg 33 #elif defined(CONFIG_TARGET_P5040DS) 34 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg 35 #endif 36 #endif 37 #endif 38 39 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 40 /* Set 1M boot space */ 41 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 42 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 43 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 44 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 45 #define CONFIG_SYS_NO_FLASH 46 #endif 47 48 /* High Level Configuration Options */ 49 #define CONFIG_BOOKE 50 #define CONFIG_E500 /* BOOKE e500 family */ 51 #define CONFIG_E500MC /* BOOKE e500mc family */ 52 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 53 #define CONFIG_MP /* support multiple processors */ 54 55 #ifndef CONFIG_SYS_TEXT_BASE 56 #define CONFIG_SYS_TEXT_BASE 0xeff40000 57 #endif 58 59 #ifndef CONFIG_RESET_VECTOR_ADDRESS 60 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 61 #endif 62 63 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 64 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 65 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 66 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 67 #define CONFIG_PCIE1 /* PCIE controller 1 */ 68 #define CONFIG_PCIE2 /* PCIE controller 2 */ 69 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 70 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 71 72 #define CONFIG_ENV_OVERWRITE 73 74 #ifdef CONFIG_SYS_NO_FLASH 75 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) 76 #define CONFIG_ENV_IS_NOWHERE 77 #endif 78 #else 79 #define CONFIG_FLASH_CFI_DRIVER 80 #define CONFIG_SYS_FLASH_CFI 81 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 82 #endif 83 84 #if defined(CONFIG_SPIFLASH) 85 #define CONFIG_SYS_EXTRA_ENV_RELOC 86 #define CONFIG_ENV_IS_IN_SPI_FLASH 87 #define CONFIG_ENV_SPI_BUS 0 88 #define CONFIG_ENV_SPI_CS 0 89 #define CONFIG_ENV_SPI_MAX_HZ 10000000 90 #define CONFIG_ENV_SPI_MODE 0 91 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 92 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 93 #define CONFIG_ENV_SECT_SIZE 0x10000 94 #elif defined(CONFIG_SDCARD) 95 #define CONFIG_SYS_EXTRA_ENV_RELOC 96 #define CONFIG_ENV_IS_IN_MMC 97 #define CONFIG_FSL_FIXED_MMC_LOCATION 98 #define CONFIG_SYS_MMC_ENV_DEV 0 99 #define CONFIG_ENV_SIZE 0x2000 100 #define CONFIG_ENV_OFFSET (512 * 1658) 101 #elif defined(CONFIG_NAND) 102 #define CONFIG_SYS_EXTRA_ENV_RELOC 103 #define CONFIG_ENV_IS_IN_NAND 104 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 105 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 106 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 107 #define CONFIG_ENV_IS_IN_REMOTE 108 #define CONFIG_ENV_ADDR 0xffe20000 109 #define CONFIG_ENV_SIZE 0x2000 110 #elif defined(CONFIG_ENV_IS_NOWHERE) 111 #define CONFIG_ENV_SIZE 0x2000 112 #else 113 #define CONFIG_ENV_IS_IN_FLASH 114 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 115 #define CONFIG_ENV_SIZE 0x2000 116 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 117 #endif 118 119 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 120 121 /* 122 * These can be toggled for performance analysis, otherwise use default. 123 */ 124 #define CONFIG_SYS_CACHE_STASHING 125 #define CONFIG_BACKSIDE_L2_CACHE 126 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 127 #define CONFIG_BTB /* toggle branch predition */ 128 #define CONFIG_DDR_ECC 129 #ifdef CONFIG_DDR_ECC 130 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 131 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 132 #endif 133 134 #define CONFIG_ENABLE_36BIT_PHYS 135 136 #ifdef CONFIG_PHYS_64BIT 137 #define CONFIG_ADDR_MAP 138 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 139 #endif 140 141 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 142 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 143 #define CONFIG_SYS_MEMTEST_END 0x00400000 144 #define CONFIG_SYS_ALT_MEMTEST 145 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 146 147 /* 148 * Config the L3 Cache as L3 SRAM 149 */ 150 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 151 #ifdef CONFIG_PHYS_64BIT 152 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) 153 #else 154 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 155 #endif 156 #define CONFIG_SYS_L3_SIZE (1024 << 10) 157 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 158 159 #ifdef CONFIG_PHYS_64BIT 160 #define CONFIG_SYS_DCSRBAR 0xf0000000 161 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 162 #endif 163 164 /* EEPROM */ 165 #define CONFIG_ID_EEPROM 166 #define CONFIG_SYS_I2C_EEPROM_NXID 167 #define CONFIG_SYS_EEPROM_BUS_NUM 0 168 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 169 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 170 171 /* 172 * DDR Setup 173 */ 174 #define CONFIG_VERY_BIG_RAM 175 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 176 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 177 178 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 179 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 180 181 #define CONFIG_DDR_SPD 182 #define CONFIG_SYS_FSL_DDR3 183 184 #define CONFIG_SYS_SPD_BUS_NUM 1 185 #define SPD_EEPROM_ADDRESS1 0x51 186 #define SPD_EEPROM_ADDRESS2 0x52 187 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 188 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 189 190 /* 191 * Local Bus Definitions 192 */ 193 194 /* Set the local bus clock 1/8 of platform clock */ 195 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 196 197 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */ 198 #ifdef CONFIG_PHYS_64BIT 199 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 200 #else 201 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 202 #endif 203 204 #define CONFIG_SYS_FLASH_BR_PRELIM \ 205 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \ 206 | BR_PS_16 | BR_V) 207 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 208 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 209 210 #define CONFIG_SYS_BR1_PRELIM \ 211 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 212 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 213 214 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 215 #ifdef CONFIG_PHYS_64BIT 216 #define PIXIS_BASE_PHYS 0xfffdf0000ull 217 #else 218 #define PIXIS_BASE_PHYS PIXIS_BASE 219 #endif 220 221 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 222 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 223 224 #define PIXIS_LBMAP_SWITCH 7 225 #define PIXIS_LBMAP_MASK 0xf0 226 #define PIXIS_LBMAP_SHIFT 4 227 #define PIXIS_LBMAP_ALTBANK 0x40 228 229 #define CONFIG_SYS_FLASH_QUIET_TEST 230 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 231 232 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 233 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 234 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 235 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 236 237 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 238 239 #if defined(CONFIG_RAMBOOT_PBL) 240 #define CONFIG_SYS_RAMBOOT 241 #endif 242 243 /* Nand Flash */ 244 #ifdef CONFIG_NAND_FSL_ELBC 245 #define CONFIG_SYS_NAND_BASE 0xffa00000 246 #ifdef CONFIG_PHYS_64BIT 247 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 248 #else 249 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 250 #endif 251 252 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 253 #define CONFIG_SYS_MAX_NAND_DEVICE 1 254 #define CONFIG_CMD_NAND 255 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 256 257 /* NAND flash config */ 258 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 259 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 260 | BR_PS_8 /* Port Size = 8 bit */ \ 261 | BR_MS_FCM /* MSEL = FCM */ \ 262 | BR_V) /* valid */ 263 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 264 | OR_FCM_PGS /* Large Page*/ \ 265 | OR_FCM_CSCT \ 266 | OR_FCM_CST \ 267 | OR_FCM_CHT \ 268 | OR_FCM_SCY_1 \ 269 | OR_FCM_TRLX \ 270 | OR_FCM_EHTR) 271 272 #ifdef CONFIG_NAND 273 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 274 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 275 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 276 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 277 #else 278 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 279 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 280 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 281 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 282 #endif 283 #else 284 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 285 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 286 #endif /* CONFIG_NAND_FSL_ELBC */ 287 288 #define CONFIG_SYS_FLASH_EMPTY_INFO 289 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 290 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 291 292 #define CONFIG_BOARD_EARLY_INIT_F 293 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 294 #define CONFIG_MISC_INIT_R 295 296 #define CONFIG_HWCONFIG 297 298 /* define to use L1 as initial stack */ 299 #define CONFIG_L1_INIT_RAM 300 #define CONFIG_SYS_INIT_RAM_LOCK 301 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 302 #ifdef CONFIG_PHYS_64BIT 303 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 304 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 305 /* The assembler doesn't like typecast */ 306 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 307 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 308 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 309 #else 310 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ 311 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 312 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 313 #endif 314 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 315 316 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 317 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 318 319 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 320 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 321 322 /* Serial Port - controlled on board with jumper J8 323 * open - index 2 324 * shorted - index 1 325 */ 326 #define CONFIG_CONS_INDEX 1 327 #define CONFIG_SYS_NS16550_SERIAL 328 #define CONFIG_SYS_NS16550_REG_SIZE 1 329 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 330 331 #define CONFIG_SYS_BAUDRATE_TABLE \ 332 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 333 334 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 335 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 336 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 337 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 338 339 /* I2C */ 340 #define CONFIG_SYS_I2C 341 #define CONFIG_SYS_I2C_FSL 342 #define CONFIG_SYS_FSL_I2C_SPEED 400000 343 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 344 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 345 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 346 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 347 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 348 349 /* 350 * RapidIO 351 */ 352 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 353 #ifdef CONFIG_PHYS_64BIT 354 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 355 #else 356 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 357 #endif 358 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 359 360 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 361 #ifdef CONFIG_PHYS_64BIT 362 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 363 #else 364 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 365 #endif 366 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 367 368 /* 369 * for slave u-boot IMAGE instored in master memory space, 370 * PHYS must be aligned based on the SIZE 371 */ 372 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 373 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 374 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 375 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 376 /* 377 * for slave UCODE and ENV instored in master memory space, 378 * PHYS must be aligned based on the SIZE 379 */ 380 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 381 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 382 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 383 384 /* slave core release by master*/ 385 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 386 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 387 388 /* 389 * SRIO_PCIE_BOOT - SLAVE 390 */ 391 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 392 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 393 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 394 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 395 #endif 396 397 /* 398 * eSPI - Enhanced SPI 399 */ 400 #define CONFIG_SF_DEFAULT_SPEED 10000000 401 #define CONFIG_SF_DEFAULT_MODE 0 402 403 /* 404 * General PCI 405 * Memory space is mapped 1-1, but I/O space must start from 0. 406 */ 407 408 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 409 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 410 #ifdef CONFIG_PHYS_64BIT 411 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 412 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 413 #else 414 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 415 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 416 #endif 417 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 418 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 419 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 420 #ifdef CONFIG_PHYS_64BIT 421 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 422 #else 423 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 424 #endif 425 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 426 427 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 428 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 429 #ifdef CONFIG_PHYS_64BIT 430 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 431 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 432 #else 433 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 434 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 435 #endif 436 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 437 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 438 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 439 #ifdef CONFIG_PHYS_64BIT 440 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 441 #else 442 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 443 #endif 444 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 445 446 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 447 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 448 #ifdef CONFIG_PHYS_64BIT 449 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 450 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 451 #else 452 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 453 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 454 #endif 455 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 456 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 457 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 458 #ifdef CONFIG_PHYS_64BIT 459 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 460 #else 461 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 462 #endif 463 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 464 465 /* controller 4, Base address 203000 */ 466 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 467 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 468 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 469 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 470 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 471 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 472 473 /* Qman/Bman */ 474 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 475 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 476 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 477 #ifdef CONFIG_PHYS_64BIT 478 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 479 #else 480 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 481 #endif 482 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 483 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 484 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 485 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 486 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 487 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 488 CONFIG_SYS_BMAN_CENA_SIZE) 489 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 490 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 491 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 492 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 493 #ifdef CONFIG_PHYS_64BIT 494 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 495 #else 496 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 497 #endif 498 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 499 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 500 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 501 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 502 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 503 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 504 CONFIG_SYS_QMAN_CENA_SIZE) 505 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 506 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 507 508 #define CONFIG_SYS_DPAA_FMAN 509 #define CONFIG_SYS_DPAA_PME 510 /* Default address of microcode for the Linux Fman driver */ 511 #if defined(CONFIG_SPIFLASH) 512 /* 513 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 514 * env, so we got 0x110000. 515 */ 516 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 517 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 518 #elif defined(CONFIG_SDCARD) 519 /* 520 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 521 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 522 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 523 */ 524 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 525 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 526 #elif defined(CONFIG_NAND) 527 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 528 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 529 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 530 /* 531 * Slave has no ucode locally, it can fetch this from remote. When implementing 532 * in two corenet boards, slave's ucode could be stored in master's memory 533 * space, the address can be mapped from slave TLB->slave LAW-> 534 * slave SRIO or PCIE outbound window->master inbound window-> 535 * master LAW->the ucode address in master's memory space. 536 */ 537 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 538 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 539 #else 540 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 541 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 542 #endif 543 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 544 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 545 546 #ifdef CONFIG_SYS_DPAA_FMAN 547 #define CONFIG_FMAN_ENET 548 #define CONFIG_PHYLIB_10G 549 #define CONFIG_PHY_VITESSE 550 #define CONFIG_PHY_TERANETICS 551 #endif 552 553 #ifdef CONFIG_PCI 554 #define CONFIG_PCI_INDIRECT_BRIDGE 555 556 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 557 #define CONFIG_DOS_PARTITION 558 #endif /* CONFIG_PCI */ 559 560 /* SATA */ 561 #ifdef CONFIG_FSL_SATA_V2 562 #define CONFIG_LIBATA 563 #define CONFIG_FSL_SATA 564 565 #define CONFIG_SYS_SATA_MAX_DEVICE 2 566 #define CONFIG_SATA1 567 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 568 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 569 #define CONFIG_SATA2 570 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 571 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 572 573 #define CONFIG_LBA48 574 #define CONFIG_CMD_SATA 575 #define CONFIG_DOS_PARTITION 576 #endif 577 578 #ifdef CONFIG_FMAN_ENET 579 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c 580 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d 581 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e 582 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f 583 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 584 585 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c 586 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d 587 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e 588 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f 589 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0 590 591 #define CONFIG_SYS_TBIPA_VALUE 8 592 #define CONFIG_MII /* MII PHY management */ 593 #define CONFIG_ETHPRIME "FM1@DTSEC1" 594 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 595 #endif 596 597 /* 598 * Environment 599 */ 600 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 601 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 602 603 /* 604 * Command line configuration. 605 */ 606 #define CONFIG_CMD_ERRATA 607 #define CONFIG_CMD_IRQ 608 #define CONFIG_CMD_REGINFO 609 610 #ifdef CONFIG_PCI 611 #define CONFIG_CMD_PCI 612 #endif 613 614 /* 615 * USB 616 */ 617 #define CONFIG_HAS_FSL_DR_USB 618 #define CONFIG_HAS_FSL_MPH_USB 619 620 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 621 #define CONFIG_USB_EHCI 622 #define CONFIG_USB_EHCI_FSL 623 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 624 #endif 625 626 #ifdef CONFIG_MMC 627 #define CONFIG_FSL_ESDHC 628 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 629 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 630 #define CONFIG_GENERIC_MMC 631 #define CONFIG_DOS_PARTITION 632 #endif 633 634 /* Hash command with SHA acceleration supported in hardware */ 635 #ifdef CONFIG_FSL_CAAM 636 #define CONFIG_CMD_HASH 637 #define CONFIG_SHA_HW_ACCEL 638 #endif 639 640 /* 641 * Miscellaneous configurable options 642 */ 643 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 644 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 645 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 646 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 647 #ifdef CONFIG_CMD_KGDB 648 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 649 #else 650 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 651 #endif 652 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 653 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 654 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 655 656 /* 657 * For booting Linux, the board info and command line data 658 * have to be in the first 64 MB of memory, since this is 659 * the maximum mapped by the Linux kernel during initialization. 660 */ 661 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 662 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 663 664 #ifdef CONFIG_CMD_KGDB 665 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 666 #endif 667 668 /* 669 * Environment Configuration 670 */ 671 #define CONFIG_ROOTPATH "/opt/nfsroot" 672 #define CONFIG_BOOTFILE "uImage" 673 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 674 675 /* default location for tftp and bootm */ 676 #define CONFIG_LOADADDR 1000000 677 678 679 #define CONFIG_BAUDRATE 115200 680 681 #ifdef CONFIG_TARGET_P4080DS 682 #define __USB_PHY_TYPE ulpi 683 #else 684 #define __USB_PHY_TYPE utmi 685 #endif 686 687 #define CONFIG_EXTRA_ENV_SETTINGS \ 688 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 689 "bank_intlv=cs0_cs1;" \ 690 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 691 "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 692 "netdev=eth0\0" \ 693 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 694 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 695 "tftpflash=tftpboot $loadaddr $uboot && " \ 696 "protect off $ubootaddr +$filesize && " \ 697 "erase $ubootaddr +$filesize && " \ 698 "cp.b $loadaddr $ubootaddr $filesize && " \ 699 "protect on $ubootaddr +$filesize && " \ 700 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 701 "consoledev=ttyS0\0" \ 702 "ramdiskaddr=2000000\0" \ 703 "ramdiskfile=p4080ds/ramdisk.uboot\0" \ 704 "fdtaddr=1e00000\0" \ 705 "fdtfile=p4080ds/p4080ds.dtb\0" \ 706 "bdev=sda3\0" 707 708 #define CONFIG_HDBOOT \ 709 "setenv bootargs root=/dev/$bdev rw " \ 710 "console=$consoledev,$baudrate $othbootargs;" \ 711 "tftp $loadaddr $bootfile;" \ 712 "tftp $fdtaddr $fdtfile;" \ 713 "bootm $loadaddr - $fdtaddr" 714 715 #define CONFIG_NFSBOOTCOMMAND \ 716 "setenv bootargs root=/dev/nfs rw " \ 717 "nfsroot=$serverip:$rootpath " \ 718 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 719 "console=$consoledev,$baudrate $othbootargs;" \ 720 "tftp $loadaddr $bootfile;" \ 721 "tftp $fdtaddr $fdtfile;" \ 722 "bootm $loadaddr - $fdtaddr" 723 724 #define CONFIG_RAMBOOTCOMMAND \ 725 "setenv bootargs root=/dev/ram rw " \ 726 "console=$consoledev,$baudrate $othbootargs;" \ 727 "tftp $ramdiskaddr $ramdiskfile;" \ 728 "tftp $loadaddr $bootfile;" \ 729 "tftp $fdtaddr $fdtfile;" \ 730 "bootm $loadaddr $ramdiskaddr $fdtaddr" 731 732 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 733 734 #include <asm/fsl_secure_boot.h> 735 736 #endif /* __CONFIG_H */ 737