1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2009-2012 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * Corenet DS style board configuration file 8 */ 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include "../board/freescale/common/ics307_clk.h" 13 14 #ifdef CONFIG_RAMBOOT_PBL 15 #ifdef CONFIG_SECURE_BOOT 16 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 17 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 18 #ifdef CONFIG_NAND 19 #define CONFIG_RAMBOOT_NAND 20 #endif 21 #define CONFIG_BOOTSCRIPT_COPY_RAM 22 #else 23 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 24 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 25 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg 26 #if defined(CONFIG_TARGET_P3041DS) 27 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg 28 #elif defined(CONFIG_TARGET_P4080DS) 29 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg 30 #elif defined(CONFIG_TARGET_P5020DS) 31 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg 32 #elif defined(CONFIG_TARGET_P5040DS) 33 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg 34 #endif 35 #endif 36 #endif 37 38 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 39 /* Set 1M boot space */ 40 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 41 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 42 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 43 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 44 #endif 45 46 /* High Level Configuration Options */ 47 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 48 49 #ifndef CONFIG_RESET_VECTOR_ADDRESS 50 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 51 #endif 52 53 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 54 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 55 #define CONFIG_PCIE1 /* PCIE controller 1 */ 56 #define CONFIG_PCIE2 /* PCIE controller 2 */ 57 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 58 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 59 60 #define CONFIG_ENV_OVERWRITE 61 62 #if defined(CONFIG_SPIFLASH) 63 #define CONFIG_ENV_SPI_BUS 0 64 #define CONFIG_ENV_SPI_CS 0 65 #define CONFIG_ENV_SPI_MAX_HZ 10000000 66 #define CONFIG_ENV_SPI_MODE 0 67 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 68 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 69 #define CONFIG_ENV_SECT_SIZE 0x10000 70 #elif defined(CONFIG_SDCARD) 71 #define CONFIG_FSL_FIXED_MMC_LOCATION 72 #define CONFIG_SYS_MMC_ENV_DEV 0 73 #define CONFIG_ENV_SIZE 0x2000 74 #define CONFIG_ENV_OFFSET (512 * 1658) 75 #elif defined(CONFIG_NAND) 76 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 77 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 78 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 79 #define CONFIG_ENV_ADDR 0xffe20000 80 #define CONFIG_ENV_SIZE 0x2000 81 #elif defined(CONFIG_ENV_IS_NOWHERE) 82 #define CONFIG_ENV_SIZE 0x2000 83 #else 84 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 85 #define CONFIG_ENV_SIZE 0x2000 86 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 87 #endif 88 89 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 90 91 /* 92 * These can be toggled for performance analysis, otherwise use default. 93 */ 94 #define CONFIG_SYS_CACHE_STASHING 95 #define CONFIG_BACKSIDE_L2_CACHE 96 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 97 #define CONFIG_BTB /* toggle branch predition */ 98 #define CONFIG_DDR_ECC 99 #ifdef CONFIG_DDR_ECC 100 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 101 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 102 #endif 103 104 #define CONFIG_ENABLE_36BIT_PHYS 105 106 #ifdef CONFIG_PHYS_64BIT 107 #define CONFIG_ADDR_MAP 108 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 109 #endif 110 111 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 112 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 113 #define CONFIG_SYS_MEMTEST_END 0x00400000 114 115 /* 116 * Config the L3 Cache as L3 SRAM 117 */ 118 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 119 #ifdef CONFIG_PHYS_64BIT 120 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) 121 #else 122 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 123 #endif 124 #define CONFIG_SYS_L3_SIZE (1024 << 10) 125 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 126 127 #ifdef CONFIG_PHYS_64BIT 128 #define CONFIG_SYS_DCSRBAR 0xf0000000 129 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 130 #endif 131 132 /* EEPROM */ 133 #define CONFIG_ID_EEPROM 134 #define CONFIG_SYS_I2C_EEPROM_NXID 135 #define CONFIG_SYS_EEPROM_BUS_NUM 0 136 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 137 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 138 139 /* 140 * DDR Setup 141 */ 142 #define CONFIG_VERY_BIG_RAM 143 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 144 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 145 146 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 147 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 148 149 #define CONFIG_DDR_SPD 150 151 #define CONFIG_SYS_SPD_BUS_NUM 1 152 #define SPD_EEPROM_ADDRESS1 0x51 153 #define SPD_EEPROM_ADDRESS2 0x52 154 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 155 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 156 157 /* 158 * Local Bus Definitions 159 */ 160 161 /* Set the local bus clock 1/8 of platform clock */ 162 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 163 164 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */ 165 #ifdef CONFIG_PHYS_64BIT 166 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 167 #else 168 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 169 #endif 170 171 #define CONFIG_SYS_FLASH_BR_PRELIM \ 172 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \ 173 | BR_PS_16 | BR_V) 174 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 175 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 176 177 #define CONFIG_SYS_BR1_PRELIM \ 178 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 179 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 180 181 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 182 #ifdef CONFIG_PHYS_64BIT 183 #define PIXIS_BASE_PHYS 0xfffdf0000ull 184 #else 185 #define PIXIS_BASE_PHYS PIXIS_BASE 186 #endif 187 188 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 189 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 190 191 #define PIXIS_LBMAP_SWITCH 7 192 #define PIXIS_LBMAP_MASK 0xf0 193 #define PIXIS_LBMAP_SHIFT 4 194 #define PIXIS_LBMAP_ALTBANK 0x40 195 196 #define CONFIG_SYS_FLASH_QUIET_TEST 197 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 198 199 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 200 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 201 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 202 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 203 204 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 205 206 #if defined(CONFIG_RAMBOOT_PBL) 207 #define CONFIG_SYS_RAMBOOT 208 #endif 209 210 /* Nand Flash */ 211 #ifdef CONFIG_NAND_FSL_ELBC 212 #define CONFIG_SYS_NAND_BASE 0xffa00000 213 #ifdef CONFIG_PHYS_64BIT 214 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 215 #else 216 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 217 #endif 218 219 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 220 #define CONFIG_SYS_MAX_NAND_DEVICE 1 221 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 222 223 /* NAND flash config */ 224 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 225 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 226 | BR_PS_8 /* Port Size = 8 bit */ \ 227 | BR_MS_FCM /* MSEL = FCM */ \ 228 | BR_V) /* valid */ 229 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 230 | OR_FCM_PGS /* Large Page*/ \ 231 | OR_FCM_CSCT \ 232 | OR_FCM_CST \ 233 | OR_FCM_CHT \ 234 | OR_FCM_SCY_1 \ 235 | OR_FCM_TRLX \ 236 | OR_FCM_EHTR) 237 238 #ifdef CONFIG_NAND 239 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 240 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 241 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 242 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 243 #else 244 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 245 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 246 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 247 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 248 #endif 249 #else 250 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 251 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 252 #endif /* CONFIG_NAND_FSL_ELBC */ 253 254 #define CONFIG_SYS_FLASH_EMPTY_INFO 255 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 256 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 257 258 #define CONFIG_HWCONFIG 259 260 /* define to use L1 as initial stack */ 261 #define CONFIG_L1_INIT_RAM 262 #define CONFIG_SYS_INIT_RAM_LOCK 263 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 264 #ifdef CONFIG_PHYS_64BIT 265 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 266 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 267 /* The assembler doesn't like typecast */ 268 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 269 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 270 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 271 #else 272 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ 273 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 274 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 275 #endif 276 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 277 278 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 279 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 280 281 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 282 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 283 284 /* Serial Port - controlled on board with jumper J8 285 * open - index 2 286 * shorted - index 1 287 */ 288 #define CONFIG_SYS_NS16550_SERIAL 289 #define CONFIG_SYS_NS16550_REG_SIZE 1 290 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 291 292 #define CONFIG_SYS_BAUDRATE_TABLE \ 293 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 294 295 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 296 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 297 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 298 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 299 300 /* I2C */ 301 #define CONFIG_SYS_I2C 302 #define CONFIG_SYS_I2C_FSL 303 #define CONFIG_SYS_FSL_I2C_SPEED 400000 304 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 305 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 306 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 307 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 308 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 309 310 /* 311 * RapidIO 312 */ 313 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 314 #ifdef CONFIG_PHYS_64BIT 315 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 316 #else 317 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 318 #endif 319 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 320 321 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 322 #ifdef CONFIG_PHYS_64BIT 323 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 324 #else 325 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 326 #endif 327 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 328 329 /* 330 * for slave u-boot IMAGE instored in master memory space, 331 * PHYS must be aligned based on the SIZE 332 */ 333 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 334 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 335 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 336 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 337 /* 338 * for slave UCODE and ENV instored in master memory space, 339 * PHYS must be aligned based on the SIZE 340 */ 341 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 342 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 343 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 344 345 /* slave core release by master*/ 346 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 347 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 348 349 /* 350 * SRIO_PCIE_BOOT - SLAVE 351 */ 352 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 353 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 354 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 355 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 356 #endif 357 358 /* 359 * eSPI - Enhanced SPI 360 */ 361 #define CONFIG_SF_DEFAULT_SPEED 10000000 362 #define CONFIG_SF_DEFAULT_MODE 0 363 364 /* 365 * General PCI 366 * Memory space is mapped 1-1, but I/O space must start from 0. 367 */ 368 369 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 370 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 371 #ifdef CONFIG_PHYS_64BIT 372 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 373 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 374 #else 375 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 376 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 377 #endif 378 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 379 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 380 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 381 #ifdef CONFIG_PHYS_64BIT 382 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 383 #else 384 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 385 #endif 386 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 387 388 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 389 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 390 #ifdef CONFIG_PHYS_64BIT 391 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 392 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 393 #else 394 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 395 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 396 #endif 397 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 398 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 399 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 400 #ifdef CONFIG_PHYS_64BIT 401 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 402 #else 403 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 404 #endif 405 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 406 407 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 408 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 409 #ifdef CONFIG_PHYS_64BIT 410 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 411 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 412 #else 413 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 414 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 415 #endif 416 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 417 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 418 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 419 #ifdef CONFIG_PHYS_64BIT 420 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 421 #else 422 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 423 #endif 424 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 425 426 /* controller 4, Base address 203000 */ 427 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 428 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 429 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 430 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 431 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 432 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 433 434 /* Qman/Bman */ 435 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 436 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 437 #ifdef CONFIG_PHYS_64BIT 438 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 439 #else 440 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 441 #endif 442 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 443 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 444 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 445 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 446 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 447 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 448 CONFIG_SYS_BMAN_CENA_SIZE) 449 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 450 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 451 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 452 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 453 #ifdef CONFIG_PHYS_64BIT 454 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 455 #else 456 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 457 #endif 458 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 459 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 460 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 461 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 462 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 463 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 464 CONFIG_SYS_QMAN_CENA_SIZE) 465 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 466 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 467 468 #define CONFIG_SYS_DPAA_FMAN 469 #define CONFIG_SYS_DPAA_PME 470 /* Default address of microcode for the Linux Fman driver */ 471 #if defined(CONFIG_SPIFLASH) 472 /* 473 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 474 * env, so we got 0x110000. 475 */ 476 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 477 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 478 #elif defined(CONFIG_SDCARD) 479 /* 480 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 481 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 482 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 483 */ 484 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 485 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 486 #elif defined(CONFIG_NAND) 487 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 488 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 489 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 490 /* 491 * Slave has no ucode locally, it can fetch this from remote. When implementing 492 * in two corenet boards, slave's ucode could be stored in master's memory 493 * space, the address can be mapped from slave TLB->slave LAW-> 494 * slave SRIO or PCIE outbound window->master inbound window-> 495 * master LAW->the ucode address in master's memory space. 496 */ 497 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 498 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 499 #else 500 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 501 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 502 #endif 503 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 504 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 505 506 #ifdef CONFIG_SYS_DPAA_FMAN 507 #define CONFIG_FMAN_ENET 508 #define CONFIG_PHYLIB_10G 509 #define CONFIG_PHY_VITESSE 510 #define CONFIG_PHY_TERANETICS 511 #endif 512 513 #ifdef CONFIG_PCI 514 #define CONFIG_PCI_INDIRECT_BRIDGE 515 516 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 517 #endif /* CONFIG_PCI */ 518 519 /* SATA */ 520 #ifdef CONFIG_FSL_SATA_V2 521 #define CONFIG_SYS_SATA_MAX_DEVICE 2 522 #define CONFIG_SATA1 523 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 524 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 525 #define CONFIG_SATA2 526 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 527 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 528 529 #define CONFIG_LBA48 530 #endif 531 532 #ifdef CONFIG_FMAN_ENET 533 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c 534 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d 535 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e 536 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f 537 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 538 539 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c 540 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d 541 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e 542 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f 543 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0 544 545 #define CONFIG_SYS_TBIPA_VALUE 8 546 #define CONFIG_ETHPRIME "FM1@DTSEC1" 547 #endif 548 549 /* 550 * Environment 551 */ 552 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 553 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 554 555 /* 556 * USB 557 */ 558 #define CONFIG_HAS_FSL_DR_USB 559 #define CONFIG_HAS_FSL_MPH_USB 560 561 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 562 #define CONFIG_USB_EHCI_FSL 563 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 564 #endif 565 566 #ifdef CONFIG_MMC 567 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 568 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 569 #endif 570 571 /* 572 * Miscellaneous configurable options 573 */ 574 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 575 576 /* 577 * For booting Linux, the board info and command line data 578 * have to be in the first 64 MB of memory, since this is 579 * the maximum mapped by the Linux kernel during initialization. 580 */ 581 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 582 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 583 584 #ifdef CONFIG_CMD_KGDB 585 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 586 #endif 587 588 /* 589 * Environment Configuration 590 */ 591 #define CONFIG_ROOTPATH "/opt/nfsroot" 592 #define CONFIG_BOOTFILE "uImage" 593 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 594 595 /* default location for tftp and bootm */ 596 #define CONFIG_LOADADDR 1000000 597 598 #ifdef CONFIG_TARGET_P4080DS 599 #define __USB_PHY_TYPE ulpi 600 #else 601 #define __USB_PHY_TYPE utmi 602 #endif 603 604 #define CONFIG_EXTRA_ENV_SETTINGS \ 605 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 606 "bank_intlv=cs0_cs1;" \ 607 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 608 "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 609 "netdev=eth0\0" \ 610 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 611 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 612 "tftpflash=tftpboot $loadaddr $uboot && " \ 613 "protect off $ubootaddr +$filesize && " \ 614 "erase $ubootaddr +$filesize && " \ 615 "cp.b $loadaddr $ubootaddr $filesize && " \ 616 "protect on $ubootaddr +$filesize && " \ 617 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 618 "consoledev=ttyS0\0" \ 619 "ramdiskaddr=2000000\0" \ 620 "ramdiskfile=p4080ds/ramdisk.uboot\0" \ 621 "fdtaddr=1e00000\0" \ 622 "fdtfile=p4080ds/p4080ds.dtb\0" \ 623 "bdev=sda3\0" 624 625 #define CONFIG_HDBOOT \ 626 "setenv bootargs root=/dev/$bdev rw " \ 627 "console=$consoledev,$baudrate $othbootargs;" \ 628 "tftp $loadaddr $bootfile;" \ 629 "tftp $fdtaddr $fdtfile;" \ 630 "bootm $loadaddr - $fdtaddr" 631 632 #define CONFIG_NFSBOOTCOMMAND \ 633 "setenv bootargs root=/dev/nfs rw " \ 634 "nfsroot=$serverip:$rootpath " \ 635 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 636 "console=$consoledev,$baudrate $othbootargs;" \ 637 "tftp $loadaddr $bootfile;" \ 638 "tftp $fdtaddr $fdtfile;" \ 639 "bootm $loadaddr - $fdtaddr" 640 641 #define CONFIG_RAMBOOTCOMMAND \ 642 "setenv bootargs root=/dev/ram rw " \ 643 "console=$consoledev,$baudrate $othbootargs;" \ 644 "tftp $ramdiskaddr $ramdiskfile;" \ 645 "tftp $loadaddr $bootfile;" \ 646 "tftp $fdtaddr $fdtfile;" \ 647 "bootm $loadaddr $ramdiskaddr $fdtaddr" 648 649 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 650 651 #include <asm/fsl_secure_boot.h> 652 653 #endif /* __CONFIG_H */ 654