xref: /openbmc/u-boot/include/configs/corenet_ds.h (revision e0a0cbf2)
1 /*
2  * Copyright 2009-2012 Freescale Semiconductor, Inc.
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20  * MA 02111-1307 USA
21  */
22 
23 /*
24  * Corenet DS style board configuration file
25  */
26 #ifndef __CONFIG_H
27 #define __CONFIG_H
28 
29 #include "../board/freescale/common/ics307_clk.h"
30 
31 #ifdef CONFIG_RAMBOOT_PBL
32 #define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
33 #define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
34 #define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg
35 #if defined(CONFIG_P3041DS)
36 #define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p3041ds.cfg
37 #elif defined(CONFIG_P4080DS)
38 #define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p4080ds.cfg
39 #elif defined(CONFIG_P5020DS)
40 #define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p5020ds.cfg
41 #endif
42 #endif
43 
44 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
45 /* Set 1M boot space */
46 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
47 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
48 		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
49 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
50 #define CONFIG_SYS_NO_FLASH
51 #endif
52 
53 /* High Level Configuration Options */
54 #define CONFIG_BOOKE
55 #define CONFIG_E500			/* BOOKE e500 family */
56 #define CONFIG_E500MC			/* BOOKE e500mc family */
57 #define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
58 #define CONFIG_MPC85xx			/* MPC85xx/PQ3 platform */
59 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
60 #define CONFIG_MP			/* support multiple processors */
61 
62 #ifndef CONFIG_SYS_TEXT_BASE
63 #define CONFIG_SYS_TEXT_BASE	0xeff80000
64 #endif
65 
66 #ifndef CONFIG_RESET_VECTOR_ADDRESS
67 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
68 #endif
69 
70 #define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
71 #define CONFIG_SYS_NUM_CPC		CONFIG_NUM_DDR_CONTROLLERS
72 #define CONFIG_FSL_ELBC			/* Has Enhanced localbus controller */
73 #define CONFIG_PCI			/* Enable PCI/PCIE */
74 #define CONFIG_PCIE1			/* PCIE controler 1 */
75 #define CONFIG_PCIE2			/* PCIE controler 2 */
76 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
77 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
78 
79 #define CONFIG_FSL_LAW			/* Use common FSL init code */
80 
81 #define CONFIG_ENV_OVERWRITE
82 
83 #ifdef CONFIG_SYS_NO_FLASH
84 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
85 #define CONFIG_ENV_IS_NOWHERE
86 #endif
87 #else
88 #define CONFIG_FLASH_CFI_DRIVER
89 #define CONFIG_SYS_FLASH_CFI
90 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
91 #endif
92 
93 #if defined(CONFIG_SPIFLASH)
94 #define CONFIG_SYS_EXTRA_ENV_RELOC
95 #define CONFIG_ENV_IS_IN_SPI_FLASH
96 #define CONFIG_ENV_SPI_BUS              0
97 #define CONFIG_ENV_SPI_CS               0
98 #define CONFIG_ENV_SPI_MAX_HZ           10000000
99 #define CONFIG_ENV_SPI_MODE             0
100 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
101 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
102 #define CONFIG_ENV_SECT_SIZE            0x10000
103 #elif defined(CONFIG_SDCARD)
104 #define CONFIG_SYS_EXTRA_ENV_RELOC
105 #define CONFIG_ENV_IS_IN_MMC
106 #define CONFIG_FSL_FIXED_MMC_LOCATION
107 #define CONFIG_SYS_MMC_ENV_DEV          0
108 #define CONFIG_ENV_SIZE			0x2000
109 #define CONFIG_ENV_OFFSET		(512 * 1097)
110 #elif defined(CONFIG_NAND)
111 #define CONFIG_SYS_EXTRA_ENV_RELOC
112 #define CONFIG_ENV_IS_IN_NAND
113 #define CONFIG_ENV_SIZE			CONFIG_SYS_NAND_BLOCK_SIZE
114 #define CONFIG_ENV_OFFSET		(5 * CONFIG_SYS_NAND_BLOCK_SIZE)
115 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
116 #define CONFIG_ENV_IS_IN_REMOTE
117 #define CONFIG_ENV_ADDR		0xffe20000
118 #define CONFIG_ENV_SIZE		0x2000
119 #elif defined(CONFIG_ENV_IS_NOWHERE)
120 #define CONFIG_ENV_SIZE		0x2000
121 #else
122 #define CONFIG_ENV_IS_IN_FLASH
123 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
124 #define CONFIG_ENV_SIZE		0x2000
125 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
126 #endif
127 
128 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk() /* sysclk for MPC85xx */
129 
130 /*
131  * These can be toggled for performance analysis, otherwise use default.
132  */
133 #define CONFIG_SYS_CACHE_STASHING
134 #define CONFIG_BACKSIDE_L2_CACHE
135 #define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
136 #define CONFIG_BTB			/* toggle branch predition */
137 #define	CONFIG_DDR_ECC
138 #ifdef CONFIG_DDR_ECC
139 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
140 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
141 #endif
142 
143 #define CONFIG_ENABLE_36BIT_PHYS
144 
145 #ifdef CONFIG_PHYS_64BIT
146 #define CONFIG_ADDR_MAP
147 #define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
148 #endif
149 
150 #define CONFIG_POST CONFIG_SYS_POST_MEMORY	/* test POST memory test */
151 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
152 #define CONFIG_SYS_MEMTEST_END		0x00400000
153 #define CONFIG_SYS_ALT_MEMTEST
154 #define CONFIG_PANIC_HANG	/* do not reset board on panic */
155 
156 /*
157  *  Config the L3 Cache as L3 SRAM
158  */
159 #define CONFIG_SYS_INIT_L3_ADDR		CONFIG_RAMBOOT_TEXT_BASE
160 #ifdef CONFIG_PHYS_64BIT
161 #define CONFIG_SYS_INIT_L3_ADDR_PHYS	(0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
162 #else
163 #define CONFIG_SYS_INIT_L3_ADDR_PHYS	CONFIG_SYS_INIT_L3_ADDR
164 #endif
165 #define CONFIG_SYS_L3_SIZE		(1024 << 10)
166 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
167 
168 #ifdef CONFIG_PHYS_64BIT
169 #define CONFIG_SYS_DCSRBAR		0xf0000000
170 #define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
171 #endif
172 
173 /* EEPROM */
174 #define CONFIG_ID_EEPROM
175 #define CONFIG_SYS_I2C_EEPROM_NXID
176 #define CONFIG_SYS_EEPROM_BUS_NUM	0
177 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
178 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
179 
180 /*
181  * DDR Setup
182  */
183 #define CONFIG_VERY_BIG_RAM
184 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
185 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
186 
187 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
188 #define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
189 
190 #define CONFIG_DDR_SPD
191 #define CONFIG_FSL_DDR3
192 
193 #define CONFIG_SYS_SPD_BUS_NUM	1
194 #define SPD_EEPROM_ADDRESS1	0x51
195 #define SPD_EEPROM_ADDRESS2	0x52
196 #define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1	/* for p3041/p5010 */
197 #define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
198 
199 /*
200  * Local Bus Definitions
201  */
202 
203 /* Set the local bus clock 1/8 of platform clock */
204 #define CONFIG_SYS_LBC_LCRR		LCRR_CLKDIV_8
205 
206 #define CONFIG_SYS_FLASH_BASE		0xe0000000	/* Start of PromJet */
207 #ifdef CONFIG_PHYS_64BIT
208 #define CONFIG_SYS_FLASH_BASE_PHYS	0xfe0000000ull
209 #else
210 #define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
211 #endif
212 
213 #define CONFIG_SYS_FLASH_BR_PRELIM \
214 		(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
215 		 | BR_PS_16 | BR_V)
216 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
217 					| OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
218 
219 #define CONFIG_SYS_BR1_PRELIM \
220 	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
221 #define CONFIG_SYS_OR1_PRELIM	0xf8000ff7
222 
223 #define PIXIS_BASE		0xffdf0000	/* PIXIS registers */
224 #ifdef CONFIG_PHYS_64BIT
225 #define PIXIS_BASE_PHYS		0xfffdf0000ull
226 #else
227 #define PIXIS_BASE_PHYS		PIXIS_BASE
228 #endif
229 
230 #define CONFIG_SYS_BR3_PRELIM	(BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
231 #define CONFIG_SYS_OR3_PRELIM	0xffffeff7	/* 32KB but only 4k mapped */
232 
233 #define PIXIS_LBMAP_SWITCH	7
234 #define PIXIS_LBMAP_MASK	0xf0
235 #define PIXIS_LBMAP_SHIFT	4
236 #define PIXIS_LBMAP_ALTBANK	0x40
237 
238 #define CONFIG_SYS_FLASH_QUIET_TEST
239 #define CONFIG_FLASH_SHOW_PROGRESS 	45 /* count down from 45/5: 9..1 */
240 
241 #define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
242 #define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
243 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
244 #define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
245 
246 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE	/* start of monitor */
247 
248 #if defined(CONFIG_RAMBOOT_PBL)
249 #define CONFIG_SYS_RAMBOOT
250 #endif
251 
252 /* Nand Flash */
253 #ifdef CONFIG_NAND_FSL_ELBC
254 #define CONFIG_SYS_NAND_BASE		0xffa00000
255 #ifdef CONFIG_PHYS_64BIT
256 #define CONFIG_SYS_NAND_BASE_PHYS	0xfffa00000ull
257 #else
258 #define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
259 #endif
260 
261 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
262 #define CONFIG_SYS_MAX_NAND_DEVICE	1
263 #define CONFIG_MTD_NAND_VERIFY_WRITE
264 #define CONFIG_CMD_NAND
265 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
266 
267 /* NAND flash config */
268 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
269 			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
270 			       | BR_PS_8	       /* Port Size = 8 bit */ \
271 			       | BR_MS_FCM	       /* MSEL = FCM */ \
272 			       | BR_V)		       /* valid */
273 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000	      /* length 256K */ \
274 			       | OR_FCM_PGS	       /* Large Page*/ \
275 			       | OR_FCM_CSCT \
276 			       | OR_FCM_CST \
277 			       | OR_FCM_CHT \
278 			       | OR_FCM_SCY_1 \
279 			       | OR_FCM_TRLX \
280 			       | OR_FCM_EHTR)
281 
282 #ifdef CONFIG_NAND
283 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
284 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
285 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
286 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
287 #else
288 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
289 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
290 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
291 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
292 #endif
293 #else
294 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
295 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
296 #endif /* CONFIG_NAND_FSL_ELBC */
297 
298 #define CONFIG_SYS_FLASH_EMPTY_INFO
299 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
300 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
301 
302 #define CONFIG_BOARD_EARLY_INIT_F
303 #define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
304 #define CONFIG_MISC_INIT_R
305 
306 #define CONFIG_HWCONFIG
307 
308 /* define to use L1 as initial stack */
309 #define CONFIG_L1_INIT_RAM
310 #define CONFIG_SYS_INIT_RAM_LOCK
311 #define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
312 #ifdef CONFIG_PHYS_64BIT
313 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
314 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
315 /* The assembler doesn't like typecast */
316 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
317 	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
318 	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
319 #else
320 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS	CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
321 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
322 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
323 #endif
324 #define CONFIG_SYS_INIT_RAM_SIZE		0x00004000	/* Size of used area in RAM */
325 
326 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
327 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
328 
329 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
330 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
331 
332 /* Serial Port - controlled on board with jumper J8
333  * open - index 2
334  * shorted - index 1
335  */
336 #define CONFIG_CONS_INDEX	1
337 #define CONFIG_SYS_NS16550
338 #define CONFIG_SYS_NS16550_SERIAL
339 #define CONFIG_SYS_NS16550_REG_SIZE	1
340 #define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
341 
342 #define CONFIG_SYS_BAUDRATE_TABLE	\
343 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
344 
345 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
346 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
347 #define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
348 #define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
349 
350 /* Use the HUSH parser */
351 #define CONFIG_SYS_HUSH_PARSER
352 
353 /* pass open firmware flat tree */
354 #define CONFIG_OF_LIBFDT
355 #define CONFIG_OF_BOARD_SETUP
356 #define CONFIG_OF_STDOUT_VIA_ALIAS
357 
358 /* new uImage format support */
359 #define CONFIG_FIT
360 #define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
361 
362 /* I2C */
363 #define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
364 #define CONFIG_HARD_I2C		/* I2C with hardware support */
365 #define CONFIG_I2C_MULTI_BUS
366 #define CONFIG_I2C_CMD_TREE
367 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
368 #define CONFIG_SYS_I2C_SLAVE		0x7F
369 #define CONFIG_SYS_I2C_OFFSET		0x118000
370 #define CONFIG_SYS_I2C2_OFFSET		0x118100
371 
372 /*
373  * RapidIO
374  */
375 #define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
376 #ifdef CONFIG_PHYS_64BIT
377 #define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
378 #else
379 #define CONFIG_SYS_SRIO1_MEM_PHYS	0xa0000000
380 #endif
381 #define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000	/* 256M */
382 
383 #define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
384 #ifdef CONFIG_PHYS_64BIT
385 #define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
386 #else
387 #define CONFIG_SYS_SRIO2_MEM_PHYS	0xb0000000
388 #endif
389 #define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000	/* 256M */
390 
391 /*
392  * for slave u-boot IMAGE instored in master memory space,
393  * PHYS must be aligned based on the SIZE
394  */
395 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
396 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
397 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000	/* 512K */
398 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
399 /*
400  * for slave UCODE and ENV instored in master memory space,
401  * PHYS must be aligned based on the SIZE
402  */
403 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
404 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
405 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000	/* 256K */
406 
407 /* slave core release by master*/
408 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
409 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
410 
411 /*
412  * SRIO_PCIE_BOOT - SLAVE
413  */
414 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
415 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
416 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
417 		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
418 #endif
419 
420 /*
421  * eSPI - Enhanced SPI
422  */
423 #define CONFIG_FSL_ESPI
424 #define CONFIG_SPI_FLASH
425 #define CONFIG_SPI_FLASH_SPANSION
426 #define CONFIG_CMD_SF
427 #define CONFIG_SF_DEFAULT_SPEED         10000000
428 #define CONFIG_SF_DEFAULT_MODE          0
429 
430 /*
431  * General PCI
432  * Memory space is mapped 1-1, but I/O space must start from 0.
433  */
434 
435 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
436 #define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
437 #ifdef CONFIG_PHYS_64BIT
438 #define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
439 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
440 #else
441 #define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
442 #define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
443 #endif
444 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
445 #define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
446 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
447 #ifdef CONFIG_PHYS_64BIT
448 #define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
449 #else
450 #define CONFIG_SYS_PCIE1_IO_PHYS	0xf8000000
451 #endif
452 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
453 
454 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
455 #define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
456 #ifdef CONFIG_PHYS_64BIT
457 #define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
458 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
459 #else
460 #define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
461 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
462 #endif
463 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
464 #define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
465 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
466 #ifdef CONFIG_PHYS_64BIT
467 #define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
468 #else
469 #define CONFIG_SYS_PCIE2_IO_PHYS	0xf8010000
470 #endif
471 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
472 
473 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
474 #define CONFIG_SYS_PCIE3_MEM_VIRT	0xc0000000
475 #ifdef CONFIG_PHYS_64BIT
476 #define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
477 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xc40000000ull
478 #else
479 #define CONFIG_SYS_PCIE3_MEM_BUS	0xc0000000
480 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xc0000000
481 #endif
482 #define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
483 #define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
484 #define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
485 #ifdef CONFIG_PHYS_64BIT
486 #define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
487 #else
488 #define CONFIG_SYS_PCIE3_IO_PHYS	0xf8020000
489 #endif
490 #define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
491 
492 /* controller 4, Base address 203000 */
493 #define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
494 #define CONFIG_SYS_PCIE4_MEM_PHYS	0xc60000000ull
495 #define CONFIG_SYS_PCIE4_MEM_SIZE	0x20000000	/* 512M */
496 #define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
497 #define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
498 #define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
499 
500 /* Qman/Bman */
501 #define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
502 #define CONFIG_SYS_BMAN_NUM_PORTALS	10
503 #define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
504 #ifdef CONFIG_PHYS_64BIT
505 #define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
506 #else
507 #define CONFIG_SYS_BMAN_MEM_PHYS	CONFIG_SYS_BMAN_MEM_BASE
508 #endif
509 #define CONFIG_SYS_BMAN_MEM_SIZE	0x00200000
510 #define CONFIG_SYS_QMAN_NUM_PORTALS	10
511 #define CONFIG_SYS_QMAN_MEM_BASE	0xf4200000
512 #ifdef CONFIG_PHYS_64BIT
513 #define CONFIG_SYS_QMAN_MEM_PHYS	0xff4200000ull
514 #else
515 #define CONFIG_SYS_QMAN_MEM_PHYS	CONFIG_SYS_QMAN_MEM_BASE
516 #endif
517 #define CONFIG_SYS_QMAN_MEM_SIZE	0x00200000
518 
519 #define CONFIG_SYS_DPAA_FMAN
520 #define CONFIG_SYS_DPAA_PME
521 /* Default address of microcode for the Linux Fman driver */
522 #if defined(CONFIG_SPIFLASH)
523 /*
524  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
525  * env, so we got 0x110000.
526  */
527 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
528 #define CONFIG_SYS_QE_FMAN_FW_ADDR	0x110000
529 #elif defined(CONFIG_SDCARD)
530 /*
531  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
532  * about 545KB (1089 blocks), Env is stored after the image, and the env size is
533  * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
534  */
535 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
536 #define CONFIG_SYS_QE_FMAN_FW_ADDR	(512 * 1130)
537 #elif defined(CONFIG_NAND)
538 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
539 #define CONFIG_SYS_QE_FMAN_FW_ADDR	(6 * CONFIG_SYS_NAND_BLOCK_SIZE)
540 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
541 /*
542  * Slave has no ucode locally, it can fetch this from remote. When implementing
543  * in two corenet boards, slave's ucode could be stored in master's memory
544  * space, the address can be mapped from slave TLB->slave LAW->
545  * slave SRIO or PCIE outbound window->master inbound window->
546  * master LAW->the ucode address in master's memory space.
547  */
548 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
549 #define CONFIG_SYS_QE_FMAN_FW_ADDR	0xFFE00000
550 #else
551 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
552 #define CONFIG_SYS_QE_FMAN_FW_ADDR		0xEF000000
553 #endif
554 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
555 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
556 
557 #ifdef CONFIG_SYS_DPAA_FMAN
558 #define CONFIG_FMAN_ENET
559 #define CONFIG_PHYLIB_10G
560 #define CONFIG_PHY_VITESSE
561 #define CONFIG_PHY_TERANETICS
562 #endif
563 
564 #ifdef CONFIG_PCI
565 #define CONFIG_PCI_PNP			/* do pci plug-and-play */
566 #define CONFIG_E1000
567 
568 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
569 #define CONFIG_DOS_PARTITION
570 #endif	/* CONFIG_PCI */
571 
572 /* SATA */
573 #ifdef CONFIG_FSL_SATA_V2
574 #define CONFIG_LIBATA
575 #define CONFIG_FSL_SATA
576 
577 #define CONFIG_SYS_SATA_MAX_DEVICE	2
578 #define CONFIG_SATA1
579 #define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
580 #define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
581 #define CONFIG_SATA2
582 #define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
583 #define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
584 
585 #define CONFIG_LBA48
586 #define CONFIG_CMD_SATA
587 #define CONFIG_DOS_PARTITION
588 #define CONFIG_CMD_EXT2
589 #endif
590 
591 #ifdef CONFIG_FMAN_ENET
592 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR	0x1c
593 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR	0x1d
594 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR	0x1e
595 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR	0x1f
596 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR	4
597 
598 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR	0x1c
599 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR	0x1d
600 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR	0x1e
601 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR	0x1f
602 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR	0
603 
604 #define CONFIG_SYS_TBIPA_VALUE	8
605 #define CONFIG_MII		/* MII PHY management */
606 #define CONFIG_ETHPRIME		"FM1@DTSEC1"
607 #define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
608 #endif
609 
610 /*
611  * Environment
612  */
613 #define CONFIG_LOADS_ECHO		/* echo on for serial download */
614 #define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
615 
616 /*
617  * Command line configuration.
618  */
619 #include <config_cmd_default.h>
620 
621 #define CONFIG_CMD_DHCP
622 #define CONFIG_CMD_ELF
623 #define CONFIG_CMD_ERRATA
624 #define CONFIG_CMD_GREPENV
625 #define CONFIG_CMD_IRQ
626 #define CONFIG_CMD_I2C
627 #define CONFIG_CMD_MII
628 #define CONFIG_CMD_PING
629 #define CONFIG_CMD_SETEXPR
630 #define CONFIG_CMD_REGINFO
631 
632 #ifdef CONFIG_PCI
633 #define CONFIG_CMD_PCI
634 #define CONFIG_CMD_NET
635 #endif
636 
637 /*
638 * USB
639 */
640 #define CONFIG_HAS_FSL_DR_USB
641 #define CONFIG_HAS_FSL_MPH_USB
642 
643 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
644 #define CONFIG_CMD_USB
645 #define CONFIG_USB_STORAGE
646 #define CONFIG_USB_EHCI
647 #define CONFIG_USB_EHCI_FSL
648 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
649 #define CONFIG_CMD_EXT2
650 #endif
651 
652 #ifdef CONFIG_MMC
653 #define CONFIG_FSL_ESDHC
654 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
655 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
656 #define CONFIG_CMD_MMC
657 #define CONFIG_GENERIC_MMC
658 #define CONFIG_CMD_EXT2
659 #define CONFIG_CMD_FAT
660 #define CONFIG_DOS_PARTITION
661 #endif
662 
663 /*
664  * Miscellaneous configurable options
665  */
666 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
667 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
668 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
669 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
670 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
671 #ifdef CONFIG_CMD_KGDB
672 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
673 #else
674 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
675 #endif
676 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
677 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
678 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
679 #define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
680 
681 /*
682  * For booting Linux, the board info and command line data
683  * have to be in the first 64 MB of memory, since this is
684  * the maximum mapped by the Linux kernel during initialization.
685  */
686 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
687 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
688 
689 #ifdef CONFIG_CMD_KGDB
690 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
691 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
692 #endif
693 
694 /*
695  * Environment Configuration
696  */
697 #define CONFIG_ROOTPATH		"/opt/nfsroot"
698 #define CONFIG_BOOTFILE		"uImage"
699 #define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
700 
701 /* default location for tftp and bootm */
702 #define CONFIG_LOADADDR		1000000
703 
704 #define CONFIG_BOOTDELAY 	10	/* -1 disables auto-boot */
705 
706 #define CONFIG_BAUDRATE	115200
707 
708 #ifdef CONFIG_P4080DS
709 #define __USB_PHY_TYPE	ulpi
710 #else
711 #define __USB_PHY_TYPE	utmi
712 #endif
713 
714 #define	CONFIG_EXTRA_ENV_SETTINGS				\
715 	"hwconfig=fsl_ddr:ctlr_intlv=cacheline,"		\
716 	"bank_intlv=cs0_cs1;"					\
717 	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
718 	"netdev=eth0\0"						\
719 	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
720 	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
721 	"tftpflash=tftpboot $loadaddr $uboot && "		\
722 	"protect off $ubootaddr +$filesize && "			\
723 	"erase $ubootaddr +$filesize && "			\
724 	"cp.b $loadaddr $ubootaddr $filesize && "		\
725 	"protect on $ubootaddr +$filesize && "			\
726 	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
727 	"consoledev=ttyS0\0"					\
728 	"ramdiskaddr=2000000\0"					\
729 	"ramdiskfile=p4080ds/ramdisk.uboot\0"			\
730 	"fdtaddr=c00000\0"					\
731 	"fdtfile=p4080ds/p4080ds.dtb\0"				\
732 	"bdev=sda3\0"						\
733 	"c=ffe\0"
734 
735 #define CONFIG_HDBOOT					\
736 	"setenv bootargs root=/dev/$bdev rw "		\
737 	"console=$consoledev,$baudrate $othbootargs;"	\
738 	"tftp $loadaddr $bootfile;"			\
739 	"tftp $fdtaddr $fdtfile;"			\
740 	"bootm $loadaddr - $fdtaddr"
741 
742 #define CONFIG_NFSBOOTCOMMAND			\
743 	"setenv bootargs root=/dev/nfs rw "	\
744 	"nfsroot=$serverip:$rootpath "		\
745 	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
746 	"console=$consoledev,$baudrate $othbootargs;"	\
747 	"tftp $loadaddr $bootfile;"		\
748 	"tftp $fdtaddr $fdtfile;"		\
749 	"bootm $loadaddr - $fdtaddr"
750 
751 #define CONFIG_RAMBOOTCOMMAND				\
752 	"setenv bootargs root=/dev/ram rw "		\
753 	"console=$consoledev,$baudrate $othbootargs;"	\
754 	"tftp $ramdiskaddr $ramdiskfile;"		\
755 	"tftp $loadaddr $bootfile;"			\
756 	"tftp $fdtaddr $fdtfile;"			\
757 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
758 
759 #define CONFIG_BOOTCOMMAND		CONFIG_HDBOOT
760 
761 #ifdef CONFIG_SECURE_BOOT
762 #include <asm/fsl_secure_boot.h>
763 #endif
764 
765 #endif	/* __CONFIG_H */
766