1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2009-2012 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * Corenet DS style board configuration file 8 */ 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include "../board/freescale/common/ics307_clk.h" 13 14 #ifdef CONFIG_RAMBOOT_PBL 15 #ifdef CONFIG_SECURE_BOOT 16 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 17 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 18 #ifdef CONFIG_NAND 19 #define CONFIG_RAMBOOT_NAND 20 #endif 21 #define CONFIG_BOOTSCRIPT_COPY_RAM 22 #else 23 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 24 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 25 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg 26 #if defined(CONFIG_TARGET_P3041DS) 27 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg 28 #elif defined(CONFIG_TARGET_P4080DS) 29 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg 30 #elif defined(CONFIG_TARGET_P5020DS) 31 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg 32 #elif defined(CONFIG_TARGET_P5040DS) 33 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg 34 #endif 35 #endif 36 #endif 37 38 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 39 /* Set 1M boot space */ 40 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 41 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 42 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 43 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 44 #endif 45 46 /* High Level Configuration Options */ 47 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 48 49 #ifndef CONFIG_RESET_VECTOR_ADDRESS 50 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 51 #endif 52 53 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 54 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 55 #define CONFIG_PCIE1 /* PCIE controller 1 */ 56 #define CONFIG_PCIE2 /* PCIE controller 2 */ 57 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 58 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 59 60 #define CONFIG_ENV_OVERWRITE 61 62 #ifndef CONFIG_MTD_NOR_FLASH 63 #else 64 #define CONFIG_FLASH_CFI_DRIVER 65 #define CONFIG_SYS_FLASH_CFI 66 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 67 #endif 68 69 #if defined(CONFIG_SPIFLASH) 70 #define CONFIG_ENV_SPI_BUS 0 71 #define CONFIG_ENV_SPI_CS 0 72 #define CONFIG_ENV_SPI_MAX_HZ 10000000 73 #define CONFIG_ENV_SPI_MODE 0 74 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 75 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 76 #define CONFIG_ENV_SECT_SIZE 0x10000 77 #elif defined(CONFIG_SDCARD) 78 #define CONFIG_FSL_FIXED_MMC_LOCATION 79 #define CONFIG_SYS_MMC_ENV_DEV 0 80 #define CONFIG_ENV_SIZE 0x2000 81 #define CONFIG_ENV_OFFSET (512 * 1658) 82 #elif defined(CONFIG_NAND) 83 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 84 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 85 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 86 #define CONFIG_ENV_ADDR 0xffe20000 87 #define CONFIG_ENV_SIZE 0x2000 88 #elif defined(CONFIG_ENV_IS_NOWHERE) 89 #define CONFIG_ENV_SIZE 0x2000 90 #else 91 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 92 #define CONFIG_ENV_SIZE 0x2000 93 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 94 #endif 95 96 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 97 98 /* 99 * These can be toggled for performance analysis, otherwise use default. 100 */ 101 #define CONFIG_SYS_CACHE_STASHING 102 #define CONFIG_BACKSIDE_L2_CACHE 103 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 104 #define CONFIG_BTB /* toggle branch predition */ 105 #define CONFIG_DDR_ECC 106 #ifdef CONFIG_DDR_ECC 107 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 108 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 109 #endif 110 111 #define CONFIG_ENABLE_36BIT_PHYS 112 113 #ifdef CONFIG_PHYS_64BIT 114 #define CONFIG_ADDR_MAP 115 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 116 #endif 117 118 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 119 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 120 #define CONFIG_SYS_MEMTEST_END 0x00400000 121 122 /* 123 * Config the L3 Cache as L3 SRAM 124 */ 125 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 126 #ifdef CONFIG_PHYS_64BIT 127 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) 128 #else 129 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 130 #endif 131 #define CONFIG_SYS_L3_SIZE (1024 << 10) 132 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 133 134 #ifdef CONFIG_PHYS_64BIT 135 #define CONFIG_SYS_DCSRBAR 0xf0000000 136 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 137 #endif 138 139 /* EEPROM */ 140 #define CONFIG_ID_EEPROM 141 #define CONFIG_SYS_I2C_EEPROM_NXID 142 #define CONFIG_SYS_EEPROM_BUS_NUM 0 143 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 144 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 145 146 /* 147 * DDR Setup 148 */ 149 #define CONFIG_VERY_BIG_RAM 150 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 151 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 152 153 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 154 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 155 156 #define CONFIG_DDR_SPD 157 158 #define CONFIG_SYS_SPD_BUS_NUM 1 159 #define SPD_EEPROM_ADDRESS1 0x51 160 #define SPD_EEPROM_ADDRESS2 0x52 161 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 162 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 163 164 /* 165 * Local Bus Definitions 166 */ 167 168 /* Set the local bus clock 1/8 of platform clock */ 169 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 170 171 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */ 172 #ifdef CONFIG_PHYS_64BIT 173 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 174 #else 175 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 176 #endif 177 178 #define CONFIG_SYS_FLASH_BR_PRELIM \ 179 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \ 180 | BR_PS_16 | BR_V) 181 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 182 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 183 184 #define CONFIG_SYS_BR1_PRELIM \ 185 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 186 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 187 188 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 189 #ifdef CONFIG_PHYS_64BIT 190 #define PIXIS_BASE_PHYS 0xfffdf0000ull 191 #else 192 #define PIXIS_BASE_PHYS PIXIS_BASE 193 #endif 194 195 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 196 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 197 198 #define PIXIS_LBMAP_SWITCH 7 199 #define PIXIS_LBMAP_MASK 0xf0 200 #define PIXIS_LBMAP_SHIFT 4 201 #define PIXIS_LBMAP_ALTBANK 0x40 202 203 #define CONFIG_SYS_FLASH_QUIET_TEST 204 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 205 206 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 207 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 208 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 209 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 210 211 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 212 213 #if defined(CONFIG_RAMBOOT_PBL) 214 #define CONFIG_SYS_RAMBOOT 215 #endif 216 217 /* Nand Flash */ 218 #ifdef CONFIG_NAND_FSL_ELBC 219 #define CONFIG_SYS_NAND_BASE 0xffa00000 220 #ifdef CONFIG_PHYS_64BIT 221 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 222 #else 223 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 224 #endif 225 226 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 227 #define CONFIG_SYS_MAX_NAND_DEVICE 1 228 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 229 230 /* NAND flash config */ 231 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 232 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 233 | BR_PS_8 /* Port Size = 8 bit */ \ 234 | BR_MS_FCM /* MSEL = FCM */ \ 235 | BR_V) /* valid */ 236 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 237 | OR_FCM_PGS /* Large Page*/ \ 238 | OR_FCM_CSCT \ 239 | OR_FCM_CST \ 240 | OR_FCM_CHT \ 241 | OR_FCM_SCY_1 \ 242 | OR_FCM_TRLX \ 243 | OR_FCM_EHTR) 244 245 #ifdef CONFIG_NAND 246 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 247 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 248 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 249 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 250 #else 251 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 252 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 253 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 254 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 255 #endif 256 #else 257 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 258 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 259 #endif /* CONFIG_NAND_FSL_ELBC */ 260 261 #define CONFIG_SYS_FLASH_EMPTY_INFO 262 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 263 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 264 265 #define CONFIG_HWCONFIG 266 267 /* define to use L1 as initial stack */ 268 #define CONFIG_L1_INIT_RAM 269 #define CONFIG_SYS_INIT_RAM_LOCK 270 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 271 #ifdef CONFIG_PHYS_64BIT 272 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 273 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 274 /* The assembler doesn't like typecast */ 275 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 276 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 277 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 278 #else 279 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ 280 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 281 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 282 #endif 283 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 284 285 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 286 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 287 288 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 289 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 290 291 /* Serial Port - controlled on board with jumper J8 292 * open - index 2 293 * shorted - index 1 294 */ 295 #define CONFIG_SYS_NS16550_SERIAL 296 #define CONFIG_SYS_NS16550_REG_SIZE 1 297 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 298 299 #define CONFIG_SYS_BAUDRATE_TABLE \ 300 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 301 302 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 303 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 304 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 305 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 306 307 /* I2C */ 308 #define CONFIG_SYS_I2C 309 #define CONFIG_SYS_I2C_FSL 310 #define CONFIG_SYS_FSL_I2C_SPEED 400000 311 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 312 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 313 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 314 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 315 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 316 317 /* 318 * RapidIO 319 */ 320 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 321 #ifdef CONFIG_PHYS_64BIT 322 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 323 #else 324 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 325 #endif 326 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 327 328 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 329 #ifdef CONFIG_PHYS_64BIT 330 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 331 #else 332 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 333 #endif 334 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 335 336 /* 337 * for slave u-boot IMAGE instored in master memory space, 338 * PHYS must be aligned based on the SIZE 339 */ 340 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 341 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 342 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 343 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 344 /* 345 * for slave UCODE and ENV instored in master memory space, 346 * PHYS must be aligned based on the SIZE 347 */ 348 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 349 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 350 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 351 352 /* slave core release by master*/ 353 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 354 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 355 356 /* 357 * SRIO_PCIE_BOOT - SLAVE 358 */ 359 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 360 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 361 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 362 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 363 #endif 364 365 /* 366 * eSPI - Enhanced SPI 367 */ 368 #define CONFIG_SF_DEFAULT_SPEED 10000000 369 #define CONFIG_SF_DEFAULT_MODE 0 370 371 /* 372 * General PCI 373 * Memory space is mapped 1-1, but I/O space must start from 0. 374 */ 375 376 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 377 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 378 #ifdef CONFIG_PHYS_64BIT 379 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 380 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 381 #else 382 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 383 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 384 #endif 385 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 386 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 387 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 388 #ifdef CONFIG_PHYS_64BIT 389 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 390 #else 391 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 392 #endif 393 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 394 395 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 396 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 397 #ifdef CONFIG_PHYS_64BIT 398 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 399 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 400 #else 401 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 402 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 403 #endif 404 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 405 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 406 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 407 #ifdef CONFIG_PHYS_64BIT 408 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 409 #else 410 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 411 #endif 412 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 413 414 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 415 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 416 #ifdef CONFIG_PHYS_64BIT 417 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 418 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 419 #else 420 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 421 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 422 #endif 423 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 424 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 425 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 426 #ifdef CONFIG_PHYS_64BIT 427 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 428 #else 429 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 430 #endif 431 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 432 433 /* controller 4, Base address 203000 */ 434 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 435 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 436 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 437 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 438 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 439 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 440 441 /* Qman/Bman */ 442 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 443 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 444 #ifdef CONFIG_PHYS_64BIT 445 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 446 #else 447 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 448 #endif 449 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 450 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 451 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 452 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 453 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 454 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 455 CONFIG_SYS_BMAN_CENA_SIZE) 456 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 457 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 458 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 459 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 460 #ifdef CONFIG_PHYS_64BIT 461 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 462 #else 463 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 464 #endif 465 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 466 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 467 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 468 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 469 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 470 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 471 CONFIG_SYS_QMAN_CENA_SIZE) 472 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 473 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 474 475 #define CONFIG_SYS_DPAA_FMAN 476 #define CONFIG_SYS_DPAA_PME 477 /* Default address of microcode for the Linux Fman driver */ 478 #if defined(CONFIG_SPIFLASH) 479 /* 480 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 481 * env, so we got 0x110000. 482 */ 483 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 484 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 485 #elif defined(CONFIG_SDCARD) 486 /* 487 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 488 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 489 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 490 */ 491 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 492 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 493 #elif defined(CONFIG_NAND) 494 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 495 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 496 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 497 /* 498 * Slave has no ucode locally, it can fetch this from remote. When implementing 499 * in two corenet boards, slave's ucode could be stored in master's memory 500 * space, the address can be mapped from slave TLB->slave LAW-> 501 * slave SRIO or PCIE outbound window->master inbound window-> 502 * master LAW->the ucode address in master's memory space. 503 */ 504 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 505 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 506 #else 507 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 508 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 509 #endif 510 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 511 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 512 513 #ifdef CONFIG_SYS_DPAA_FMAN 514 #define CONFIG_FMAN_ENET 515 #define CONFIG_PHYLIB_10G 516 #define CONFIG_PHY_VITESSE 517 #define CONFIG_PHY_TERANETICS 518 #endif 519 520 #ifdef CONFIG_PCI 521 #define CONFIG_PCI_INDIRECT_BRIDGE 522 523 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 524 #endif /* CONFIG_PCI */ 525 526 /* SATA */ 527 #ifdef CONFIG_FSL_SATA_V2 528 #define CONFIG_SYS_SATA_MAX_DEVICE 2 529 #define CONFIG_SATA1 530 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 531 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 532 #define CONFIG_SATA2 533 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 534 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 535 536 #define CONFIG_LBA48 537 #endif 538 539 #ifdef CONFIG_FMAN_ENET 540 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c 541 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d 542 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e 543 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f 544 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 545 546 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c 547 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d 548 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e 549 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f 550 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0 551 552 #define CONFIG_SYS_TBIPA_VALUE 8 553 #define CONFIG_ETHPRIME "FM1@DTSEC1" 554 #endif 555 556 /* 557 * Environment 558 */ 559 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 560 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 561 562 /* 563 * USB 564 */ 565 #define CONFIG_HAS_FSL_DR_USB 566 #define CONFIG_HAS_FSL_MPH_USB 567 568 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 569 #define CONFIG_USB_EHCI_FSL 570 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 571 #endif 572 573 #ifdef CONFIG_MMC 574 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 575 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 576 #endif 577 578 /* 579 * Miscellaneous configurable options 580 */ 581 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 582 583 /* 584 * For booting Linux, the board info and command line data 585 * have to be in the first 64 MB of memory, since this is 586 * the maximum mapped by the Linux kernel during initialization. 587 */ 588 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 589 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 590 591 #ifdef CONFIG_CMD_KGDB 592 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 593 #endif 594 595 /* 596 * Environment Configuration 597 */ 598 #define CONFIG_ROOTPATH "/opt/nfsroot" 599 #define CONFIG_BOOTFILE "uImage" 600 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 601 602 /* default location for tftp and bootm */ 603 #define CONFIG_LOADADDR 1000000 604 605 #ifdef CONFIG_TARGET_P4080DS 606 #define __USB_PHY_TYPE ulpi 607 #else 608 #define __USB_PHY_TYPE utmi 609 #endif 610 611 #define CONFIG_EXTRA_ENV_SETTINGS \ 612 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 613 "bank_intlv=cs0_cs1;" \ 614 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 615 "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 616 "netdev=eth0\0" \ 617 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 618 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 619 "tftpflash=tftpboot $loadaddr $uboot && " \ 620 "protect off $ubootaddr +$filesize && " \ 621 "erase $ubootaddr +$filesize && " \ 622 "cp.b $loadaddr $ubootaddr $filesize && " \ 623 "protect on $ubootaddr +$filesize && " \ 624 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 625 "consoledev=ttyS0\0" \ 626 "ramdiskaddr=2000000\0" \ 627 "ramdiskfile=p4080ds/ramdisk.uboot\0" \ 628 "fdtaddr=1e00000\0" \ 629 "fdtfile=p4080ds/p4080ds.dtb\0" \ 630 "bdev=sda3\0" 631 632 #define CONFIG_HDBOOT \ 633 "setenv bootargs root=/dev/$bdev rw " \ 634 "console=$consoledev,$baudrate $othbootargs;" \ 635 "tftp $loadaddr $bootfile;" \ 636 "tftp $fdtaddr $fdtfile;" \ 637 "bootm $loadaddr - $fdtaddr" 638 639 #define CONFIG_NFSBOOTCOMMAND \ 640 "setenv bootargs root=/dev/nfs rw " \ 641 "nfsroot=$serverip:$rootpath " \ 642 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 643 "console=$consoledev,$baudrate $othbootargs;" \ 644 "tftp $loadaddr $bootfile;" \ 645 "tftp $fdtaddr $fdtfile;" \ 646 "bootm $loadaddr - $fdtaddr" 647 648 #define CONFIG_RAMBOOTCOMMAND \ 649 "setenv bootargs root=/dev/ram rw " \ 650 "console=$consoledev,$baudrate $othbootargs;" \ 651 "tftp $ramdiskaddr $ramdiskfile;" \ 652 "tftp $loadaddr $bootfile;" \ 653 "tftp $fdtaddr $fdtfile;" \ 654 "bootm $loadaddr $ramdiskaddr $fdtaddr" 655 656 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 657 658 #include <asm/fsl_secure_boot.h> 659 660 #endif /* __CONFIG_H */ 661