1 /* 2 * Copyright 2009-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * Corenet DS style board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #include "../board/freescale/common/ics307_clk.h" 14 15 #ifdef CONFIG_RAMBOOT_PBL 16 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 17 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 18 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg 19 #if defined(CONFIG_P3041DS) 20 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg 21 #elif defined(CONFIG_P4080DS) 22 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg 23 #elif defined(CONFIG_P5020DS) 24 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg 25 #elif defined(CONFIG_P5040DS) 26 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg 27 #endif 28 #endif 29 30 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 31 /* Set 1M boot space */ 32 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 33 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 34 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 35 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 36 #define CONFIG_SYS_NO_FLASH 37 #endif 38 39 /* High Level Configuration Options */ 40 #define CONFIG_BOOKE 41 #define CONFIG_E500 /* BOOKE e500 family */ 42 #define CONFIG_E500MC /* BOOKE e500mc family */ 43 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 44 #define CONFIG_MP /* support multiple processors */ 45 46 #ifndef CONFIG_SYS_TEXT_BASE 47 #define CONFIG_SYS_TEXT_BASE 0xeff40000 48 #endif 49 50 #ifndef CONFIG_RESET_VECTOR_ADDRESS 51 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 52 #endif 53 54 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 55 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 56 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 57 #define CONFIG_PCI /* Enable PCI/PCIE */ 58 #define CONFIG_PCIE1 /* PCIE controler 1 */ 59 #define CONFIG_PCIE2 /* PCIE controler 2 */ 60 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 61 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 62 63 #define CONFIG_FSL_LAW /* Use common FSL init code */ 64 65 #define CONFIG_ENV_OVERWRITE 66 67 #ifdef CONFIG_SYS_NO_FLASH 68 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) 69 #define CONFIG_ENV_IS_NOWHERE 70 #endif 71 #else 72 #define CONFIG_FLASH_CFI_DRIVER 73 #define CONFIG_SYS_FLASH_CFI 74 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 75 #endif 76 77 #if defined(CONFIG_SPIFLASH) 78 #define CONFIG_SYS_EXTRA_ENV_RELOC 79 #define CONFIG_ENV_IS_IN_SPI_FLASH 80 #define CONFIG_ENV_SPI_BUS 0 81 #define CONFIG_ENV_SPI_CS 0 82 #define CONFIG_ENV_SPI_MAX_HZ 10000000 83 #define CONFIG_ENV_SPI_MODE 0 84 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 85 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 86 #define CONFIG_ENV_SECT_SIZE 0x10000 87 #elif defined(CONFIG_SDCARD) 88 #define CONFIG_SYS_EXTRA_ENV_RELOC 89 #define CONFIG_ENV_IS_IN_MMC 90 #define CONFIG_FSL_FIXED_MMC_LOCATION 91 #define CONFIG_SYS_MMC_ENV_DEV 0 92 #define CONFIG_ENV_SIZE 0x2000 93 #define CONFIG_ENV_OFFSET (512 * 1658) 94 #elif defined(CONFIG_NAND) 95 #define CONFIG_SYS_EXTRA_ENV_RELOC 96 #define CONFIG_ENV_IS_IN_NAND 97 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 98 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 99 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 100 #define CONFIG_ENV_IS_IN_REMOTE 101 #define CONFIG_ENV_ADDR 0xffe20000 102 #define CONFIG_ENV_SIZE 0x2000 103 #elif defined(CONFIG_ENV_IS_NOWHERE) 104 #define CONFIG_ENV_SIZE 0x2000 105 #else 106 #define CONFIG_ENV_IS_IN_FLASH 107 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 108 #define CONFIG_ENV_SIZE 0x2000 109 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 110 #endif 111 112 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 113 114 /* 115 * These can be toggled for performance analysis, otherwise use default. 116 */ 117 #define CONFIG_SYS_CACHE_STASHING 118 #define CONFIG_BACKSIDE_L2_CACHE 119 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 120 #define CONFIG_BTB /* toggle branch predition */ 121 #define CONFIG_DDR_ECC 122 #ifdef CONFIG_DDR_ECC 123 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 124 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 125 #endif 126 127 #define CONFIG_ENABLE_36BIT_PHYS 128 129 #ifdef CONFIG_PHYS_64BIT 130 #define CONFIG_ADDR_MAP 131 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 132 #endif 133 134 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 135 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 136 #define CONFIG_SYS_MEMTEST_END 0x00400000 137 #define CONFIG_SYS_ALT_MEMTEST 138 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 139 140 /* 141 * Config the L3 Cache as L3 SRAM 142 */ 143 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 144 #ifdef CONFIG_PHYS_64BIT 145 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) 146 #else 147 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 148 #endif 149 #define CONFIG_SYS_L3_SIZE (1024 << 10) 150 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 151 152 #ifdef CONFIG_PHYS_64BIT 153 #define CONFIG_SYS_DCSRBAR 0xf0000000 154 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 155 #endif 156 157 /* EEPROM */ 158 #define CONFIG_ID_EEPROM 159 #define CONFIG_SYS_I2C_EEPROM_NXID 160 #define CONFIG_SYS_EEPROM_BUS_NUM 0 161 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 162 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 163 164 /* 165 * DDR Setup 166 */ 167 #define CONFIG_VERY_BIG_RAM 168 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 169 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 170 171 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 172 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 173 174 #define CONFIG_DDR_SPD 175 #define CONFIG_SYS_FSL_DDR3 176 177 #define CONFIG_SYS_SPD_BUS_NUM 1 178 #define SPD_EEPROM_ADDRESS1 0x51 179 #define SPD_EEPROM_ADDRESS2 0x52 180 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 181 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 182 183 /* 184 * Local Bus Definitions 185 */ 186 187 /* Set the local bus clock 1/8 of platform clock */ 188 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 189 190 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */ 191 #ifdef CONFIG_PHYS_64BIT 192 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 193 #else 194 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 195 #endif 196 197 #define CONFIG_SYS_FLASH_BR_PRELIM \ 198 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \ 199 | BR_PS_16 | BR_V) 200 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 201 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 202 203 #define CONFIG_SYS_BR1_PRELIM \ 204 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 205 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 206 207 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 208 #ifdef CONFIG_PHYS_64BIT 209 #define PIXIS_BASE_PHYS 0xfffdf0000ull 210 #else 211 #define PIXIS_BASE_PHYS PIXIS_BASE 212 #endif 213 214 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 215 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 216 217 #define PIXIS_LBMAP_SWITCH 7 218 #define PIXIS_LBMAP_MASK 0xf0 219 #define PIXIS_LBMAP_SHIFT 4 220 #define PIXIS_LBMAP_ALTBANK 0x40 221 222 #define CONFIG_SYS_FLASH_QUIET_TEST 223 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 224 225 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 226 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 227 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 228 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 229 230 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 231 232 #if defined(CONFIG_RAMBOOT_PBL) 233 #define CONFIG_SYS_RAMBOOT 234 #endif 235 236 /* Nand Flash */ 237 #ifdef CONFIG_NAND_FSL_ELBC 238 #define CONFIG_SYS_NAND_BASE 0xffa00000 239 #ifdef CONFIG_PHYS_64BIT 240 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 241 #else 242 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 243 #endif 244 245 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 246 #define CONFIG_SYS_MAX_NAND_DEVICE 1 247 #define CONFIG_MTD_NAND_VERIFY_WRITE 248 #define CONFIG_CMD_NAND 249 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 250 251 /* NAND flash config */ 252 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 253 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 254 | BR_PS_8 /* Port Size = 8 bit */ \ 255 | BR_MS_FCM /* MSEL = FCM */ \ 256 | BR_V) /* valid */ 257 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 258 | OR_FCM_PGS /* Large Page*/ \ 259 | OR_FCM_CSCT \ 260 | OR_FCM_CST \ 261 | OR_FCM_CHT \ 262 | OR_FCM_SCY_1 \ 263 | OR_FCM_TRLX \ 264 | OR_FCM_EHTR) 265 266 #ifdef CONFIG_NAND 267 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 268 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 269 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 270 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 271 #else 272 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 273 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 274 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 275 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 276 #endif 277 #else 278 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 279 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 280 #endif /* CONFIG_NAND_FSL_ELBC */ 281 282 #define CONFIG_SYS_FLASH_EMPTY_INFO 283 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 284 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 285 286 #define CONFIG_BOARD_EARLY_INIT_F 287 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 288 #define CONFIG_MISC_INIT_R 289 290 #define CONFIG_HWCONFIG 291 292 /* define to use L1 as initial stack */ 293 #define CONFIG_L1_INIT_RAM 294 #define CONFIG_SYS_INIT_RAM_LOCK 295 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 296 #ifdef CONFIG_PHYS_64BIT 297 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 298 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 299 /* The assembler doesn't like typecast */ 300 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 301 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 302 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 303 #else 304 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ 305 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 306 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 307 #endif 308 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 309 310 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 311 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 312 313 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 314 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 315 316 /* Serial Port - controlled on board with jumper J8 317 * open - index 2 318 * shorted - index 1 319 */ 320 #define CONFIG_CONS_INDEX 1 321 #define CONFIG_SYS_NS16550 322 #define CONFIG_SYS_NS16550_SERIAL 323 #define CONFIG_SYS_NS16550_REG_SIZE 1 324 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 325 326 #define CONFIG_SYS_BAUDRATE_TABLE \ 327 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 328 329 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 330 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 331 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 332 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 333 334 /* Use the HUSH parser */ 335 #define CONFIG_SYS_HUSH_PARSER 336 337 /* pass open firmware flat tree */ 338 #define CONFIG_OF_LIBFDT 339 #define CONFIG_OF_BOARD_SETUP 340 #define CONFIG_OF_STDOUT_VIA_ALIAS 341 342 /* new uImage format support */ 343 #define CONFIG_FIT 344 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 345 346 /* I2C */ 347 #define CONFIG_SYS_I2C 348 #define CONFIG_SYS_I2C_FSL 349 #define CONFIG_SYS_FSL_I2C_SPEED 400000 350 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 351 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 352 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 353 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 354 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 355 356 /* 357 * RapidIO 358 */ 359 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 360 #ifdef CONFIG_PHYS_64BIT 361 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 362 #else 363 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 364 #endif 365 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 366 367 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 368 #ifdef CONFIG_PHYS_64BIT 369 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 370 #else 371 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 372 #endif 373 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 374 375 /* 376 * for slave u-boot IMAGE instored in master memory space, 377 * PHYS must be aligned based on the SIZE 378 */ 379 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull 380 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull 381 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */ 382 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull 383 /* 384 * for slave UCODE and ENV instored in master memory space, 385 * PHYS must be aligned based on the SIZE 386 */ 387 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull 388 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 389 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 390 391 /* slave core release by master*/ 392 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 393 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 394 395 /* 396 * SRIO_PCIE_BOOT - SLAVE 397 */ 398 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 399 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 400 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 401 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 402 #endif 403 404 /* 405 * eSPI - Enhanced SPI 406 */ 407 #define CONFIG_FSL_ESPI 408 #define CONFIG_SPI_FLASH 409 #define CONFIG_SPI_FLASH_SPANSION 410 #define CONFIG_CMD_SF 411 #define CONFIG_SF_DEFAULT_SPEED 10000000 412 #define CONFIG_SF_DEFAULT_MODE 0 413 414 /* 415 * General PCI 416 * Memory space is mapped 1-1, but I/O space must start from 0. 417 */ 418 419 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 420 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 421 #ifdef CONFIG_PHYS_64BIT 422 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 423 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 424 #else 425 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 426 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 427 #endif 428 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 429 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 430 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 431 #ifdef CONFIG_PHYS_64BIT 432 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 433 #else 434 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 435 #endif 436 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 437 438 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 439 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 440 #ifdef CONFIG_PHYS_64BIT 441 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 442 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 443 #else 444 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 445 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 446 #endif 447 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 448 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 449 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 450 #ifdef CONFIG_PHYS_64BIT 451 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 452 #else 453 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 454 #endif 455 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 456 457 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 458 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 459 #ifdef CONFIG_PHYS_64BIT 460 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 461 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 462 #else 463 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 464 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 465 #endif 466 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 467 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 468 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 469 #ifdef CONFIG_PHYS_64BIT 470 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 471 #else 472 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 473 #endif 474 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 475 476 /* controller 4, Base address 203000 */ 477 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 478 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 479 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 480 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 481 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 482 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 483 484 /* Qman/Bman */ 485 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 486 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 487 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 488 #ifdef CONFIG_PHYS_64BIT 489 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 490 #else 491 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 492 #endif 493 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 494 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 495 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 496 #ifdef CONFIG_PHYS_64BIT 497 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 498 #else 499 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 500 #endif 501 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 502 503 #define CONFIG_SYS_DPAA_FMAN 504 #define CONFIG_SYS_DPAA_PME 505 /* Default address of microcode for the Linux Fman driver */ 506 #if defined(CONFIG_SPIFLASH) 507 /* 508 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 509 * env, so we got 0x110000. 510 */ 511 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 512 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 513 #elif defined(CONFIG_SDCARD) 514 /* 515 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 516 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 517 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 518 */ 519 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 520 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) 521 #elif defined(CONFIG_NAND) 522 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 523 #define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 524 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 525 /* 526 * Slave has no ucode locally, it can fetch this from remote. When implementing 527 * in two corenet boards, slave's ucode could be stored in master's memory 528 * space, the address can be mapped from slave TLB->slave LAW-> 529 * slave SRIO or PCIE outbound window->master inbound window-> 530 * master LAW->the ucode address in master's memory space. 531 */ 532 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 533 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 534 #else 535 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 536 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 537 #endif 538 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 539 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 540 541 #ifdef CONFIG_SYS_DPAA_FMAN 542 #define CONFIG_FMAN_ENET 543 #define CONFIG_PHYLIB_10G 544 #define CONFIG_PHY_VITESSE 545 #define CONFIG_PHY_TERANETICS 546 #endif 547 548 #ifdef CONFIG_PCI 549 #define CONFIG_PCI_INDIRECT_BRIDGE 550 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 551 #define CONFIG_E1000 552 553 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 554 #define CONFIG_DOS_PARTITION 555 #endif /* CONFIG_PCI */ 556 557 /* SATA */ 558 #ifdef CONFIG_FSL_SATA_V2 559 #define CONFIG_LIBATA 560 #define CONFIG_FSL_SATA 561 562 #define CONFIG_SYS_SATA_MAX_DEVICE 2 563 #define CONFIG_SATA1 564 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 565 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 566 #define CONFIG_SATA2 567 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 568 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 569 570 #define CONFIG_LBA48 571 #define CONFIG_CMD_SATA 572 #define CONFIG_DOS_PARTITION 573 #define CONFIG_CMD_EXT2 574 #endif 575 576 #ifdef CONFIG_FMAN_ENET 577 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c 578 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d 579 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e 580 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f 581 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 582 583 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c 584 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d 585 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e 586 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f 587 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0 588 589 #define CONFIG_SYS_TBIPA_VALUE 8 590 #define CONFIG_MII /* MII PHY management */ 591 #define CONFIG_ETHPRIME "FM1@DTSEC1" 592 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 593 #endif 594 595 /* 596 * Environment 597 */ 598 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 599 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 600 601 /* 602 * Command line configuration. 603 */ 604 #include <config_cmd_default.h> 605 606 #define CONFIG_CMD_DHCP 607 #define CONFIG_CMD_ELF 608 #define CONFIG_CMD_ERRATA 609 #define CONFIG_CMD_GREPENV 610 #define CONFIG_CMD_IRQ 611 #define CONFIG_CMD_I2C 612 #define CONFIG_CMD_MII 613 #define CONFIG_CMD_PING 614 #define CONFIG_CMD_SETEXPR 615 #define CONFIG_CMD_REGINFO 616 617 #ifdef CONFIG_PCI 618 #define CONFIG_CMD_PCI 619 #define CONFIG_CMD_NET 620 #endif 621 622 /* 623 * USB 624 */ 625 #define CONFIG_HAS_FSL_DR_USB 626 #define CONFIG_HAS_FSL_MPH_USB 627 628 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 629 #define CONFIG_CMD_USB 630 #define CONFIG_USB_STORAGE 631 #define CONFIG_USB_EHCI 632 #define CONFIG_USB_EHCI_FSL 633 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 634 #define CONFIG_CMD_EXT2 635 #endif 636 637 #ifdef CONFIG_MMC 638 #define CONFIG_FSL_ESDHC 639 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 640 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 641 #define CONFIG_CMD_MMC 642 #define CONFIG_GENERIC_MMC 643 #define CONFIG_CMD_EXT2 644 #define CONFIG_CMD_FAT 645 #define CONFIG_DOS_PARTITION 646 #endif 647 648 /* 649 * Miscellaneous configurable options 650 */ 651 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 652 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 653 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 654 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 655 #ifdef CONFIG_CMD_KGDB 656 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 657 #else 658 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 659 #endif 660 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 661 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 662 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 663 664 /* 665 * For booting Linux, the board info and command line data 666 * have to be in the first 64 MB of memory, since this is 667 * the maximum mapped by the Linux kernel during initialization. 668 */ 669 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 670 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 671 672 #ifdef CONFIG_CMD_KGDB 673 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 674 #endif 675 676 /* 677 * Environment Configuration 678 */ 679 #define CONFIG_ROOTPATH "/opt/nfsroot" 680 #define CONFIG_BOOTFILE "uImage" 681 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 682 683 /* default location for tftp and bootm */ 684 #define CONFIG_LOADADDR 1000000 685 686 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 687 688 #define CONFIG_BAUDRATE 115200 689 690 #ifdef CONFIG_P4080DS 691 #define __USB_PHY_TYPE ulpi 692 #else 693 #define __USB_PHY_TYPE utmi 694 #endif 695 696 #define CONFIG_EXTRA_ENV_SETTINGS \ 697 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 698 "bank_intlv=cs0_cs1;" \ 699 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 700 "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 701 "netdev=eth0\0" \ 702 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 703 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 704 "tftpflash=tftpboot $loadaddr $uboot && " \ 705 "protect off $ubootaddr +$filesize && " \ 706 "erase $ubootaddr +$filesize && " \ 707 "cp.b $loadaddr $ubootaddr $filesize && " \ 708 "protect on $ubootaddr +$filesize && " \ 709 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 710 "consoledev=ttyS0\0" \ 711 "ramdiskaddr=2000000\0" \ 712 "ramdiskfile=p4080ds/ramdisk.uboot\0" \ 713 "fdtaddr=c00000\0" \ 714 "fdtfile=p4080ds/p4080ds.dtb\0" \ 715 "bdev=sda3\0" \ 716 "c=ffe\0" 717 718 #define CONFIG_HDBOOT \ 719 "setenv bootargs root=/dev/$bdev rw " \ 720 "console=$consoledev,$baudrate $othbootargs;" \ 721 "tftp $loadaddr $bootfile;" \ 722 "tftp $fdtaddr $fdtfile;" \ 723 "bootm $loadaddr - $fdtaddr" 724 725 #define CONFIG_NFSBOOTCOMMAND \ 726 "setenv bootargs root=/dev/nfs rw " \ 727 "nfsroot=$serverip:$rootpath " \ 728 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 729 "console=$consoledev,$baudrate $othbootargs;" \ 730 "tftp $loadaddr $bootfile;" \ 731 "tftp $fdtaddr $fdtfile;" \ 732 "bootm $loadaddr - $fdtaddr" 733 734 #define CONFIG_RAMBOOTCOMMAND \ 735 "setenv bootargs root=/dev/ram rw " \ 736 "console=$consoledev,$baudrate $othbootargs;" \ 737 "tftp $ramdiskaddr $ramdiskfile;" \ 738 "tftp $loadaddr $bootfile;" \ 739 "tftp $fdtaddr $fdtfile;" \ 740 "bootm $loadaddr $ramdiskaddr $fdtaddr" 741 742 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 743 744 #include <asm/fsl_secure_boot.h> 745 746 #endif /* __CONFIG_H */ 747