1 /* 2 * Copyright 2009-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * Corenet DS style board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #include "../board/freescale/common/ics307_clk.h" 14 15 #ifdef CONFIG_RAMBOOT_PBL 16 #ifdef CONFIG_SECURE_BOOT 17 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 18 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 19 #ifdef CONFIG_NAND 20 #define CONFIG_RAMBOOT_NAND 21 #endif 22 #define CONFIG_BOOTSCRIPT_COPY_RAM 23 #else 24 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 25 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 26 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg 27 #if defined(CONFIG_TARGET_P3041DS) 28 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg 29 #elif defined(CONFIG_TARGET_P4080DS) 30 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg 31 #elif defined(CONFIG_TARGET_P5020DS) 32 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg 33 #elif defined(CONFIG_TARGET_P5040DS) 34 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg 35 #endif 36 #endif 37 #endif 38 39 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 40 /* Set 1M boot space */ 41 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 42 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 43 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 44 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 45 #define CONFIG_SYS_NO_FLASH 46 #endif 47 48 /* High Level Configuration Options */ 49 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 50 #define CONFIG_MP /* support multiple processors */ 51 52 #ifndef CONFIG_SYS_TEXT_BASE 53 #define CONFIG_SYS_TEXT_BASE 0xeff40000 54 #endif 55 56 #ifndef CONFIG_RESET_VECTOR_ADDRESS 57 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 58 #endif 59 60 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 61 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 62 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 63 #define CONFIG_PCIE1 /* PCIE controller 1 */ 64 #define CONFIG_PCIE2 /* PCIE controller 2 */ 65 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 66 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 67 68 #define CONFIG_ENV_OVERWRITE 69 70 #ifdef CONFIG_SYS_NO_FLASH 71 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) 72 #define CONFIG_ENV_IS_NOWHERE 73 #endif 74 #else 75 #define CONFIG_FLASH_CFI_DRIVER 76 #define CONFIG_SYS_FLASH_CFI 77 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 78 #endif 79 80 #if defined(CONFIG_SPIFLASH) 81 #define CONFIG_SYS_EXTRA_ENV_RELOC 82 #define CONFIG_ENV_IS_IN_SPI_FLASH 83 #define CONFIG_ENV_SPI_BUS 0 84 #define CONFIG_ENV_SPI_CS 0 85 #define CONFIG_ENV_SPI_MAX_HZ 10000000 86 #define CONFIG_ENV_SPI_MODE 0 87 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 88 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 89 #define CONFIG_ENV_SECT_SIZE 0x10000 90 #elif defined(CONFIG_SDCARD) 91 #define CONFIG_SYS_EXTRA_ENV_RELOC 92 #define CONFIG_ENV_IS_IN_MMC 93 #define CONFIG_FSL_FIXED_MMC_LOCATION 94 #define CONFIG_SYS_MMC_ENV_DEV 0 95 #define CONFIG_ENV_SIZE 0x2000 96 #define CONFIG_ENV_OFFSET (512 * 1658) 97 #elif defined(CONFIG_NAND) 98 #define CONFIG_SYS_EXTRA_ENV_RELOC 99 #define CONFIG_ENV_IS_IN_NAND 100 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 101 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 102 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 103 #define CONFIG_ENV_IS_IN_REMOTE 104 #define CONFIG_ENV_ADDR 0xffe20000 105 #define CONFIG_ENV_SIZE 0x2000 106 #elif defined(CONFIG_ENV_IS_NOWHERE) 107 #define CONFIG_ENV_SIZE 0x2000 108 #else 109 #define CONFIG_ENV_IS_IN_FLASH 110 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 111 #define CONFIG_ENV_SIZE 0x2000 112 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 113 #endif 114 115 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 116 117 /* 118 * These can be toggled for performance analysis, otherwise use default. 119 */ 120 #define CONFIG_SYS_CACHE_STASHING 121 #define CONFIG_BACKSIDE_L2_CACHE 122 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 123 #define CONFIG_BTB /* toggle branch predition */ 124 #define CONFIG_DDR_ECC 125 #ifdef CONFIG_DDR_ECC 126 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 127 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 128 #endif 129 130 #define CONFIG_ENABLE_36BIT_PHYS 131 132 #ifdef CONFIG_PHYS_64BIT 133 #define CONFIG_ADDR_MAP 134 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 135 #endif 136 137 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 138 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 139 #define CONFIG_SYS_MEMTEST_END 0x00400000 140 #define CONFIG_SYS_ALT_MEMTEST 141 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 142 143 /* 144 * Config the L3 Cache as L3 SRAM 145 */ 146 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 147 #ifdef CONFIG_PHYS_64BIT 148 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) 149 #else 150 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 151 #endif 152 #define CONFIG_SYS_L3_SIZE (1024 << 10) 153 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 154 155 #ifdef CONFIG_PHYS_64BIT 156 #define CONFIG_SYS_DCSRBAR 0xf0000000 157 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 158 #endif 159 160 /* EEPROM */ 161 #define CONFIG_ID_EEPROM 162 #define CONFIG_SYS_I2C_EEPROM_NXID 163 #define CONFIG_SYS_EEPROM_BUS_NUM 0 164 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 165 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 166 167 /* 168 * DDR Setup 169 */ 170 #define CONFIG_VERY_BIG_RAM 171 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 172 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 173 174 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 175 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 176 177 #define CONFIG_DDR_SPD 178 179 #define CONFIG_SYS_SPD_BUS_NUM 1 180 #define SPD_EEPROM_ADDRESS1 0x51 181 #define SPD_EEPROM_ADDRESS2 0x52 182 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 183 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 184 185 /* 186 * Local Bus Definitions 187 */ 188 189 /* Set the local bus clock 1/8 of platform clock */ 190 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 191 192 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */ 193 #ifdef CONFIG_PHYS_64BIT 194 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 195 #else 196 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 197 #endif 198 199 #define CONFIG_SYS_FLASH_BR_PRELIM \ 200 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \ 201 | BR_PS_16 | BR_V) 202 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 203 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 204 205 #define CONFIG_SYS_BR1_PRELIM \ 206 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 207 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 208 209 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 210 #ifdef CONFIG_PHYS_64BIT 211 #define PIXIS_BASE_PHYS 0xfffdf0000ull 212 #else 213 #define PIXIS_BASE_PHYS PIXIS_BASE 214 #endif 215 216 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 217 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 218 219 #define PIXIS_LBMAP_SWITCH 7 220 #define PIXIS_LBMAP_MASK 0xf0 221 #define PIXIS_LBMAP_SHIFT 4 222 #define PIXIS_LBMAP_ALTBANK 0x40 223 224 #define CONFIG_SYS_FLASH_QUIET_TEST 225 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 226 227 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 228 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 229 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 230 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 231 232 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 233 234 #if defined(CONFIG_RAMBOOT_PBL) 235 #define CONFIG_SYS_RAMBOOT 236 #endif 237 238 /* Nand Flash */ 239 #ifdef CONFIG_NAND_FSL_ELBC 240 #define CONFIG_SYS_NAND_BASE 0xffa00000 241 #ifdef CONFIG_PHYS_64BIT 242 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 243 #else 244 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 245 #endif 246 247 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 248 #define CONFIG_SYS_MAX_NAND_DEVICE 1 249 #define CONFIG_CMD_NAND 250 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 251 252 /* NAND flash config */ 253 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 254 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 255 | BR_PS_8 /* Port Size = 8 bit */ \ 256 | BR_MS_FCM /* MSEL = FCM */ \ 257 | BR_V) /* valid */ 258 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 259 | OR_FCM_PGS /* Large Page*/ \ 260 | OR_FCM_CSCT \ 261 | OR_FCM_CST \ 262 | OR_FCM_CHT \ 263 | OR_FCM_SCY_1 \ 264 | OR_FCM_TRLX \ 265 | OR_FCM_EHTR) 266 267 #ifdef CONFIG_NAND 268 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 269 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 270 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 271 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 272 #else 273 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 274 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 275 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 276 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 277 #endif 278 #else 279 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 280 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 281 #endif /* CONFIG_NAND_FSL_ELBC */ 282 283 #define CONFIG_SYS_FLASH_EMPTY_INFO 284 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 285 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 286 287 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 288 #define CONFIG_MISC_INIT_R 289 290 #define CONFIG_HWCONFIG 291 292 /* define to use L1 as initial stack */ 293 #define CONFIG_L1_INIT_RAM 294 #define CONFIG_SYS_INIT_RAM_LOCK 295 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 296 #ifdef CONFIG_PHYS_64BIT 297 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 298 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 299 /* The assembler doesn't like typecast */ 300 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 301 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 302 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 303 #else 304 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ 305 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 306 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 307 #endif 308 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 309 310 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 311 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 312 313 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 314 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 315 316 /* Serial Port - controlled on board with jumper J8 317 * open - index 2 318 * shorted - index 1 319 */ 320 #define CONFIG_CONS_INDEX 1 321 #define CONFIG_SYS_NS16550_SERIAL 322 #define CONFIG_SYS_NS16550_REG_SIZE 1 323 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 324 325 #define CONFIG_SYS_BAUDRATE_TABLE \ 326 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 327 328 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 329 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 330 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 331 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 332 333 /* I2C */ 334 #define CONFIG_SYS_I2C 335 #define CONFIG_SYS_I2C_FSL 336 #define CONFIG_SYS_FSL_I2C_SPEED 400000 337 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 338 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 339 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 340 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 341 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 342 343 /* 344 * RapidIO 345 */ 346 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 347 #ifdef CONFIG_PHYS_64BIT 348 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 349 #else 350 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 351 #endif 352 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 353 354 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 355 #ifdef CONFIG_PHYS_64BIT 356 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 357 #else 358 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 359 #endif 360 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 361 362 /* 363 * for slave u-boot IMAGE instored in master memory space, 364 * PHYS must be aligned based on the SIZE 365 */ 366 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 367 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 368 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 369 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 370 /* 371 * for slave UCODE and ENV instored in master memory space, 372 * PHYS must be aligned based on the SIZE 373 */ 374 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 375 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 376 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 377 378 /* slave core release by master*/ 379 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 380 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 381 382 /* 383 * SRIO_PCIE_BOOT - SLAVE 384 */ 385 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 386 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 387 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 388 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 389 #endif 390 391 /* 392 * eSPI - Enhanced SPI 393 */ 394 #define CONFIG_SF_DEFAULT_SPEED 10000000 395 #define CONFIG_SF_DEFAULT_MODE 0 396 397 /* 398 * General PCI 399 * Memory space is mapped 1-1, but I/O space must start from 0. 400 */ 401 402 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 403 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 404 #ifdef CONFIG_PHYS_64BIT 405 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 406 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 407 #else 408 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 409 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 410 #endif 411 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 412 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 413 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 414 #ifdef CONFIG_PHYS_64BIT 415 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 416 #else 417 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 418 #endif 419 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 420 421 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 422 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 423 #ifdef CONFIG_PHYS_64BIT 424 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 425 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 426 #else 427 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 428 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 429 #endif 430 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 431 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 432 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 433 #ifdef CONFIG_PHYS_64BIT 434 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 435 #else 436 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 437 #endif 438 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 439 440 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 441 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 442 #ifdef CONFIG_PHYS_64BIT 443 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 444 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 445 #else 446 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 447 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 448 #endif 449 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 450 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 451 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 452 #ifdef CONFIG_PHYS_64BIT 453 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 454 #else 455 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 456 #endif 457 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 458 459 /* controller 4, Base address 203000 */ 460 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 461 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 462 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 463 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 464 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 465 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 466 467 /* Qman/Bman */ 468 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 469 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 470 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 471 #ifdef CONFIG_PHYS_64BIT 472 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 473 #else 474 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 475 #endif 476 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 477 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 478 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 479 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 480 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 481 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 482 CONFIG_SYS_BMAN_CENA_SIZE) 483 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 484 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 485 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 486 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 487 #ifdef CONFIG_PHYS_64BIT 488 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 489 #else 490 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 491 #endif 492 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 493 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 494 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 495 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 496 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 497 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 498 CONFIG_SYS_QMAN_CENA_SIZE) 499 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 500 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 501 502 #define CONFIG_SYS_DPAA_FMAN 503 #define CONFIG_SYS_DPAA_PME 504 /* Default address of microcode for the Linux Fman driver */ 505 #if defined(CONFIG_SPIFLASH) 506 /* 507 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 508 * env, so we got 0x110000. 509 */ 510 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 511 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 512 #elif defined(CONFIG_SDCARD) 513 /* 514 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 515 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 516 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 517 */ 518 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 519 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 520 #elif defined(CONFIG_NAND) 521 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 522 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 523 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 524 /* 525 * Slave has no ucode locally, it can fetch this from remote. When implementing 526 * in two corenet boards, slave's ucode could be stored in master's memory 527 * space, the address can be mapped from slave TLB->slave LAW-> 528 * slave SRIO or PCIE outbound window->master inbound window-> 529 * master LAW->the ucode address in master's memory space. 530 */ 531 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 532 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 533 #else 534 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 535 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 536 #endif 537 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 538 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 539 540 #ifdef CONFIG_SYS_DPAA_FMAN 541 #define CONFIG_FMAN_ENET 542 #define CONFIG_PHYLIB_10G 543 #define CONFIG_PHY_VITESSE 544 #define CONFIG_PHY_TERANETICS 545 #endif 546 547 #ifdef CONFIG_PCI 548 #define CONFIG_PCI_INDIRECT_BRIDGE 549 550 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 551 #endif /* CONFIG_PCI */ 552 553 /* SATA */ 554 #ifdef CONFIG_FSL_SATA_V2 555 #define CONFIG_LIBATA 556 #define CONFIG_FSL_SATA 557 558 #define CONFIG_SYS_SATA_MAX_DEVICE 2 559 #define CONFIG_SATA1 560 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 561 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 562 #define CONFIG_SATA2 563 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 564 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 565 566 #define CONFIG_LBA48 567 #define CONFIG_CMD_SATA 568 #endif 569 570 #ifdef CONFIG_FMAN_ENET 571 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c 572 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d 573 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e 574 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f 575 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 576 577 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c 578 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d 579 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e 580 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f 581 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0 582 583 #define CONFIG_SYS_TBIPA_VALUE 8 584 #define CONFIG_MII /* MII PHY management */ 585 #define CONFIG_ETHPRIME "FM1@DTSEC1" 586 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 587 #endif 588 589 /* 590 * Environment 591 */ 592 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 593 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 594 595 /* 596 * Command line configuration. 597 */ 598 #define CONFIG_CMD_ERRATA 599 #define CONFIG_CMD_IRQ 600 #define CONFIG_CMD_REGINFO 601 602 #ifdef CONFIG_PCI 603 #define CONFIG_CMD_PCI 604 #endif 605 606 /* 607 * USB 608 */ 609 #define CONFIG_HAS_FSL_DR_USB 610 #define CONFIG_HAS_FSL_MPH_USB 611 612 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 613 #define CONFIG_USB_EHCI 614 #define CONFIG_USB_EHCI_FSL 615 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 616 #endif 617 618 #ifdef CONFIG_MMC 619 #define CONFIG_FSL_ESDHC 620 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 621 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 622 #endif 623 624 /* Hash command with SHA acceleration supported in hardware */ 625 #ifdef CONFIG_FSL_CAAM 626 #define CONFIG_CMD_HASH 627 #define CONFIG_SHA_HW_ACCEL 628 #endif 629 630 /* 631 * Miscellaneous configurable options 632 */ 633 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 634 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 635 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 636 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 637 #ifdef CONFIG_CMD_KGDB 638 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 639 #else 640 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 641 #endif 642 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 643 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 644 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 645 646 /* 647 * For booting Linux, the board info and command line data 648 * have to be in the first 64 MB of memory, since this is 649 * the maximum mapped by the Linux kernel during initialization. 650 */ 651 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 652 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 653 654 #ifdef CONFIG_CMD_KGDB 655 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 656 #endif 657 658 /* 659 * Environment Configuration 660 */ 661 #define CONFIG_ROOTPATH "/opt/nfsroot" 662 #define CONFIG_BOOTFILE "uImage" 663 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 664 665 /* default location for tftp and bootm */ 666 #define CONFIG_LOADADDR 1000000 667 668 669 #define CONFIG_BAUDRATE 115200 670 671 #ifdef CONFIG_TARGET_P4080DS 672 #define __USB_PHY_TYPE ulpi 673 #else 674 #define __USB_PHY_TYPE utmi 675 #endif 676 677 #define CONFIG_EXTRA_ENV_SETTINGS \ 678 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 679 "bank_intlv=cs0_cs1;" \ 680 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 681 "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 682 "netdev=eth0\0" \ 683 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 684 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 685 "tftpflash=tftpboot $loadaddr $uboot && " \ 686 "protect off $ubootaddr +$filesize && " \ 687 "erase $ubootaddr +$filesize && " \ 688 "cp.b $loadaddr $ubootaddr $filesize && " \ 689 "protect on $ubootaddr +$filesize && " \ 690 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 691 "consoledev=ttyS0\0" \ 692 "ramdiskaddr=2000000\0" \ 693 "ramdiskfile=p4080ds/ramdisk.uboot\0" \ 694 "fdtaddr=1e00000\0" \ 695 "fdtfile=p4080ds/p4080ds.dtb\0" \ 696 "bdev=sda3\0" 697 698 #define CONFIG_HDBOOT \ 699 "setenv bootargs root=/dev/$bdev rw " \ 700 "console=$consoledev,$baudrate $othbootargs;" \ 701 "tftp $loadaddr $bootfile;" \ 702 "tftp $fdtaddr $fdtfile;" \ 703 "bootm $loadaddr - $fdtaddr" 704 705 #define CONFIG_NFSBOOTCOMMAND \ 706 "setenv bootargs root=/dev/nfs rw " \ 707 "nfsroot=$serverip:$rootpath " \ 708 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 709 "console=$consoledev,$baudrate $othbootargs;" \ 710 "tftp $loadaddr $bootfile;" \ 711 "tftp $fdtaddr $fdtfile;" \ 712 "bootm $loadaddr - $fdtaddr" 713 714 #define CONFIG_RAMBOOTCOMMAND \ 715 "setenv bootargs root=/dev/ram rw " \ 716 "console=$consoledev,$baudrate $othbootargs;" \ 717 "tftp $ramdiskaddr $ramdiskfile;" \ 718 "tftp $loadaddr $bootfile;" \ 719 "tftp $fdtaddr $fdtfile;" \ 720 "bootm $loadaddr $ramdiskaddr $fdtaddr" 721 722 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 723 724 #include <asm/fsl_secure_boot.h> 725 726 #endif /* __CONFIG_H */ 727