1 /* 2 * Copyright 2009-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * Corenet DS style board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #include "../board/freescale/common/ics307_clk.h" 14 15 #ifdef CONFIG_RAMBOOT_PBL 16 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 17 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 18 #define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg 19 #if defined(CONFIG_P3041DS) 20 #define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p3041ds.cfg 21 #elif defined(CONFIG_P4080DS) 22 #define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p4080ds.cfg 23 #elif defined(CONFIG_P5020DS) 24 #define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p5020ds.cfg 25 #elif defined(CONFIG_P5040DS) 26 #define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p5040ds.cfg 27 #endif 28 #endif 29 30 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 31 /* Set 1M boot space */ 32 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 33 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 34 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 35 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 36 #define CONFIG_SYS_NO_FLASH 37 #endif 38 39 /* High Level Configuration Options */ 40 #define CONFIG_BOOKE 41 #define CONFIG_E500 /* BOOKE e500 family */ 42 #define CONFIG_E500MC /* BOOKE e500mc family */ 43 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 44 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ 45 #define CONFIG_MP /* support multiple processors */ 46 47 #ifndef CONFIG_SYS_TEXT_BASE 48 #define CONFIG_SYS_TEXT_BASE 0xeff80000 49 #endif 50 51 #ifndef CONFIG_RESET_VECTOR_ADDRESS 52 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 53 #endif 54 55 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 56 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 57 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 58 #define CONFIG_PCI /* Enable PCI/PCIE */ 59 #define CONFIG_PCIE1 /* PCIE controler 1 */ 60 #define CONFIG_PCIE2 /* PCIE controler 2 */ 61 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 62 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 63 64 #define CONFIG_FSL_LAW /* Use common FSL init code */ 65 66 #define CONFIG_ENV_OVERWRITE 67 68 #ifdef CONFIG_SYS_NO_FLASH 69 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) 70 #define CONFIG_ENV_IS_NOWHERE 71 #endif 72 #else 73 #define CONFIG_FLASH_CFI_DRIVER 74 #define CONFIG_SYS_FLASH_CFI 75 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 76 #endif 77 78 #if defined(CONFIG_SPIFLASH) 79 #define CONFIG_SYS_EXTRA_ENV_RELOC 80 #define CONFIG_ENV_IS_IN_SPI_FLASH 81 #define CONFIG_ENV_SPI_BUS 0 82 #define CONFIG_ENV_SPI_CS 0 83 #define CONFIG_ENV_SPI_MAX_HZ 10000000 84 #define CONFIG_ENV_SPI_MODE 0 85 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 86 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 87 #define CONFIG_ENV_SECT_SIZE 0x10000 88 #elif defined(CONFIG_SDCARD) 89 #define CONFIG_SYS_EXTRA_ENV_RELOC 90 #define CONFIG_ENV_IS_IN_MMC 91 #define CONFIG_FSL_FIXED_MMC_LOCATION 92 #define CONFIG_SYS_MMC_ENV_DEV 0 93 #define CONFIG_ENV_SIZE 0x2000 94 #define CONFIG_ENV_OFFSET (512 * 1097) 95 #elif defined(CONFIG_NAND) 96 #define CONFIG_SYS_EXTRA_ENV_RELOC 97 #define CONFIG_ENV_IS_IN_NAND 98 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 99 #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 100 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 101 #define CONFIG_ENV_IS_IN_REMOTE 102 #define CONFIG_ENV_ADDR 0xffe20000 103 #define CONFIG_ENV_SIZE 0x2000 104 #elif defined(CONFIG_ENV_IS_NOWHERE) 105 #define CONFIG_ENV_SIZE 0x2000 106 #else 107 #define CONFIG_ENV_IS_IN_FLASH 108 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 109 #define CONFIG_ENV_SIZE 0x2000 110 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 111 #endif 112 113 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 114 115 /* 116 * These can be toggled for performance analysis, otherwise use default. 117 */ 118 #define CONFIG_SYS_CACHE_STASHING 119 #define CONFIG_BACKSIDE_L2_CACHE 120 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 121 #define CONFIG_BTB /* toggle branch predition */ 122 #define CONFIG_DDR_ECC 123 #ifdef CONFIG_DDR_ECC 124 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 125 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 126 #endif 127 128 #define CONFIG_ENABLE_36BIT_PHYS 129 130 #ifdef CONFIG_PHYS_64BIT 131 #define CONFIG_ADDR_MAP 132 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 133 #endif 134 135 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 136 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 137 #define CONFIG_SYS_MEMTEST_END 0x00400000 138 #define CONFIG_SYS_ALT_MEMTEST 139 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 140 141 /* 142 * Config the L3 Cache as L3 SRAM 143 */ 144 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 145 #ifdef CONFIG_PHYS_64BIT 146 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) 147 #else 148 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 149 #endif 150 #define CONFIG_SYS_L3_SIZE (1024 << 10) 151 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 152 153 #ifdef CONFIG_PHYS_64BIT 154 #define CONFIG_SYS_DCSRBAR 0xf0000000 155 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 156 #endif 157 158 /* EEPROM */ 159 #define CONFIG_ID_EEPROM 160 #define CONFIG_SYS_I2C_EEPROM_NXID 161 #define CONFIG_SYS_EEPROM_BUS_NUM 0 162 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 163 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 164 165 /* 166 * DDR Setup 167 */ 168 #define CONFIG_VERY_BIG_RAM 169 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 170 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 171 172 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 173 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 174 175 #define CONFIG_DDR_SPD 176 #define CONFIG_FSL_DDR3 177 178 #define CONFIG_SYS_SPD_BUS_NUM 1 179 #define SPD_EEPROM_ADDRESS1 0x51 180 #define SPD_EEPROM_ADDRESS2 0x52 181 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 182 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 183 184 /* 185 * Local Bus Definitions 186 */ 187 188 /* Set the local bus clock 1/8 of platform clock */ 189 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 190 191 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */ 192 #ifdef CONFIG_PHYS_64BIT 193 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 194 #else 195 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 196 #endif 197 198 #define CONFIG_SYS_FLASH_BR_PRELIM \ 199 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \ 200 | BR_PS_16 | BR_V) 201 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 202 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 203 204 #define CONFIG_SYS_BR1_PRELIM \ 205 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 206 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 207 208 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 209 #ifdef CONFIG_PHYS_64BIT 210 #define PIXIS_BASE_PHYS 0xfffdf0000ull 211 #else 212 #define PIXIS_BASE_PHYS PIXIS_BASE 213 #endif 214 215 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 216 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 217 218 #define PIXIS_LBMAP_SWITCH 7 219 #define PIXIS_LBMAP_MASK 0xf0 220 #define PIXIS_LBMAP_SHIFT 4 221 #define PIXIS_LBMAP_ALTBANK 0x40 222 223 #define CONFIG_SYS_FLASH_QUIET_TEST 224 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 225 226 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 227 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 228 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 229 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 230 231 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 232 233 #if defined(CONFIG_RAMBOOT_PBL) 234 #define CONFIG_SYS_RAMBOOT 235 #endif 236 237 /* Nand Flash */ 238 #ifdef CONFIG_NAND_FSL_ELBC 239 #define CONFIG_SYS_NAND_BASE 0xffa00000 240 #ifdef CONFIG_PHYS_64BIT 241 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 242 #else 243 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 244 #endif 245 246 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 247 #define CONFIG_SYS_MAX_NAND_DEVICE 1 248 #define CONFIG_MTD_NAND_VERIFY_WRITE 249 #define CONFIG_CMD_NAND 250 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 251 252 /* NAND flash config */ 253 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 254 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 255 | BR_PS_8 /* Port Size = 8 bit */ \ 256 | BR_MS_FCM /* MSEL = FCM */ \ 257 | BR_V) /* valid */ 258 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 259 | OR_FCM_PGS /* Large Page*/ \ 260 | OR_FCM_CSCT \ 261 | OR_FCM_CST \ 262 | OR_FCM_CHT \ 263 | OR_FCM_SCY_1 \ 264 | OR_FCM_TRLX \ 265 | OR_FCM_EHTR) 266 267 #ifdef CONFIG_NAND 268 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 269 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 270 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 271 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 272 #else 273 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 274 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 275 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 276 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 277 #endif 278 #else 279 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 280 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 281 #endif /* CONFIG_NAND_FSL_ELBC */ 282 283 #define CONFIG_SYS_FLASH_EMPTY_INFO 284 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 285 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 286 287 #define CONFIG_BOARD_EARLY_INIT_F 288 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 289 #define CONFIG_MISC_INIT_R 290 291 #define CONFIG_HWCONFIG 292 293 /* define to use L1 as initial stack */ 294 #define CONFIG_L1_INIT_RAM 295 #define CONFIG_SYS_INIT_RAM_LOCK 296 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 297 #ifdef CONFIG_PHYS_64BIT 298 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 299 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 300 /* The assembler doesn't like typecast */ 301 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 302 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 303 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 304 #else 305 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ 306 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 307 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 308 #endif 309 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 310 311 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 312 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 313 314 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 315 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 316 317 /* Serial Port - controlled on board with jumper J8 318 * open - index 2 319 * shorted - index 1 320 */ 321 #define CONFIG_CONS_INDEX 1 322 #define CONFIG_SYS_NS16550 323 #define CONFIG_SYS_NS16550_SERIAL 324 #define CONFIG_SYS_NS16550_REG_SIZE 1 325 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 326 327 #define CONFIG_SYS_BAUDRATE_TABLE \ 328 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 329 330 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 331 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 332 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 333 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 334 335 /* Use the HUSH parser */ 336 #define CONFIG_SYS_HUSH_PARSER 337 338 /* pass open firmware flat tree */ 339 #define CONFIG_OF_LIBFDT 340 #define CONFIG_OF_BOARD_SETUP 341 #define CONFIG_OF_STDOUT_VIA_ALIAS 342 343 /* new uImage format support */ 344 #define CONFIG_FIT 345 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 346 347 /* I2C */ 348 #define CONFIG_SYS_I2C 349 #define CONFIG_SYS_I2C_FSL 350 #define CONFIG_SYS_FSL_I2C_SPEED 400000 351 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 352 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 353 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 354 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 355 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 356 357 /* 358 * RapidIO 359 */ 360 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 361 #ifdef CONFIG_PHYS_64BIT 362 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 363 #else 364 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 365 #endif 366 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 367 368 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 369 #ifdef CONFIG_PHYS_64BIT 370 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 371 #else 372 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 373 #endif 374 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 375 376 /* 377 * for slave u-boot IMAGE instored in master memory space, 378 * PHYS must be aligned based on the SIZE 379 */ 380 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull 381 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull 382 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */ 383 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull 384 /* 385 * for slave UCODE and ENV instored in master memory space, 386 * PHYS must be aligned based on the SIZE 387 */ 388 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull 389 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 390 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 391 392 /* slave core release by master*/ 393 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 394 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 395 396 /* 397 * SRIO_PCIE_BOOT - SLAVE 398 */ 399 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 400 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 401 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 402 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 403 #endif 404 405 /* 406 * eSPI - Enhanced SPI 407 */ 408 #define CONFIG_FSL_ESPI 409 #define CONFIG_SPI_FLASH 410 #define CONFIG_SPI_FLASH_SPANSION 411 #define CONFIG_CMD_SF 412 #define CONFIG_SF_DEFAULT_SPEED 10000000 413 #define CONFIG_SF_DEFAULT_MODE 0 414 415 /* 416 * General PCI 417 * Memory space is mapped 1-1, but I/O space must start from 0. 418 */ 419 420 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 421 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 422 #ifdef CONFIG_PHYS_64BIT 423 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 424 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 425 #else 426 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 427 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 428 #endif 429 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 430 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 431 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 432 #ifdef CONFIG_PHYS_64BIT 433 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 434 #else 435 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 436 #endif 437 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 438 439 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 440 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 441 #ifdef CONFIG_PHYS_64BIT 442 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 443 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 444 #else 445 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 446 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 447 #endif 448 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 449 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 450 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 451 #ifdef CONFIG_PHYS_64BIT 452 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 453 #else 454 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 455 #endif 456 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 457 458 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 459 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 460 #ifdef CONFIG_PHYS_64BIT 461 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 462 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 463 #else 464 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 465 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 466 #endif 467 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 468 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 469 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 470 #ifdef CONFIG_PHYS_64BIT 471 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 472 #else 473 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 474 #endif 475 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 476 477 /* controller 4, Base address 203000 */ 478 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 479 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 480 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 481 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 482 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 483 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 484 485 /* Qman/Bman */ 486 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 487 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 488 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 489 #ifdef CONFIG_PHYS_64BIT 490 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 491 #else 492 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 493 #endif 494 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 495 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 496 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 497 #ifdef CONFIG_PHYS_64BIT 498 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 499 #else 500 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 501 #endif 502 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 503 504 #define CONFIG_SYS_DPAA_FMAN 505 #define CONFIG_SYS_DPAA_PME 506 /* Default address of microcode for the Linux Fman driver */ 507 #if defined(CONFIG_SPIFLASH) 508 /* 509 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 510 * env, so we got 0x110000. 511 */ 512 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 513 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 514 #elif defined(CONFIG_SDCARD) 515 /* 516 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 517 * about 545KB (1089 blocks), Env is stored after the image, and the env size is 518 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. 519 */ 520 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 521 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) 522 #elif defined(CONFIG_NAND) 523 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 524 #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) 525 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 526 /* 527 * Slave has no ucode locally, it can fetch this from remote. When implementing 528 * in two corenet boards, slave's ucode could be stored in master's memory 529 * space, the address can be mapped from slave TLB->slave LAW-> 530 * slave SRIO or PCIE outbound window->master inbound window-> 531 * master LAW->the ucode address in master's memory space. 532 */ 533 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 534 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 535 #else 536 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 537 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 538 #endif 539 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 540 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 541 542 #ifdef CONFIG_SYS_DPAA_FMAN 543 #define CONFIG_FMAN_ENET 544 #define CONFIG_PHYLIB_10G 545 #define CONFIG_PHY_VITESSE 546 #define CONFIG_PHY_TERANETICS 547 #endif 548 549 #ifdef CONFIG_PCI 550 #define CONFIG_PCI_INDIRECT_BRIDGE 551 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 552 #define CONFIG_E1000 553 554 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 555 #define CONFIG_DOS_PARTITION 556 #endif /* CONFIG_PCI */ 557 558 /* SATA */ 559 #ifdef CONFIG_FSL_SATA_V2 560 #define CONFIG_LIBATA 561 #define CONFIG_FSL_SATA 562 563 #define CONFIG_SYS_SATA_MAX_DEVICE 2 564 #define CONFIG_SATA1 565 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 566 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 567 #define CONFIG_SATA2 568 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 569 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 570 571 #define CONFIG_LBA48 572 #define CONFIG_CMD_SATA 573 #define CONFIG_DOS_PARTITION 574 #define CONFIG_CMD_EXT2 575 #endif 576 577 #ifdef CONFIG_FMAN_ENET 578 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c 579 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d 580 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e 581 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f 582 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 583 584 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c 585 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d 586 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e 587 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f 588 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0 589 590 #define CONFIG_SYS_TBIPA_VALUE 8 591 #define CONFIG_MII /* MII PHY management */ 592 #define CONFIG_ETHPRIME "FM1@DTSEC1" 593 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 594 #endif 595 596 /* 597 * Environment 598 */ 599 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 600 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 601 602 /* 603 * Command line configuration. 604 */ 605 #include <config_cmd_default.h> 606 607 #define CONFIG_CMD_DHCP 608 #define CONFIG_CMD_ELF 609 #define CONFIG_CMD_ERRATA 610 #define CONFIG_CMD_GREPENV 611 #define CONFIG_CMD_IRQ 612 #define CONFIG_CMD_I2C 613 #define CONFIG_CMD_MII 614 #define CONFIG_CMD_PING 615 #define CONFIG_CMD_SETEXPR 616 #define CONFIG_CMD_REGINFO 617 618 #ifdef CONFIG_PCI 619 #define CONFIG_CMD_PCI 620 #define CONFIG_CMD_NET 621 #endif 622 623 /* 624 * USB 625 */ 626 #define CONFIG_HAS_FSL_DR_USB 627 #define CONFIG_HAS_FSL_MPH_USB 628 629 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 630 #define CONFIG_CMD_USB 631 #define CONFIG_USB_STORAGE 632 #define CONFIG_USB_EHCI 633 #define CONFIG_USB_EHCI_FSL 634 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 635 #define CONFIG_CMD_EXT2 636 #endif 637 638 #ifdef CONFIG_MMC 639 #define CONFIG_FSL_ESDHC 640 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 641 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 642 #define CONFIG_CMD_MMC 643 #define CONFIG_GENERIC_MMC 644 #define CONFIG_CMD_EXT2 645 #define CONFIG_CMD_FAT 646 #define CONFIG_DOS_PARTITION 647 #endif 648 649 /* 650 * Miscellaneous configurable options 651 */ 652 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 653 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 654 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 655 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 656 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 657 #ifdef CONFIG_CMD_KGDB 658 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 659 #else 660 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 661 #endif 662 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 663 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 664 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 665 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 666 667 /* 668 * For booting Linux, the board info and command line data 669 * have to be in the first 64 MB of memory, since this is 670 * the maximum mapped by the Linux kernel during initialization. 671 */ 672 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 673 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 674 675 #ifdef CONFIG_CMD_KGDB 676 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 677 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 678 #endif 679 680 /* 681 * Environment Configuration 682 */ 683 #define CONFIG_ROOTPATH "/opt/nfsroot" 684 #define CONFIG_BOOTFILE "uImage" 685 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 686 687 /* default location for tftp and bootm */ 688 #define CONFIG_LOADADDR 1000000 689 690 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 691 692 #define CONFIG_BAUDRATE 115200 693 694 #ifdef CONFIG_P4080DS 695 #define __USB_PHY_TYPE ulpi 696 #else 697 #define __USB_PHY_TYPE utmi 698 #endif 699 700 #define CONFIG_EXTRA_ENV_SETTINGS \ 701 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 702 "bank_intlv=cs0_cs1;" \ 703 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 704 "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 705 "netdev=eth0\0" \ 706 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 707 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 708 "tftpflash=tftpboot $loadaddr $uboot && " \ 709 "protect off $ubootaddr +$filesize && " \ 710 "erase $ubootaddr +$filesize && " \ 711 "cp.b $loadaddr $ubootaddr $filesize && " \ 712 "protect on $ubootaddr +$filesize && " \ 713 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 714 "consoledev=ttyS0\0" \ 715 "ramdiskaddr=2000000\0" \ 716 "ramdiskfile=p4080ds/ramdisk.uboot\0" \ 717 "fdtaddr=c00000\0" \ 718 "fdtfile=p4080ds/p4080ds.dtb\0" \ 719 "bdev=sda3\0" \ 720 "c=ffe\0" 721 722 #define CONFIG_HDBOOT \ 723 "setenv bootargs root=/dev/$bdev rw " \ 724 "console=$consoledev,$baudrate $othbootargs;" \ 725 "tftp $loadaddr $bootfile;" \ 726 "tftp $fdtaddr $fdtfile;" \ 727 "bootm $loadaddr - $fdtaddr" 728 729 #define CONFIG_NFSBOOTCOMMAND \ 730 "setenv bootargs root=/dev/nfs rw " \ 731 "nfsroot=$serverip:$rootpath " \ 732 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 733 "console=$consoledev,$baudrate $othbootargs;" \ 734 "tftp $loadaddr $bootfile;" \ 735 "tftp $fdtaddr $fdtfile;" \ 736 "bootm $loadaddr - $fdtaddr" 737 738 #define CONFIG_RAMBOOTCOMMAND \ 739 "setenv bootargs root=/dev/ram rw " \ 740 "console=$consoledev,$baudrate $othbootargs;" \ 741 "tftp $ramdiskaddr $ramdiskfile;" \ 742 "tftp $loadaddr $bootfile;" \ 743 "tftp $fdtaddr $fdtfile;" \ 744 "bootm $loadaddr $ramdiskaddr $fdtaddr" 745 746 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 747 748 #include <asm/fsl_secure_boot.h> 749 750 #endif /* __CONFIG_H */ 751