1 /* 2 * Copyright 2009-2011 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * Corenet DS style board configuration file 25 */ 26 #ifndef __CONFIG_H 27 #define __CONFIG_H 28 29 #include "../board/freescale/common/ics307_clk.h" 30 31 #ifdef CONFIG_RAMBOOT_PBL 32 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 33 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 34 #endif 35 36 /* High Level Configuration Options */ 37 #define CONFIG_BOOKE 38 #define CONFIG_E500 /* BOOKE e500 family */ 39 #define CONFIG_E500MC /* BOOKE e500mc family */ 40 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 41 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ 42 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 43 #define CONFIG_MP /* support multiple processors */ 44 45 #ifndef CONFIG_SYS_TEXT_BASE 46 #define CONFIG_SYS_TEXT_BASE 0xeff80000 47 #endif 48 49 #ifndef CONFIG_RESET_VECTOR_ADDRESS 50 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 51 #endif 52 53 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 54 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 55 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 56 #define CONFIG_PCI /* Enable PCI/PCIE */ 57 #define CONFIG_PCIE1 /* PCIE controler 1 */ 58 #define CONFIG_PCIE2 /* PCIE controler 2 */ 59 #define CONFIG_PCIE3 /* PCIE controler 3 */ 60 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 61 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 62 63 #define CONFIG_SYS_SRIO 64 #define CONFIG_SRIO1 /* SRIO port 1 */ 65 #define CONFIG_SRIO2 /* SRIO port 2 */ 66 67 #define CONFIG_FSL_LAW /* Use common FSL init code */ 68 69 #define CONFIG_ENV_OVERWRITE 70 71 #ifdef CONFIG_SYS_NO_FLASH 72 #define CONFIG_ENV_IS_NOWHERE 73 #else 74 #define CONFIG_FLASH_CFI_DRIVER 75 #define CONFIG_SYS_FLASH_CFI 76 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 77 #endif 78 79 #if defined(CONFIG_SPIFLASH) 80 #define CONFIG_SYS_EXTRA_ENV_RELOC 81 #define CONFIG_ENV_IS_IN_SPI_FLASH 82 #define CONFIG_ENV_SPI_BUS 0 83 #define CONFIG_ENV_SPI_CS 0 84 #define CONFIG_ENV_SPI_MAX_HZ 10000000 85 #define CONFIG_ENV_SPI_MODE 0 86 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 87 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 88 #define CONFIG_ENV_SECT_SIZE 0x10000 89 #elif defined(CONFIG_SDCARD) 90 #define CONFIG_SYS_EXTRA_ENV_RELOC 91 #define CONFIG_ENV_IS_IN_MMC 92 #define CONFIG_SYS_MMC_ENV_DEV 0 93 #define CONFIG_ENV_SIZE 0x2000 94 #define CONFIG_ENV_OFFSET (512 * 1097) 95 #elif defined(CONFIG_NAND) 96 #define CONFIG_SYS_EXTRA_ENV_RELOC 97 #define CONFIG_ENV_IS_IN_NAND 98 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 99 #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 100 #else 101 #define CONFIG_ENV_IS_IN_FLASH 102 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 103 #define CONFIG_ENV_SIZE 0x2000 104 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 105 #endif 106 107 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 108 109 /* 110 * These can be toggled for performance analysis, otherwise use default. 111 */ 112 #define CONFIG_SYS_CACHE_STASHING 113 #define CONFIG_BACKSIDE_L2_CACHE 114 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 115 #define CONFIG_BTB /* toggle branch predition */ 116 #define CONFIG_DDR_ECC 117 #ifdef CONFIG_DDR_ECC 118 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 119 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 120 #endif 121 122 #define CONFIG_ENABLE_36BIT_PHYS 123 124 #ifdef CONFIG_PHYS_64BIT 125 #define CONFIG_ADDR_MAP 126 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 127 #endif 128 129 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 130 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 131 #define CONFIG_SYS_MEMTEST_END 0x00400000 132 #define CONFIG_SYS_ALT_MEMTEST 133 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 134 135 /* 136 * Config the L3 Cache as L3 SRAM 137 */ 138 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 139 #ifdef CONFIG_PHYS_64BIT 140 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) 141 #else 142 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 143 #endif 144 #define CONFIG_SYS_L3_SIZE (1024 << 10) 145 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 146 147 /* 148 * Base addresses -- Note these are effective addresses where the 149 * actual resources get mapped (not physical addresses) 150 */ 151 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 /* CCSRBAR Default */ 152 #define CONFIG_SYS_CCSRBAR 0xfe000000 /* relocated CCSRBAR */ 153 #ifdef CONFIG_PHYS_64BIT 154 #define CONFIG_SYS_CCSRBAR_PHYS 0xffe000000ull /* physical addr of CCSRBAR */ 155 #else 156 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ 157 #endif 158 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 159 160 #ifdef CONFIG_PHYS_64BIT 161 #define CONFIG_SYS_DCSRBAR 0xf0000000 162 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 163 #endif 164 165 /* EEPROM */ 166 #define CONFIG_ID_EEPROM 167 #define CONFIG_SYS_I2C_EEPROM_NXID 168 #define CONFIG_SYS_EEPROM_BUS_NUM 0 169 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 170 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 171 172 /* 173 * DDR Setup 174 */ 175 #define CONFIG_VERY_BIG_RAM 176 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 177 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 178 179 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 180 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 181 182 #define CONFIG_DDR_SPD 183 #define CONFIG_FSL_DDR3 184 185 #define CONFIG_SYS_SPD_BUS_NUM 1 186 #define SPD_EEPROM_ADDRESS1 0x51 187 #define SPD_EEPROM_ADDRESS2 0x52 188 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 189 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 190 191 /* 192 * Local Bus Definitions 193 */ 194 195 /* Set the local bus clock 1/8 of platform clock */ 196 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 197 198 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */ 199 #ifdef CONFIG_PHYS_64BIT 200 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 201 #else 202 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 203 #endif 204 205 #define CONFIG_SYS_FLASH_BR_PRELIM \ 206 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \ 207 | BR_PS_16 | BR_V) 208 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 209 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 210 211 #define CONFIG_SYS_BR1_PRELIM \ 212 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 213 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 214 215 #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ 216 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 217 #ifdef CONFIG_PHYS_64BIT 218 #define PIXIS_BASE_PHYS 0xfffdf0000ull 219 #else 220 #define PIXIS_BASE_PHYS PIXIS_BASE 221 #endif 222 223 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 224 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 225 226 #define PIXIS_LBMAP_SWITCH 7 227 #define PIXIS_LBMAP_MASK 0xf0 228 #define PIXIS_LBMAP_SHIFT 4 229 #define PIXIS_LBMAP_ALTBANK 0x40 230 231 #define CONFIG_SYS_FLASH_QUIET_TEST 232 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 233 234 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 235 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 236 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 237 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 238 239 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 240 241 #if defined(CONFIG_RAMBOOT_PBL) 242 #define CONFIG_SYS_RAMBOOT 243 #endif 244 245 /* Nand Flash */ 246 #if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) 247 #define CONFIG_NAND_FSL_ELBC 248 #ifdef CONFIG_NAND_FSL_ELBC 249 #define CONFIG_SYS_NAND_BASE 0xffa00000 250 #ifdef CONFIG_PHYS_64BIT 251 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 252 #else 253 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 254 #endif 255 256 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 257 #define CONFIG_SYS_MAX_NAND_DEVICE 1 258 #define CONFIG_MTD_NAND_VERIFY_WRITE 259 #define CONFIG_CMD_NAND 260 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 261 262 /* NAND flash config */ 263 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 264 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 265 | BR_PS_8 /* Port Size = 8 bit */ \ 266 | BR_MS_FCM /* MSEL = FCM */ \ 267 | BR_V) /* valid */ 268 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 269 | OR_FCM_PGS /* Large Page*/ \ 270 | OR_FCM_CSCT \ 271 | OR_FCM_CST \ 272 | OR_FCM_CHT \ 273 | OR_FCM_SCY_1 \ 274 | OR_FCM_TRLX \ 275 | OR_FCM_EHTR) 276 277 #ifdef CONFIG_NAND 278 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 279 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 280 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 281 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 282 #else 283 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 284 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 285 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 286 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 287 #endif 288 #endif /* CONFIG_NAND_FSL_ELBC */ 289 #else 290 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 291 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 292 #endif 293 294 #define CONFIG_SYS_FLASH_EMPTY_INFO 295 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 296 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 297 298 #define CONFIG_BOARD_EARLY_INIT_F 299 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 300 #define CONFIG_MISC_INIT_R 301 302 #define CONFIG_HWCONFIG 303 304 /* define to use L1 as initial stack */ 305 #define CONFIG_L1_INIT_RAM 306 #define CONFIG_SYS_INIT_RAM_LOCK 307 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 308 #ifdef CONFIG_PHYS_64BIT 309 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 310 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 311 /* The assembler doesn't like typecast */ 312 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 313 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 314 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 315 #else 316 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ 317 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 318 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 319 #endif 320 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 321 322 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 323 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 324 325 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 326 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 327 328 /* Serial Port - controlled on board with jumper J8 329 * open - index 2 330 * shorted - index 1 331 */ 332 #define CONFIG_CONS_INDEX 1 333 #define CONFIG_SYS_NS16550 334 #define CONFIG_SYS_NS16550_SERIAL 335 #define CONFIG_SYS_NS16550_REG_SIZE 1 336 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 337 338 #define CONFIG_SYS_BAUDRATE_TABLE \ 339 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 340 341 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 342 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 343 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 344 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 345 346 /* Use the HUSH parser */ 347 #define CONFIG_SYS_HUSH_PARSER 348 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 349 350 /* pass open firmware flat tree */ 351 #define CONFIG_OF_LIBFDT 352 #define CONFIG_OF_BOARD_SETUP 353 #define CONFIG_OF_STDOUT_VIA_ALIAS 354 355 /* new uImage format support */ 356 #define CONFIG_FIT 357 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 358 359 /* I2C */ 360 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 361 #define CONFIG_HARD_I2C /* I2C with hardware support */ 362 #define CONFIG_I2C_MULTI_BUS 363 #define CONFIG_I2C_CMD_TREE 364 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 365 #define CONFIG_SYS_I2C_SLAVE 0x7F 366 #define CONFIG_SYS_I2C_OFFSET 0x118000 367 #define CONFIG_SYS_I2C2_OFFSET 0x118100 368 369 /* 370 * RapidIO 371 */ 372 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 373 #ifdef CONFIG_PHYS_64BIT 374 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 375 #else 376 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 377 #endif 378 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 379 380 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 381 #ifdef CONFIG_PHYS_64BIT 382 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 383 #else 384 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 385 #endif 386 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 387 388 /* 389 * eSPI - Enhanced SPI 390 */ 391 #define CONFIG_FSL_ESPI 392 #define CONFIG_SPI_FLASH 393 #define CONFIG_SPI_FLASH_SPANSION 394 #define CONFIG_CMD_SF 395 #define CONFIG_SF_DEFAULT_SPEED 10000000 396 #define CONFIG_SF_DEFAULT_MODE 0 397 398 /* 399 * General PCI 400 * Memory space is mapped 1-1, but I/O space must start from 0. 401 */ 402 403 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 404 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 405 #ifdef CONFIG_PHYS_64BIT 406 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 407 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 408 #else 409 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 410 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 411 #endif 412 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 413 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 414 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 415 #ifdef CONFIG_PHYS_64BIT 416 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 417 #else 418 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 419 #endif 420 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 421 422 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 423 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 424 #ifdef CONFIG_PHYS_64BIT 425 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 426 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 427 #else 428 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 429 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 430 #endif 431 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 432 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 433 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 434 #ifdef CONFIG_PHYS_64BIT 435 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 436 #else 437 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 438 #endif 439 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 440 441 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 442 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 443 #ifdef CONFIG_PHYS_64BIT 444 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 445 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 446 #else 447 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 448 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 449 #endif 450 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 451 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 452 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 453 #ifdef CONFIG_PHYS_64BIT 454 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 455 #else 456 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 457 #endif 458 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 459 460 /* controller 4, Base address 203000 */ 461 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 462 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 463 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 464 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 465 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 466 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 467 468 /* Qman/Bman */ 469 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 470 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 471 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 472 #ifdef CONFIG_PHYS_64BIT 473 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 474 #else 475 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 476 #endif 477 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 478 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 479 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 480 #ifdef CONFIG_PHYS_64BIT 481 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 482 #else 483 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 484 #endif 485 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 486 487 #define CONFIG_SYS_DPAA_FMAN 488 #define CONFIG_SYS_DPAA_PME 489 /* Default address of microcode for the Linux Fman driver */ 490 #define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000 491 #ifdef CONFIG_PHYS_64BIT 492 #define CONFIG_SYS_FMAN_FW_ADDR_PHYS 0xFEF000000ULL 493 #else 494 #define CONFIG_SYS_FMAN_FW_ADDR_PHYS CONFIG_SYS_FMAN_FW_ADDR 495 #endif 496 497 #ifdef CONFIG_SYS_DPAA_FMAN 498 #define CONFIG_FMAN_ENET 499 #endif 500 501 #ifdef CONFIG_PCI 502 #define CONFIG_NET_MULTI 503 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 504 #define CONFIG_E1000 505 506 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 507 #define CONFIG_DOS_PARTITION 508 #endif /* CONFIG_PCI */ 509 510 /* SATA */ 511 #ifdef CONFIG_FSL_SATA_V2 512 #define CONFIG_LIBATA 513 #define CONFIG_FSL_SATA 514 515 #define CONFIG_SYS_SATA_MAX_DEVICE 2 516 #define CONFIG_SATA1 517 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 518 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 519 #define CONFIG_SATA2 520 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 521 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 522 523 #define CONFIG_LBA48 524 #define CONFIG_CMD_SATA 525 #define CONFIG_DOS_PARTITION 526 #define CONFIG_CMD_EXT2 527 #endif 528 529 #ifdef CONFIG_FMAN_ENET 530 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c 531 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d 532 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e 533 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f 534 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 535 536 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c 537 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d 538 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e 539 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f 540 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0 541 542 #define CONFIG_SYS_TBIPA_VALUE 8 543 #define CONFIG_MII /* MII PHY management */ 544 #define CONFIG_ETHPRIME "FM1@DTSEC1" 545 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 546 #endif 547 548 /* 549 * Environment 550 */ 551 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 552 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 553 554 /* 555 * Command line configuration. 556 */ 557 #include <config_cmd_default.h> 558 559 #define CONFIG_CMD_DHCP 560 #define CONFIG_CMD_ELF 561 #define CONFIG_CMD_ERRATA 562 #define CONFIG_CMD_GREPENV 563 #define CONFIG_CMD_IRQ 564 #define CONFIG_CMD_I2C 565 #define CONFIG_CMD_MII 566 #define CONFIG_CMD_PING 567 #define CONFIG_CMD_SETEXPR 568 569 #ifdef CONFIG_PCI 570 #define CONFIG_CMD_PCI 571 #define CONFIG_CMD_NET 572 #endif 573 574 /* 575 * USB 576 */ 577 #define CONFIG_CMD_USB 578 #define CONFIG_USB_STORAGE 579 #define CONFIG_USB_EHCI 580 #define CONFIG_USB_EHCI_FSL 581 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 582 #define CONFIG_CMD_EXT2 583 584 #define CONFIG_MMC 585 586 #ifdef CONFIG_MMC 587 #define CONFIG_FSL_ESDHC 588 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 589 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 590 #define CONFIG_CMD_MMC 591 #define CONFIG_GENERIC_MMC 592 #define CONFIG_CMD_EXT2 593 #define CONFIG_CMD_FAT 594 #define CONFIG_DOS_PARTITION 595 #endif 596 597 /* 598 * Miscellaneous configurable options 599 */ 600 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 601 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 602 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 603 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 604 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 605 #ifdef CONFIG_CMD_KGDB 606 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 607 #else 608 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 609 #endif 610 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 611 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 612 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 613 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 614 615 /* 616 * For booting Linux, the board info and command line data 617 * have to be in the first 64 MB of memory, since this is 618 * the maximum mapped by the Linux kernel during initialization. 619 */ 620 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 621 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 622 623 #ifdef CONFIG_CMD_KGDB 624 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 625 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 626 #endif 627 628 /* 629 * Environment Configuration 630 */ 631 #define CONFIG_ROOTPATH /opt/nfsroot 632 #define CONFIG_BOOTFILE uImage 633 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 634 635 /* default location for tftp and bootm */ 636 #define CONFIG_LOADADDR 1000000 637 638 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 639 640 #define CONFIG_BAUDRATE 115200 641 642 #if defined(CONFIG_P4080DS) 643 #define __USB_PHY_TYPE ulpi 644 #else 645 #define __USB_PHY_TYPE utmi 646 #endif 647 648 #define CONFIG_EXTRA_ENV_SETTINGS \ 649 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 650 "bank_intlv=cs0_cs1;" \ 651 "usb1:dr_mode=host,phy_type=" MK_STR(__USB_PHY_TYPE) "\0"\ 652 "netdev=eth0\0" \ 653 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 654 "ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0" \ 655 "tftpflash=tftpboot $loadaddr $uboot && " \ 656 "protect off $ubootaddr +$filesize && " \ 657 "erase $ubootaddr +$filesize && " \ 658 "cp.b $loadaddr $ubootaddr $filesize && " \ 659 "protect on $ubootaddr +$filesize && " \ 660 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 661 "consoledev=ttyS0\0" \ 662 "ramdiskaddr=2000000\0" \ 663 "ramdiskfile=p4080ds/ramdisk.uboot\0" \ 664 "fdtaddr=c00000\0" \ 665 "fdtfile=p4080ds/p4080ds.dtb\0" \ 666 "bdev=sda3\0" \ 667 "c=ffe\0" \ 668 "fman_ucode="MK_STR(CONFIG_SYS_FMAN_FW_ADDR_PHYS)"\0" 669 670 #define CONFIG_HDBOOT \ 671 "setenv bootargs root=/dev/$bdev rw " \ 672 "console=$consoledev,$baudrate $othbootargs;" \ 673 "tftp $loadaddr $bootfile;" \ 674 "tftp $fdtaddr $fdtfile;" \ 675 "bootm $loadaddr - $fdtaddr" 676 677 #define CONFIG_NFSBOOTCOMMAND \ 678 "setenv bootargs root=/dev/nfs rw " \ 679 "nfsroot=$serverip:$rootpath " \ 680 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 681 "console=$consoledev,$baudrate $othbootargs;" \ 682 "tftp $loadaddr $bootfile;" \ 683 "tftp $fdtaddr $fdtfile;" \ 684 "bootm $loadaddr - $fdtaddr" 685 686 #define CONFIG_RAMBOOTCOMMAND \ 687 "setenv bootargs root=/dev/ram rw " \ 688 "console=$consoledev,$baudrate $othbootargs;" \ 689 "tftp $ramdiskaddr $ramdiskfile;" \ 690 "tftp $loadaddr $bootfile;" \ 691 "tftp $fdtaddr $fdtfile;" \ 692 "bootm $loadaddr $ramdiskaddr $fdtaddr" 693 694 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 695 696 #endif /* __CONFIG_H */ 697