1 /* 2 * Copyright 2009-2011 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * Corenet DS style board configuration file 25 */ 26 #ifndef __CONFIG_H 27 #define __CONFIG_H 28 29 #include "../board/freescale/common/ics307_clk.h" 30 31 #ifdef CONFIG_RAMBOOT_PBL 32 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 33 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 34 #endif 35 36 /* High Level Configuration Options */ 37 #define CONFIG_BOOKE 38 #define CONFIG_E500 /* BOOKE e500 family */ 39 #define CONFIG_E500MC /* BOOKE e500mc family */ 40 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 41 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ 42 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 43 #define CONFIG_MP /* support multiple processors */ 44 45 #ifndef CONFIG_SYS_TEXT_BASE 46 #define CONFIG_SYS_TEXT_BASE 0xeff80000 47 #endif 48 49 #ifndef CONFIG_RESET_VECTOR_ADDRESS 50 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 51 #endif 52 53 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 54 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 55 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 56 #define CONFIG_PCI /* Enable PCI/PCIE */ 57 #define CONFIG_PCIE1 /* PCIE controler 1 */ 58 #define CONFIG_PCIE2 /* PCIE controler 2 */ 59 #define CONFIG_PCIE3 /* PCIE controler 3 */ 60 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 61 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 62 63 #define CONFIG_SYS_SRIO 64 #define CONFIG_SRIO1 /* SRIO port 1 */ 65 #define CONFIG_SRIO2 /* SRIO port 2 */ 66 67 #define CONFIG_FSL_LAW /* Use common FSL init code */ 68 69 #define CONFIG_ENV_OVERWRITE 70 71 #if defined(CONFIG_RAMBOOT_PBL) 72 #define CONFIG_SYS_NO_FLASH /* Store ENV in memory only */ 73 #endif 74 75 #ifdef CONFIG_SYS_NO_FLASH 76 #define CONFIG_ENV_IS_NOWHERE 77 #else 78 #define CONFIG_ENV_IS_IN_FLASH 79 #define CONFIG_FLASH_CFI_DRIVER 80 #define CONFIG_SYS_FLASH_CFI 81 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 82 #endif 83 84 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 85 86 /* 87 * These can be toggled for performance analysis, otherwise use default. 88 */ 89 #define CONFIG_SYS_CACHE_STASHING 90 #define CONFIG_BACKSIDE_L2_CACHE 91 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 92 #define CONFIG_BTB /* toggle branch predition */ 93 #define CONFIG_DDR_ECC 94 #ifdef CONFIG_DDR_ECC 95 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 96 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 97 #endif 98 99 #define CONFIG_ENABLE_36BIT_PHYS 100 101 #ifdef CONFIG_PHYS_64BIT 102 #define CONFIG_ADDR_MAP 103 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 104 #endif 105 106 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 107 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 108 #define CONFIG_SYS_MEMTEST_END 0x00400000 109 #define CONFIG_SYS_ALT_MEMTEST 110 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 111 112 /* 113 * Config the L3 Cache as L3 SRAM 114 */ 115 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 116 #ifdef CONFIG_PHYS_64BIT 117 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) 118 #else 119 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 120 #endif 121 #define CONFIG_SYS_L3_SIZE (1024 << 10) 122 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 123 124 /* 125 * Base addresses -- Note these are effective addresses where the 126 * actual resources get mapped (not physical addresses) 127 */ 128 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 /* CCSRBAR Default */ 129 #define CONFIG_SYS_CCSRBAR 0xfe000000 /* relocated CCSRBAR */ 130 #ifdef CONFIG_PHYS_64BIT 131 #define CONFIG_SYS_CCSRBAR_PHYS 0xffe000000ull /* physical addr of CCSRBAR */ 132 #else 133 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ 134 #endif 135 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 136 137 #ifdef CONFIG_PHYS_64BIT 138 #define CONFIG_SYS_DCSRBAR 0xf0000000 139 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 140 #endif 141 142 /* EEPROM */ 143 #define CONFIG_ID_EEPROM 144 #define CONFIG_SYS_I2C_EEPROM_NXID 145 #define CONFIG_SYS_EEPROM_BUS_NUM 0 146 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 147 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 148 149 /* 150 * DDR Setup 151 */ 152 #define CONFIG_VERY_BIG_RAM 153 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 154 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 155 156 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 157 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 158 159 #define CONFIG_DDR_SPD 160 #define CONFIG_FSL_DDR3 161 162 #define CONFIG_SYS_SPD_BUS_NUM 1 163 #define SPD_EEPROM_ADDRESS1 0x51 164 #define SPD_EEPROM_ADDRESS2 0x52 165 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 166 167 /* 168 * Local Bus Definitions 169 */ 170 171 /* Set the local bus clock 1/8 of platform clock */ 172 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 173 174 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */ 175 #ifdef CONFIG_PHYS_64BIT 176 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 177 #else 178 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 179 #endif 180 181 #define CONFIG_SYS_BR0_PRELIM \ 182 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \ 183 BR_PS_16 | BR_V) 184 #define CONFIG_SYS_OR0_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 185 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 186 187 #define CONFIG_SYS_BR1_PRELIM \ 188 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 189 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 190 191 #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ 192 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 193 #ifdef CONFIG_PHYS_64BIT 194 #define PIXIS_BASE_PHYS 0xfffdf0000ull 195 #else 196 #define PIXIS_BASE_PHYS PIXIS_BASE 197 #endif 198 199 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 200 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 201 202 #define PIXIS_LBMAP_SWITCH 7 203 #define PIXIS_LBMAP_MASK 0xf0 204 #define PIXIS_LBMAP_SHIFT 4 205 #define PIXIS_LBMAP_ALTBANK 0x40 206 207 #define CONFIG_SYS_FLASH_QUIET_TEST 208 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 209 210 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 211 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 212 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 213 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 214 215 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 216 217 #if defined(CONFIG_RAMBOOT_PBL) 218 #define CONFIG_SYS_RAMBOOT 219 #endif 220 221 #define CONFIG_SYS_FLASH_EMPTY_INFO 222 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 223 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 224 225 #define CONFIG_BOARD_EARLY_INIT_F 226 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 227 #define CONFIG_MISC_INIT_R 228 229 #define CONFIG_HWCONFIG 230 231 /* define to use L1 as initial stack */ 232 #define CONFIG_L1_INIT_RAM 233 #define CONFIG_SYS_INIT_RAM_LOCK 234 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 235 #ifdef CONFIG_PHYS_64BIT 236 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 237 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 238 /* The assembler doesn't like typecast */ 239 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 240 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 241 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 242 #else 243 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ 244 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 245 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 246 #endif 247 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 248 249 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 250 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 251 252 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 253 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 254 255 /* Serial Port - controlled on board with jumper J8 256 * open - index 2 257 * shorted - index 1 258 */ 259 #define CONFIG_CONS_INDEX 1 260 #define CONFIG_SYS_NS16550 261 #define CONFIG_SYS_NS16550_SERIAL 262 #define CONFIG_SYS_NS16550_REG_SIZE 1 263 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 264 265 #define CONFIG_SYS_BAUDRATE_TABLE \ 266 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 267 268 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 269 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 270 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 271 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 272 273 /* Use the HUSH parser */ 274 #define CONFIG_SYS_HUSH_PARSER 275 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 276 277 /* pass open firmware flat tree */ 278 #define CONFIG_OF_LIBFDT 279 #define CONFIG_OF_BOARD_SETUP 280 #define CONFIG_OF_STDOUT_VIA_ALIAS 281 282 /* new uImage format support */ 283 #define CONFIG_FIT 284 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 285 286 /* I2C */ 287 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 288 #define CONFIG_HARD_I2C /* I2C with hardware support */ 289 #define CONFIG_I2C_MULTI_BUS 290 #define CONFIG_I2C_CMD_TREE 291 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 292 #define CONFIG_SYS_I2C_SLAVE 0x7F 293 #define CONFIG_SYS_I2C_OFFSET 0x118000 294 #define CONFIG_SYS_I2C2_OFFSET 0x118100 295 296 /* 297 * RapidIO 298 */ 299 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 300 #ifdef CONFIG_PHYS_64BIT 301 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 302 #else 303 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 304 #endif 305 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 306 307 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 308 #ifdef CONFIG_PHYS_64BIT 309 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 310 #else 311 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 312 #endif 313 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 314 315 /* 316 * General PCI 317 * Memory space is mapped 1-1, but I/O space must start from 0. 318 */ 319 320 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 321 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 322 #ifdef CONFIG_PHYS_64BIT 323 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 324 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 325 #else 326 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 327 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 328 #endif 329 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 330 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 331 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 332 #ifdef CONFIG_PHYS_64BIT 333 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 334 #else 335 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 336 #endif 337 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 338 339 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 340 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 341 #ifdef CONFIG_PHYS_64BIT 342 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 343 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 344 #else 345 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 346 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 347 #endif 348 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 349 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 350 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 351 #ifdef CONFIG_PHYS_64BIT 352 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 353 #else 354 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 355 #endif 356 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 357 358 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 359 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xe0000000 360 #ifdef CONFIG_PHYS_64BIT 361 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 362 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 363 #else 364 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 365 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 366 #endif 367 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 368 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 369 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 370 #ifdef CONFIG_PHYS_64BIT 371 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 372 #else 373 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 374 #endif 375 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 376 377 /* controller 4, Base address 203000 */ 378 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 379 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 380 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 381 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 382 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 383 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 384 385 /* Qman/Bman */ 386 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 387 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 388 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 389 #ifdef CONFIG_PHYS_64BIT 390 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 391 #else 392 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 393 #endif 394 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 395 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 396 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 397 #ifdef CONFIG_PHYS_64BIT 398 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 399 #else 400 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 401 #endif 402 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 403 404 #define CONFIG_SYS_DPAA_FMAN 405 #define CONFIG_SYS_DPAA_PME 406 /* Default address of microcode for the Linux Fman driver */ 407 #define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000 408 #ifdef CONFIG_PHYS_64BIT 409 #define CONFIG_SYS_FMAN_FW_ADDR_PHYS 0xFEF000000ULL 410 #else 411 #define CONFIG_SYS_FMAN_FW_ADDR_PHYS CONFIG_SYS_FMAN_FW_ADDR 412 #endif 413 414 #ifdef CONFIG_SYS_DPAA_FMAN 415 #define CONFIG_FMAN_ENET 416 #endif 417 418 #ifdef CONFIG_PCI 419 #define CONFIG_NET_MULTI 420 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 421 #define CONFIG_E1000 422 423 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 424 #define CONFIG_DOS_PARTITION 425 #endif /* CONFIG_PCI */ 426 427 /* SATA */ 428 #ifdef CONFIG_FSL_SATA_V2 429 #define CONFIG_LIBATA 430 #define CONFIG_FSL_SATA 431 432 #define CONFIG_SYS_SATA_MAX_DEVICE 2 433 #define CONFIG_SATA1 434 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 435 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 436 #define CONFIG_SATA2 437 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 438 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 439 440 #define CONFIG_LBA48 441 #define CONFIG_CMD_SATA 442 #define CONFIG_DOS_PARTITION 443 #define CONFIG_CMD_EXT2 444 #endif 445 446 #ifdef CONFIG_FMAN_ENET 447 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c 448 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d 449 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e 450 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f 451 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 452 453 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c 454 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d 455 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e 456 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f 457 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0 458 459 #define CONFIG_SYS_TBIPA_VALUE 8 460 #define CONFIG_MII /* MII PHY management */ 461 #define CONFIG_ETHPRIME "FM1@DTSEC1" 462 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 463 #endif 464 465 /* 466 * Environment 467 */ 468 #define CONFIG_ENV_SIZE 0x2000 469 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 470 471 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 472 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 473 474 /* 475 * Command line configuration. 476 */ 477 #include <config_cmd_default.h> 478 479 #define CONFIG_CMD_ELF 480 #define CONFIG_CMD_ERRATA 481 #define CONFIG_CMD_IRQ 482 #define CONFIG_CMD_I2C 483 #define CONFIG_CMD_MII 484 #define CONFIG_CMD_PING 485 #define CONFIG_CMD_SETEXPR 486 #define CONFIG_CMD_DHCP 487 488 #ifdef CONFIG_PCI 489 #define CONFIG_CMD_PCI 490 #define CONFIG_CMD_NET 491 #endif 492 493 /* 494 * USB 495 */ 496 #define CONFIG_CMD_USB 497 #define CONFIG_USB_STORAGE 498 #define CONFIG_USB_EHCI 499 #define CONFIG_USB_EHCI_FSL 500 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 501 #define CONFIG_CMD_EXT2 502 503 #define CONFIG_MMC 504 505 #ifdef CONFIG_MMC 506 #define CONFIG_FSL_ESDHC 507 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 508 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 509 #define CONFIG_CMD_MMC 510 #define CONFIG_GENERIC_MMC 511 #define CONFIG_CMD_EXT2 512 #define CONFIG_CMD_FAT 513 #define CONFIG_DOS_PARTITION 514 #endif 515 516 /* 517 * Miscellaneous configurable options 518 */ 519 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 520 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 521 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 522 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 523 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 524 #ifdef CONFIG_CMD_KGDB 525 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 526 #else 527 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 528 #endif 529 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 530 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 531 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 532 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 533 534 /* 535 * For booting Linux, the board info and command line data 536 * have to be in the first 16 MB of memory, since this is 537 * the maximum mapped by the Linux kernel during initialization. 538 */ 539 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 540 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ 541 542 #ifdef CONFIG_CMD_KGDB 543 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 544 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 545 #endif 546 547 /* 548 * Environment Configuration 549 */ 550 #define CONFIG_ROOTPATH /opt/nfsroot 551 #define CONFIG_BOOTFILE uImage 552 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 553 554 /* default location for tftp and bootm */ 555 #define CONFIG_LOADADDR 1000000 556 557 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 558 559 #define CONFIG_BAUDRATE 115200 560 561 #define CONFIG_EXTRA_ENV_SETTINGS \ 562 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 563 "bank_intlv=cs0_cs1\0" \ 564 "netdev=eth0\0" \ 565 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 566 "ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0" \ 567 "tftpflash=tftpboot $loadaddr $uboot && " \ 568 "protect off $ubootaddr +$filesize && " \ 569 "erase $ubootaddr +$filesize && " \ 570 "cp.b $loadaddr $ubootaddr $filesize && " \ 571 "protect on $ubootaddr +$filesize && " \ 572 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 573 "consoledev=ttyS0\0" \ 574 "ramdiskaddr=2000000\0" \ 575 "ramdiskfile=p4080ds/ramdisk.uboot\0" \ 576 "fdtaddr=c00000\0" \ 577 "fdtfile=p4080ds/p4080ds.dtb\0" \ 578 "bdev=sda3\0" \ 579 "c=ffe\0" \ 580 "fman_ucode="MK_STR(CONFIG_SYS_FMAN_FW_ADDR_PHYS)"\0" 581 582 #define CONFIG_HDBOOT \ 583 "setenv bootargs root=/dev/$bdev rw " \ 584 "console=$consoledev,$baudrate $othbootargs;" \ 585 "tftp $loadaddr $bootfile;" \ 586 "tftp $fdtaddr $fdtfile;" \ 587 "bootm $loadaddr - $fdtaddr" 588 589 #define CONFIG_NFSBOOTCOMMAND \ 590 "setenv bootargs root=/dev/nfs rw " \ 591 "nfsroot=$serverip:$rootpath " \ 592 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 593 "console=$consoledev,$baudrate $othbootargs;" \ 594 "tftp $loadaddr $bootfile;" \ 595 "tftp $fdtaddr $fdtfile;" \ 596 "bootm $loadaddr - $fdtaddr" 597 598 #define CONFIG_RAMBOOTCOMMAND \ 599 "setenv bootargs root=/dev/ram rw " \ 600 "console=$consoledev,$baudrate $othbootargs;" \ 601 "tftp $ramdiskaddr $ramdiskfile;" \ 602 "tftp $loadaddr $bootfile;" \ 603 "tftp $fdtaddr $fdtfile;" \ 604 "bootm $loadaddr $ramdiskaddr $fdtaddr" 605 606 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 607 608 #endif /* __CONFIG_H */ 609