1 /* 2 * Copyright 2009-2011 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * Corenet DS style board configuration file 25 */ 26 #ifndef __CONFIG_H 27 #define __CONFIG_H 28 29 #include "../board/freescale/common/ics307_clk.h" 30 31 #ifdef CONFIG_RAMBOOT_PBL 32 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 33 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 34 #endif 35 36 /* High Level Configuration Options */ 37 #define CONFIG_BOOKE 38 #define CONFIG_E500 /* BOOKE e500 family */ 39 #define CONFIG_E500MC /* BOOKE e500mc family */ 40 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 41 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ 42 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 43 #define CONFIG_MP /* support multiple processors */ 44 45 #ifndef CONFIG_SYS_TEXT_BASE 46 #define CONFIG_SYS_TEXT_BASE 0xeff80000 47 #endif 48 49 #ifndef CONFIG_RESET_VECTOR_ADDRESS 50 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 51 #endif 52 53 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 54 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 55 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 56 #define CONFIG_PCI /* Enable PCI/PCIE */ 57 #define CONFIG_PCIE1 /* PCIE controler 1 */ 58 #define CONFIG_PCIE2 /* PCIE controler 2 */ 59 #define CONFIG_PCIE3 /* PCIE controler 3 */ 60 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 61 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 62 63 #define CONFIG_SYS_SRIO 64 #define CONFIG_SRIO1 /* SRIO port 1 */ 65 #define CONFIG_SRIO2 /* SRIO port 2 */ 66 67 #define CONFIG_FSL_LAW /* Use common FSL init code */ 68 69 #define CONFIG_ENV_OVERWRITE 70 71 #ifdef CONFIG_SYS_NO_FLASH 72 #define CONFIG_ENV_IS_NOWHERE 73 #else 74 #define CONFIG_FLASH_CFI_DRIVER 75 #define CONFIG_SYS_FLASH_CFI 76 #endif 77 78 #if defined(CONFIG_SPIFLASH) 79 #define CONFIG_SYS_EXTRA_ENV_RELOC 80 #define CONFIG_ENV_IS_IN_SPI_FLASH 81 #define CONFIG_ENV_SPI_BUS 0 82 #define CONFIG_ENV_SPI_CS 0 83 #define CONFIG_ENV_SPI_MAX_HZ 10000000 84 #define CONFIG_ENV_SPI_MODE 0 85 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 86 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 87 #define CONFIG_ENV_SECT_SIZE 0x10000 88 #elif defined(CONFIG_SDCARD) 89 #define CONFIG_SYS_EXTRA_ENV_RELOC 90 #define CONFIG_ENV_IS_IN_MMC 91 #define CONFIG_SYS_MMC_ENV_DEV 0 92 #define CONFIG_ENV_SIZE 0x2000 93 #define CONFIG_ENV_OFFSET (512 * 1097) 94 #elif defined(CONFIG_NAND) 95 #define CONFIG_SYS_EXTRA_ENV_RELOC 96 #define CONFIG_ENV_IS_IN_NAND 97 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 98 #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 99 #else 100 #define CONFIG_ENV_IS_IN_FLASH 101 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 102 #define CONFIG_ENV_SIZE 0x2000 103 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 104 #endif 105 106 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 107 108 /* 109 * These can be toggled for performance analysis, otherwise use default. 110 */ 111 #define CONFIG_SYS_CACHE_STASHING 112 #define CONFIG_BACKSIDE_L2_CACHE 113 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 114 #define CONFIG_BTB /* toggle branch predition */ 115 #define CONFIG_DDR_ECC 116 #ifdef CONFIG_DDR_ECC 117 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 118 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 119 #endif 120 121 #define CONFIG_ENABLE_36BIT_PHYS 122 123 #ifdef CONFIG_PHYS_64BIT 124 #define CONFIG_ADDR_MAP 125 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 126 #endif 127 128 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 129 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 130 #define CONFIG_SYS_MEMTEST_END 0x00400000 131 #define CONFIG_SYS_ALT_MEMTEST 132 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 133 134 /* 135 * Config the L3 Cache as L3 SRAM 136 */ 137 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 138 #ifdef CONFIG_PHYS_64BIT 139 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) 140 #else 141 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 142 #endif 143 #define CONFIG_SYS_L3_SIZE (1024 << 10) 144 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 145 146 /* 147 * Base addresses -- Note these are effective addresses where the 148 * actual resources get mapped (not physical addresses) 149 */ 150 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 /* CCSRBAR Default */ 151 #define CONFIG_SYS_CCSRBAR 0xfe000000 /* relocated CCSRBAR */ 152 #ifdef CONFIG_PHYS_64BIT 153 #define CONFIG_SYS_CCSRBAR_PHYS 0xffe000000ull /* physical addr of CCSRBAR */ 154 #else 155 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ 156 #endif 157 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 158 159 #ifdef CONFIG_PHYS_64BIT 160 #define CONFIG_SYS_DCSRBAR 0xf0000000 161 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 162 #endif 163 164 /* EEPROM */ 165 #define CONFIG_ID_EEPROM 166 #define CONFIG_SYS_I2C_EEPROM_NXID 167 #define CONFIG_SYS_EEPROM_BUS_NUM 0 168 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 169 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 170 171 /* 172 * DDR Setup 173 */ 174 #define CONFIG_VERY_BIG_RAM 175 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 176 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 177 178 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 179 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 180 181 #define CONFIG_DDR_SPD 182 #define CONFIG_FSL_DDR3 183 184 #define CONFIG_SYS_SPD_BUS_NUM 1 185 #define SPD_EEPROM_ADDRESS1 0x51 186 #define SPD_EEPROM_ADDRESS2 0x52 187 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 188 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 189 190 /* 191 * Local Bus Definitions 192 */ 193 194 /* Set the local bus clock 1/8 of platform clock */ 195 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 196 197 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */ 198 #ifdef CONFIG_PHYS_64BIT 199 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 200 #else 201 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 202 #endif 203 204 #define CONFIG_SYS_FLASH_BR_PRELIM \ 205 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \ 206 | BR_PS_16 | BR_V) 207 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 208 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 209 210 #define CONFIG_SYS_BR1_PRELIM \ 211 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 212 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 213 214 #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ 215 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 216 #ifdef CONFIG_PHYS_64BIT 217 #define PIXIS_BASE_PHYS 0xfffdf0000ull 218 #else 219 #define PIXIS_BASE_PHYS PIXIS_BASE 220 #endif 221 222 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 223 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 224 225 #define PIXIS_LBMAP_SWITCH 7 226 #define PIXIS_LBMAP_MASK 0xf0 227 #define PIXIS_LBMAP_SHIFT 4 228 #define PIXIS_LBMAP_ALTBANK 0x40 229 230 #define CONFIG_SYS_FLASH_QUIET_TEST 231 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 232 233 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 234 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 235 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 236 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 237 238 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 239 240 #if defined(CONFIG_RAMBOOT_PBL) 241 #define CONFIG_SYS_RAMBOOT 242 #endif 243 244 /* Nand Flash */ 245 #if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) 246 #define CONFIG_NAND_FSL_ELBC 247 #ifdef CONFIG_NAND_FSL_ELBC 248 #define CONFIG_SYS_NAND_BASE 0xffa00000 249 #ifdef CONFIG_PHYS_64BIT 250 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 251 #else 252 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 253 #endif 254 255 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 256 #define CONFIG_SYS_MAX_NAND_DEVICE 1 257 #define CONFIG_MTD_NAND_VERIFY_WRITE 258 #define CONFIG_CMD_NAND 259 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 260 261 /* NAND flash config */ 262 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 263 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 264 | BR_PS_8 /* Port Size = 8 bit */ \ 265 | BR_MS_FCM /* MSEL = FCM */ \ 266 | BR_V) /* valid */ 267 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 268 | OR_FCM_PGS /* Large Page*/ \ 269 | OR_FCM_CSCT \ 270 | OR_FCM_CST \ 271 | OR_FCM_CHT \ 272 | OR_FCM_SCY_1 \ 273 | OR_FCM_TRLX \ 274 | OR_FCM_EHTR) 275 276 #ifdef CONFIG_NAND 277 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 278 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 279 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 280 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 281 #else 282 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 283 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 284 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 285 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 286 #endif 287 #endif /* CONFIG_NAND_FSL_ELBC */ 288 #else 289 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 290 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 291 #endif 292 293 #define CONFIG_SYS_FLASH_EMPTY_INFO 294 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 295 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 296 297 #define CONFIG_BOARD_EARLY_INIT_F 298 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 299 #define CONFIG_MISC_INIT_R 300 301 #define CONFIG_HWCONFIG 302 303 /* define to use L1 as initial stack */ 304 #define CONFIG_L1_INIT_RAM 305 #define CONFIG_SYS_INIT_RAM_LOCK 306 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 307 #ifdef CONFIG_PHYS_64BIT 308 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 309 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 310 /* The assembler doesn't like typecast */ 311 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 312 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 313 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 314 #else 315 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ 316 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 317 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 318 #endif 319 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 320 321 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 322 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 323 324 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 325 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 326 327 /* Serial Port - controlled on board with jumper J8 328 * open - index 2 329 * shorted - index 1 330 */ 331 #define CONFIG_CONS_INDEX 1 332 #define CONFIG_SYS_NS16550 333 #define CONFIG_SYS_NS16550_SERIAL 334 #define CONFIG_SYS_NS16550_REG_SIZE 1 335 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 336 337 #define CONFIG_SYS_BAUDRATE_TABLE \ 338 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 339 340 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 341 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 342 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 343 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 344 345 /* Use the HUSH parser */ 346 #define CONFIG_SYS_HUSH_PARSER 347 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 348 349 /* pass open firmware flat tree */ 350 #define CONFIG_OF_LIBFDT 351 #define CONFIG_OF_BOARD_SETUP 352 #define CONFIG_OF_STDOUT_VIA_ALIAS 353 354 /* new uImage format support */ 355 #define CONFIG_FIT 356 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 357 358 /* I2C */ 359 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 360 #define CONFIG_HARD_I2C /* I2C with hardware support */ 361 #define CONFIG_I2C_MULTI_BUS 362 #define CONFIG_I2C_CMD_TREE 363 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 364 #define CONFIG_SYS_I2C_SLAVE 0x7F 365 #define CONFIG_SYS_I2C_OFFSET 0x118000 366 #define CONFIG_SYS_I2C2_OFFSET 0x118100 367 368 /* 369 * RapidIO 370 */ 371 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 372 #ifdef CONFIG_PHYS_64BIT 373 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 374 #else 375 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 376 #endif 377 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 378 379 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 380 #ifdef CONFIG_PHYS_64BIT 381 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 382 #else 383 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 384 #endif 385 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 386 387 /* 388 * eSPI - Enhanced SPI 389 */ 390 #define CONFIG_FSL_ESPI 391 #define CONFIG_SPI_FLASH 392 #define CONFIG_SPI_FLASH_SPANSION 393 #define CONFIG_CMD_SF 394 #define CONFIG_SF_DEFAULT_SPEED 10000000 395 #define CONFIG_SF_DEFAULT_MODE 0 396 397 /* 398 * General PCI 399 * Memory space is mapped 1-1, but I/O space must start from 0. 400 */ 401 402 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 403 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 404 #ifdef CONFIG_PHYS_64BIT 405 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 406 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 407 #else 408 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 409 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 410 #endif 411 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 412 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 413 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 414 #ifdef CONFIG_PHYS_64BIT 415 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 416 #else 417 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 418 #endif 419 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 420 421 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 422 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 423 #ifdef CONFIG_PHYS_64BIT 424 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 425 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 426 #else 427 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 428 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 429 #endif 430 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 431 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 432 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 433 #ifdef CONFIG_PHYS_64BIT 434 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 435 #else 436 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 437 #endif 438 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 439 440 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 441 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 442 #ifdef CONFIG_PHYS_64BIT 443 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 444 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 445 #else 446 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 447 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 448 #endif 449 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 450 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 451 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 452 #ifdef CONFIG_PHYS_64BIT 453 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 454 #else 455 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 456 #endif 457 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 458 459 /* controller 4, Base address 203000 */ 460 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 461 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 462 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 463 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 464 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 465 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 466 467 /* Qman/Bman */ 468 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 469 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 470 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 471 #ifdef CONFIG_PHYS_64BIT 472 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 473 #else 474 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 475 #endif 476 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 477 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 478 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 479 #ifdef CONFIG_PHYS_64BIT 480 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 481 #else 482 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 483 #endif 484 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 485 486 #define CONFIG_SYS_DPAA_FMAN 487 #define CONFIG_SYS_DPAA_PME 488 /* Default address of microcode for the Linux Fman driver */ 489 #define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000 490 #ifdef CONFIG_PHYS_64BIT 491 #define CONFIG_SYS_FMAN_FW_ADDR_PHYS 0xFEF000000ULL 492 #else 493 #define CONFIG_SYS_FMAN_FW_ADDR_PHYS CONFIG_SYS_FMAN_FW_ADDR 494 #endif 495 496 #ifdef CONFIG_SYS_DPAA_FMAN 497 #define CONFIG_FMAN_ENET 498 #endif 499 500 #ifdef CONFIG_PCI 501 #define CONFIG_NET_MULTI 502 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 503 #define CONFIG_E1000 504 505 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 506 #define CONFIG_DOS_PARTITION 507 #endif /* CONFIG_PCI */ 508 509 /* SATA */ 510 #ifdef CONFIG_FSL_SATA_V2 511 #define CONFIG_LIBATA 512 #define CONFIG_FSL_SATA 513 514 #define CONFIG_SYS_SATA_MAX_DEVICE 2 515 #define CONFIG_SATA1 516 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 517 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 518 #define CONFIG_SATA2 519 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 520 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 521 522 #define CONFIG_LBA48 523 #define CONFIG_CMD_SATA 524 #define CONFIG_DOS_PARTITION 525 #define CONFIG_CMD_EXT2 526 #endif 527 528 #ifdef CONFIG_FMAN_ENET 529 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c 530 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d 531 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e 532 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f 533 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 534 535 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c 536 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d 537 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e 538 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f 539 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0 540 541 #define CONFIG_SYS_TBIPA_VALUE 8 542 #define CONFIG_MII /* MII PHY management */ 543 #define CONFIG_ETHPRIME "FM1@DTSEC1" 544 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 545 #endif 546 547 /* 548 * Environment 549 */ 550 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 551 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 552 553 /* 554 * Command line configuration. 555 */ 556 #include <config_cmd_default.h> 557 558 #define CONFIG_CMD_DHCP 559 #define CONFIG_CMD_ELF 560 #define CONFIG_CMD_ERRATA 561 #define CONFIG_CMD_GREPENV 562 #define CONFIG_CMD_IRQ 563 #define CONFIG_CMD_I2C 564 #define CONFIG_CMD_MII 565 #define CONFIG_CMD_PING 566 #define CONFIG_CMD_SETEXPR 567 568 #ifdef CONFIG_PCI 569 #define CONFIG_CMD_PCI 570 #define CONFIG_CMD_NET 571 #endif 572 573 /* 574 * USB 575 */ 576 #define CONFIG_CMD_USB 577 #define CONFIG_USB_STORAGE 578 #define CONFIG_USB_EHCI 579 #define CONFIG_USB_EHCI_FSL 580 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 581 #define CONFIG_CMD_EXT2 582 583 #define CONFIG_MMC 584 585 #ifdef CONFIG_MMC 586 #define CONFIG_FSL_ESDHC 587 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 588 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 589 #define CONFIG_CMD_MMC 590 #define CONFIG_GENERIC_MMC 591 #define CONFIG_CMD_EXT2 592 #define CONFIG_CMD_FAT 593 #define CONFIG_DOS_PARTITION 594 #endif 595 596 /* 597 * Miscellaneous configurable options 598 */ 599 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 600 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 601 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 602 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 603 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 604 #ifdef CONFIG_CMD_KGDB 605 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 606 #else 607 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 608 #endif 609 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 610 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 611 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 612 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 613 614 /* 615 * For booting Linux, the board info and command line data 616 * have to be in the first 64 MB of memory, since this is 617 * the maximum mapped by the Linux kernel during initialization. 618 */ 619 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 620 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 621 622 #ifdef CONFIG_CMD_KGDB 623 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 624 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 625 #endif 626 627 /* 628 * Environment Configuration 629 */ 630 #define CONFIG_ROOTPATH /opt/nfsroot 631 #define CONFIG_BOOTFILE uImage 632 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 633 634 /* default location for tftp and bootm */ 635 #define CONFIG_LOADADDR 1000000 636 637 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 638 639 #define CONFIG_BAUDRATE 115200 640 641 #define CONFIG_EXTRA_ENV_SETTINGS \ 642 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 643 "bank_intlv=cs0_cs1\0" \ 644 "netdev=eth0\0" \ 645 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 646 "ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0" \ 647 "tftpflash=tftpboot $loadaddr $uboot && " \ 648 "protect off $ubootaddr +$filesize && " \ 649 "erase $ubootaddr +$filesize && " \ 650 "cp.b $loadaddr $ubootaddr $filesize && " \ 651 "protect on $ubootaddr +$filesize && " \ 652 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 653 "consoledev=ttyS0\0" \ 654 "ramdiskaddr=2000000\0" \ 655 "ramdiskfile=p4080ds/ramdisk.uboot\0" \ 656 "fdtaddr=c00000\0" \ 657 "fdtfile=p4080ds/p4080ds.dtb\0" \ 658 "bdev=sda3\0" \ 659 "c=ffe\0" \ 660 "fman_ucode="MK_STR(CONFIG_SYS_FMAN_FW_ADDR_PHYS)"\0" 661 662 #define CONFIG_HDBOOT \ 663 "setenv bootargs root=/dev/$bdev rw " \ 664 "console=$consoledev,$baudrate $othbootargs;" \ 665 "tftp $loadaddr $bootfile;" \ 666 "tftp $fdtaddr $fdtfile;" \ 667 "bootm $loadaddr - $fdtaddr" 668 669 #define CONFIG_NFSBOOTCOMMAND \ 670 "setenv bootargs root=/dev/nfs rw " \ 671 "nfsroot=$serverip:$rootpath " \ 672 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 673 "console=$consoledev,$baudrate $othbootargs;" \ 674 "tftp $loadaddr $bootfile;" \ 675 "tftp $fdtaddr $fdtfile;" \ 676 "bootm $loadaddr - $fdtaddr" 677 678 #define CONFIG_RAMBOOTCOMMAND \ 679 "setenv bootargs root=/dev/ram rw " \ 680 "console=$consoledev,$baudrate $othbootargs;" \ 681 "tftp $ramdiskaddr $ramdiskfile;" \ 682 "tftp $loadaddr $bootfile;" \ 683 "tftp $fdtaddr $fdtfile;" \ 684 "bootm $loadaddr $ramdiskaddr $fdtaddr" 685 686 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 687 688 #endif /* __CONFIG_H */ 689