1 /* 2 * Copyright 2009-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * Corenet DS style board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_SYS_GENERIC_BOARD 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 #include "../board/freescale/common/ics307_clk.h" 17 18 #ifdef CONFIG_RAMBOOT_PBL 19 #ifdef CONFIG_SECURE_BOOT 20 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 21 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 22 #ifdef CONFIG_NAND 23 #define CONFIG_RAMBOOT_NAND 24 #endif 25 #define CONFIG_BOOTSCRIPT_COPY_RAM 26 #else 27 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 28 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 29 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg 30 #if defined(CONFIG_P3041DS) 31 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg 32 #elif defined(CONFIG_P4080DS) 33 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg 34 #elif defined(CONFIG_P5020DS) 35 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg 36 #elif defined(CONFIG_P5040DS) 37 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg 38 #endif 39 #endif 40 #endif 41 42 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 43 /* Set 1M boot space */ 44 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 45 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 46 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 47 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 48 #define CONFIG_SYS_NO_FLASH 49 #endif 50 51 /* High Level Configuration Options */ 52 #define CONFIG_BOOKE 53 #define CONFIG_E500 /* BOOKE e500 family */ 54 #define CONFIG_E500MC /* BOOKE e500mc family */ 55 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 56 #define CONFIG_MP /* support multiple processors */ 57 58 #ifndef CONFIG_SYS_TEXT_BASE 59 #define CONFIG_SYS_TEXT_BASE 0xeff40000 60 #endif 61 62 #ifndef CONFIG_RESET_VECTOR_ADDRESS 63 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 64 #endif 65 66 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 67 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 68 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 69 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 70 #define CONFIG_PCI /* Enable PCI/PCIE */ 71 #define CONFIG_PCIE1 /* PCIE controler 1 */ 72 #define CONFIG_PCIE2 /* PCIE controler 2 */ 73 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 74 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 75 76 #define CONFIG_FSL_LAW /* Use common FSL init code */ 77 78 #define CONFIG_ENV_OVERWRITE 79 80 #ifdef CONFIG_SYS_NO_FLASH 81 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) 82 #define CONFIG_ENV_IS_NOWHERE 83 #endif 84 #else 85 #define CONFIG_FLASH_CFI_DRIVER 86 #define CONFIG_SYS_FLASH_CFI 87 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 88 #endif 89 90 #if defined(CONFIG_SPIFLASH) 91 #define CONFIG_SYS_EXTRA_ENV_RELOC 92 #define CONFIG_ENV_IS_IN_SPI_FLASH 93 #define CONFIG_ENV_SPI_BUS 0 94 #define CONFIG_ENV_SPI_CS 0 95 #define CONFIG_ENV_SPI_MAX_HZ 10000000 96 #define CONFIG_ENV_SPI_MODE 0 97 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 98 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 99 #define CONFIG_ENV_SECT_SIZE 0x10000 100 #elif defined(CONFIG_SDCARD) 101 #define CONFIG_SYS_EXTRA_ENV_RELOC 102 #define CONFIG_ENV_IS_IN_MMC 103 #define CONFIG_FSL_FIXED_MMC_LOCATION 104 #define CONFIG_SYS_MMC_ENV_DEV 0 105 #define CONFIG_ENV_SIZE 0x2000 106 #define CONFIG_ENV_OFFSET (512 * 1658) 107 #elif defined(CONFIG_NAND) 108 #define CONFIG_SYS_EXTRA_ENV_RELOC 109 #define CONFIG_ENV_IS_IN_NAND 110 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 111 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 112 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 113 #define CONFIG_ENV_IS_IN_REMOTE 114 #define CONFIG_ENV_ADDR 0xffe20000 115 #define CONFIG_ENV_SIZE 0x2000 116 #elif defined(CONFIG_ENV_IS_NOWHERE) 117 #define CONFIG_ENV_SIZE 0x2000 118 #else 119 #define CONFIG_ENV_IS_IN_FLASH 120 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 121 #define CONFIG_ENV_SIZE 0x2000 122 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 123 #endif 124 125 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 126 127 /* 128 * These can be toggled for performance analysis, otherwise use default. 129 */ 130 #define CONFIG_SYS_CACHE_STASHING 131 #define CONFIG_BACKSIDE_L2_CACHE 132 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 133 #define CONFIG_BTB /* toggle branch predition */ 134 #define CONFIG_DDR_ECC 135 #ifdef CONFIG_DDR_ECC 136 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 137 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 138 #endif 139 140 #define CONFIG_ENABLE_36BIT_PHYS 141 142 #ifdef CONFIG_PHYS_64BIT 143 #define CONFIG_ADDR_MAP 144 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 145 #endif 146 147 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 148 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 149 #define CONFIG_SYS_MEMTEST_END 0x00400000 150 #define CONFIG_SYS_ALT_MEMTEST 151 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 152 153 /* 154 * Config the L3 Cache as L3 SRAM 155 */ 156 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 157 #ifdef CONFIG_PHYS_64BIT 158 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) 159 #else 160 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 161 #endif 162 #define CONFIG_SYS_L3_SIZE (1024 << 10) 163 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 164 165 #ifdef CONFIG_PHYS_64BIT 166 #define CONFIG_SYS_DCSRBAR 0xf0000000 167 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 168 #endif 169 170 /* EEPROM */ 171 #define CONFIG_ID_EEPROM 172 #define CONFIG_SYS_I2C_EEPROM_NXID 173 #define CONFIG_SYS_EEPROM_BUS_NUM 0 174 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 175 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 176 177 /* 178 * DDR Setup 179 */ 180 #define CONFIG_VERY_BIG_RAM 181 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 182 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 183 184 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 185 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 186 187 #define CONFIG_DDR_SPD 188 #define CONFIG_SYS_FSL_DDR3 189 190 #define CONFIG_SYS_SPD_BUS_NUM 1 191 #define SPD_EEPROM_ADDRESS1 0x51 192 #define SPD_EEPROM_ADDRESS2 0x52 193 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 194 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 195 196 /* 197 * Local Bus Definitions 198 */ 199 200 /* Set the local bus clock 1/8 of platform clock */ 201 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 202 203 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */ 204 #ifdef CONFIG_PHYS_64BIT 205 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 206 #else 207 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 208 #endif 209 210 #define CONFIG_SYS_FLASH_BR_PRELIM \ 211 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \ 212 | BR_PS_16 | BR_V) 213 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 214 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 215 216 #define CONFIG_SYS_BR1_PRELIM \ 217 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 218 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 219 220 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 221 #ifdef CONFIG_PHYS_64BIT 222 #define PIXIS_BASE_PHYS 0xfffdf0000ull 223 #else 224 #define PIXIS_BASE_PHYS PIXIS_BASE 225 #endif 226 227 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 228 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 229 230 #define PIXIS_LBMAP_SWITCH 7 231 #define PIXIS_LBMAP_MASK 0xf0 232 #define PIXIS_LBMAP_SHIFT 4 233 #define PIXIS_LBMAP_ALTBANK 0x40 234 235 #define CONFIG_SYS_FLASH_QUIET_TEST 236 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 237 238 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 239 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 240 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 241 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 242 243 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 244 245 #if defined(CONFIG_RAMBOOT_PBL) 246 #define CONFIG_SYS_RAMBOOT 247 #endif 248 249 /* Nand Flash */ 250 #ifdef CONFIG_NAND_FSL_ELBC 251 #define CONFIG_SYS_NAND_BASE 0xffa00000 252 #ifdef CONFIG_PHYS_64BIT 253 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 254 #else 255 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 256 #endif 257 258 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 259 #define CONFIG_SYS_MAX_NAND_DEVICE 1 260 #define CONFIG_CMD_NAND 261 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 262 263 /* NAND flash config */ 264 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 265 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 266 | BR_PS_8 /* Port Size = 8 bit */ \ 267 | BR_MS_FCM /* MSEL = FCM */ \ 268 | BR_V) /* valid */ 269 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 270 | OR_FCM_PGS /* Large Page*/ \ 271 | OR_FCM_CSCT \ 272 | OR_FCM_CST \ 273 | OR_FCM_CHT \ 274 | OR_FCM_SCY_1 \ 275 | OR_FCM_TRLX \ 276 | OR_FCM_EHTR) 277 278 #ifdef CONFIG_NAND 279 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 280 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 281 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 282 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 283 #else 284 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 285 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 286 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 287 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 288 #endif 289 #else 290 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 291 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 292 #endif /* CONFIG_NAND_FSL_ELBC */ 293 294 #define CONFIG_SYS_FLASH_EMPTY_INFO 295 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 296 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 297 298 #define CONFIG_BOARD_EARLY_INIT_F 299 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 300 #define CONFIG_MISC_INIT_R 301 302 #define CONFIG_HWCONFIG 303 304 /* define to use L1 as initial stack */ 305 #define CONFIG_L1_INIT_RAM 306 #define CONFIG_SYS_INIT_RAM_LOCK 307 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 308 #ifdef CONFIG_PHYS_64BIT 309 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 310 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 311 /* The assembler doesn't like typecast */ 312 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 313 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 314 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 315 #else 316 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ 317 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 318 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 319 #endif 320 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 321 322 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 323 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 324 325 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 326 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 327 328 /* Serial Port - controlled on board with jumper J8 329 * open - index 2 330 * shorted - index 1 331 */ 332 #define CONFIG_CONS_INDEX 1 333 #define CONFIG_SYS_NS16550 334 #define CONFIG_SYS_NS16550_SERIAL 335 #define CONFIG_SYS_NS16550_REG_SIZE 1 336 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 337 338 #define CONFIG_SYS_BAUDRATE_TABLE \ 339 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 340 341 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 342 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 343 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 344 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 345 346 /* Use the HUSH parser */ 347 #define CONFIG_SYS_HUSH_PARSER 348 349 /* pass open firmware flat tree */ 350 #define CONFIG_OF_LIBFDT 351 #define CONFIG_OF_BOARD_SETUP 352 #define CONFIG_OF_STDOUT_VIA_ALIAS 353 354 /* new uImage format support */ 355 #define CONFIG_FIT 356 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 357 358 /* I2C */ 359 #define CONFIG_SYS_I2C 360 #define CONFIG_SYS_I2C_FSL 361 #define CONFIG_SYS_FSL_I2C_SPEED 400000 362 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 363 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 364 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 365 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 366 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 367 368 /* 369 * RapidIO 370 */ 371 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 372 #ifdef CONFIG_PHYS_64BIT 373 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 374 #else 375 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 376 #endif 377 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 378 379 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 380 #ifdef CONFIG_PHYS_64BIT 381 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 382 #else 383 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 384 #endif 385 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 386 387 /* 388 * for slave u-boot IMAGE instored in master memory space, 389 * PHYS must be aligned based on the SIZE 390 */ 391 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 392 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 393 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 394 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 395 /* 396 * for slave UCODE and ENV instored in master memory space, 397 * PHYS must be aligned based on the SIZE 398 */ 399 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 400 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 401 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 402 403 /* slave core release by master*/ 404 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 405 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 406 407 /* 408 * SRIO_PCIE_BOOT - SLAVE 409 */ 410 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 411 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 412 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 413 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 414 #endif 415 416 /* 417 * eSPI - Enhanced SPI 418 */ 419 #define CONFIG_FSL_ESPI 420 #define CONFIG_SPI_FLASH_SPANSION 421 #define CONFIG_CMD_SF 422 #define CONFIG_SF_DEFAULT_SPEED 10000000 423 #define CONFIG_SF_DEFAULT_MODE 0 424 425 /* 426 * General PCI 427 * Memory space is mapped 1-1, but I/O space must start from 0. 428 */ 429 430 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 431 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 432 #ifdef CONFIG_PHYS_64BIT 433 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 434 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 435 #else 436 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 437 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 438 #endif 439 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 440 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 441 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 442 #ifdef CONFIG_PHYS_64BIT 443 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 444 #else 445 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 446 #endif 447 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 448 449 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 450 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 451 #ifdef CONFIG_PHYS_64BIT 452 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 453 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 454 #else 455 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 456 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 457 #endif 458 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 459 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 460 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 461 #ifdef CONFIG_PHYS_64BIT 462 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 463 #else 464 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 465 #endif 466 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 467 468 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 469 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 470 #ifdef CONFIG_PHYS_64BIT 471 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 472 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 473 #else 474 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 475 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 476 #endif 477 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 478 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 479 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 480 #ifdef CONFIG_PHYS_64BIT 481 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 482 #else 483 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 484 #endif 485 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 486 487 /* controller 4, Base address 203000 */ 488 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 489 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 490 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 491 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 492 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 493 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 494 495 /* Qman/Bman */ 496 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 497 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 498 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 499 #ifdef CONFIG_PHYS_64BIT 500 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 501 #else 502 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 503 #endif 504 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 505 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 506 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 507 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 508 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 509 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 510 CONFIG_SYS_BMAN_CENA_SIZE) 511 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 512 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 513 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 514 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 515 #ifdef CONFIG_PHYS_64BIT 516 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 517 #else 518 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 519 #endif 520 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 521 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 522 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 523 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 524 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 525 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 526 CONFIG_SYS_QMAN_CENA_SIZE) 527 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 528 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 529 530 #define CONFIG_SYS_DPAA_FMAN 531 #define CONFIG_SYS_DPAA_PME 532 /* Default address of microcode for the Linux Fman driver */ 533 #if defined(CONFIG_SPIFLASH) 534 /* 535 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 536 * env, so we got 0x110000. 537 */ 538 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 539 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 540 #elif defined(CONFIG_SDCARD) 541 /* 542 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 543 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 544 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 545 */ 546 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 547 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 548 #elif defined(CONFIG_NAND) 549 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 550 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 551 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 552 /* 553 * Slave has no ucode locally, it can fetch this from remote. When implementing 554 * in two corenet boards, slave's ucode could be stored in master's memory 555 * space, the address can be mapped from slave TLB->slave LAW-> 556 * slave SRIO or PCIE outbound window->master inbound window-> 557 * master LAW->the ucode address in master's memory space. 558 */ 559 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 560 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 561 #else 562 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 563 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 564 #endif 565 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 566 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 567 568 #ifdef CONFIG_SYS_DPAA_FMAN 569 #define CONFIG_FMAN_ENET 570 #define CONFIG_PHYLIB_10G 571 #define CONFIG_PHY_VITESSE 572 #define CONFIG_PHY_TERANETICS 573 #endif 574 575 #ifdef CONFIG_PCI 576 #define CONFIG_PCI_INDIRECT_BRIDGE 577 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 578 #define CONFIG_E1000 579 580 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 581 #define CONFIG_DOS_PARTITION 582 #endif /* CONFIG_PCI */ 583 584 /* SATA */ 585 #ifdef CONFIG_FSL_SATA_V2 586 #define CONFIG_LIBATA 587 #define CONFIG_FSL_SATA 588 589 #define CONFIG_SYS_SATA_MAX_DEVICE 2 590 #define CONFIG_SATA1 591 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 592 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 593 #define CONFIG_SATA2 594 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 595 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 596 597 #define CONFIG_LBA48 598 #define CONFIG_CMD_SATA 599 #define CONFIG_DOS_PARTITION 600 #define CONFIG_CMD_EXT2 601 #endif 602 603 #ifdef CONFIG_FMAN_ENET 604 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c 605 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d 606 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e 607 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f 608 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 609 610 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c 611 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d 612 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e 613 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f 614 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0 615 616 #define CONFIG_SYS_TBIPA_VALUE 8 617 #define CONFIG_MII /* MII PHY management */ 618 #define CONFIG_ETHPRIME "FM1@DTSEC1" 619 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 620 #endif 621 622 /* 623 * Environment 624 */ 625 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 626 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 627 628 /* 629 * Command line configuration. 630 */ 631 #define CONFIG_CMD_DHCP 632 #define CONFIG_CMD_ELF 633 #define CONFIG_CMD_ERRATA 634 #define CONFIG_CMD_GREPENV 635 #define CONFIG_CMD_IRQ 636 #define CONFIG_CMD_I2C 637 #define CONFIG_CMD_MII 638 #define CONFIG_CMD_PING 639 #define CONFIG_CMD_REGINFO 640 641 #ifdef CONFIG_PCI 642 #define CONFIG_CMD_PCI 643 #endif 644 645 /* 646 * USB 647 */ 648 #define CONFIG_HAS_FSL_DR_USB 649 #define CONFIG_HAS_FSL_MPH_USB 650 651 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 652 #define CONFIG_CMD_USB 653 #define CONFIG_USB_STORAGE 654 #define CONFIG_USB_EHCI 655 #define CONFIG_USB_EHCI_FSL 656 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 657 #define CONFIG_CMD_EXT2 658 #endif 659 660 #ifdef CONFIG_MMC 661 #define CONFIG_FSL_ESDHC 662 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 663 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 664 #define CONFIG_CMD_MMC 665 #define CONFIG_GENERIC_MMC 666 #define CONFIG_CMD_EXT2 667 #define CONFIG_CMD_FAT 668 #define CONFIG_DOS_PARTITION 669 #endif 670 671 /* Hash command with SHA acceleration supported in hardware */ 672 #ifdef CONFIG_FSL_CAAM 673 #define CONFIG_CMD_HASH 674 #define CONFIG_SHA_HW_ACCEL 675 #endif 676 677 /* 678 * Miscellaneous configurable options 679 */ 680 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 681 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 682 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 683 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 684 #ifdef CONFIG_CMD_KGDB 685 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 686 #else 687 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 688 #endif 689 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 690 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 691 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 692 693 /* 694 * For booting Linux, the board info and command line data 695 * have to be in the first 64 MB of memory, since this is 696 * the maximum mapped by the Linux kernel during initialization. 697 */ 698 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 699 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 700 701 #ifdef CONFIG_CMD_KGDB 702 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 703 #endif 704 705 /* 706 * Environment Configuration 707 */ 708 #define CONFIG_ROOTPATH "/opt/nfsroot" 709 #define CONFIG_BOOTFILE "uImage" 710 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 711 712 /* default location for tftp and bootm */ 713 #define CONFIG_LOADADDR 1000000 714 715 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 716 717 #define CONFIG_BAUDRATE 115200 718 719 #ifdef CONFIG_P4080DS 720 #define __USB_PHY_TYPE ulpi 721 #else 722 #define __USB_PHY_TYPE utmi 723 #endif 724 725 #define CONFIG_EXTRA_ENV_SETTINGS \ 726 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 727 "bank_intlv=cs0_cs1;" \ 728 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 729 "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 730 "netdev=eth0\0" \ 731 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 732 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 733 "tftpflash=tftpboot $loadaddr $uboot && " \ 734 "protect off $ubootaddr +$filesize && " \ 735 "erase $ubootaddr +$filesize && " \ 736 "cp.b $loadaddr $ubootaddr $filesize && " \ 737 "protect on $ubootaddr +$filesize && " \ 738 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 739 "consoledev=ttyS0\0" \ 740 "ramdiskaddr=2000000\0" \ 741 "ramdiskfile=p4080ds/ramdisk.uboot\0" \ 742 "fdtaddr=c00000\0" \ 743 "fdtfile=p4080ds/p4080ds.dtb\0" \ 744 "bdev=sda3\0" 745 746 #define CONFIG_HDBOOT \ 747 "setenv bootargs root=/dev/$bdev rw " \ 748 "console=$consoledev,$baudrate $othbootargs;" \ 749 "tftp $loadaddr $bootfile;" \ 750 "tftp $fdtaddr $fdtfile;" \ 751 "bootm $loadaddr - $fdtaddr" 752 753 #define CONFIG_NFSBOOTCOMMAND \ 754 "setenv bootargs root=/dev/nfs rw " \ 755 "nfsroot=$serverip:$rootpath " \ 756 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 757 "console=$consoledev,$baudrate $othbootargs;" \ 758 "tftp $loadaddr $bootfile;" \ 759 "tftp $fdtaddr $fdtfile;" \ 760 "bootm $loadaddr - $fdtaddr" 761 762 #define CONFIG_RAMBOOTCOMMAND \ 763 "setenv bootargs root=/dev/ram rw " \ 764 "console=$consoledev,$baudrate $othbootargs;" \ 765 "tftp $ramdiskaddr $ramdiskfile;" \ 766 "tftp $loadaddr $bootfile;" \ 767 "tftp $fdtaddr $fdtfile;" \ 768 "bootm $loadaddr $ramdiskaddr $fdtaddr" 769 770 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 771 772 #include <asm/fsl_secure_boot.h> 773 774 #ifdef CONFIG_SECURE_BOOT 775 #define CONFIG_CMD_BLOB 776 #endif 777 778 #endif /* __CONFIG_H */ 779