1 /* 2 * Copyright 2009-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * Corenet DS style board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #include "../board/freescale/common/ics307_clk.h" 14 15 #ifdef CONFIG_RAMBOOT_PBL 16 #ifdef CONFIG_SECURE_BOOT 17 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 18 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 19 #ifdef CONFIG_NAND 20 #define CONFIG_RAMBOOT_NAND 21 #endif 22 #define CONFIG_BOOTSCRIPT_COPY_RAM 23 #else 24 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 25 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 26 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg 27 #if defined(CONFIG_TARGET_P3041DS) 28 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg 29 #elif defined(CONFIG_TARGET_P4080DS) 30 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg 31 #elif defined(CONFIG_TARGET_P5020DS) 32 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg 33 #elif defined(CONFIG_TARGET_P5040DS) 34 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg 35 #endif 36 #endif 37 #endif 38 39 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 40 /* Set 1M boot space */ 41 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 42 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 43 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 44 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 45 #endif 46 47 /* High Level Configuration Options */ 48 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 49 #define CONFIG_MP /* support multiple processors */ 50 51 #ifndef CONFIG_SYS_TEXT_BASE 52 #define CONFIG_SYS_TEXT_BASE 0xeff40000 53 #endif 54 55 #ifndef CONFIG_RESET_VECTOR_ADDRESS 56 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 57 #endif 58 59 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 60 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 61 #define CONFIG_PCIE1 /* PCIE controller 1 */ 62 #define CONFIG_PCIE2 /* PCIE controller 2 */ 63 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 64 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 65 66 #define CONFIG_ENV_OVERWRITE 67 68 #ifndef CONFIG_MTD_NOR_FLASH 69 #else 70 #define CONFIG_FLASH_CFI_DRIVER 71 #define CONFIG_SYS_FLASH_CFI 72 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 73 #endif 74 75 #if defined(CONFIG_SPIFLASH) 76 #define CONFIG_SYS_EXTRA_ENV_RELOC 77 #define CONFIG_ENV_IS_IN_SPI_FLASH 78 #define CONFIG_ENV_SPI_BUS 0 79 #define CONFIG_ENV_SPI_CS 0 80 #define CONFIG_ENV_SPI_MAX_HZ 10000000 81 #define CONFIG_ENV_SPI_MODE 0 82 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 83 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 84 #define CONFIG_ENV_SECT_SIZE 0x10000 85 #elif defined(CONFIG_SDCARD) 86 #define CONFIG_SYS_EXTRA_ENV_RELOC 87 #define CONFIG_FSL_FIXED_MMC_LOCATION 88 #define CONFIG_SYS_MMC_ENV_DEV 0 89 #define CONFIG_ENV_SIZE 0x2000 90 #define CONFIG_ENV_OFFSET (512 * 1658) 91 #elif defined(CONFIG_NAND) 92 #define CONFIG_SYS_EXTRA_ENV_RELOC 93 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 94 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 95 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 96 #define CONFIG_ENV_IS_IN_REMOTE 97 #define CONFIG_ENV_ADDR 0xffe20000 98 #define CONFIG_ENV_SIZE 0x2000 99 #elif defined(CONFIG_ENV_IS_NOWHERE) 100 #define CONFIG_ENV_SIZE 0x2000 101 #else 102 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 103 #define CONFIG_ENV_SIZE 0x2000 104 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 105 #endif 106 107 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 108 109 /* 110 * These can be toggled for performance analysis, otherwise use default. 111 */ 112 #define CONFIG_SYS_CACHE_STASHING 113 #define CONFIG_BACKSIDE_L2_CACHE 114 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 115 #define CONFIG_BTB /* toggle branch predition */ 116 #define CONFIG_DDR_ECC 117 #ifdef CONFIG_DDR_ECC 118 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 119 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 120 #endif 121 122 #define CONFIG_ENABLE_36BIT_PHYS 123 124 #ifdef CONFIG_PHYS_64BIT 125 #define CONFIG_ADDR_MAP 126 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 127 #endif 128 129 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 130 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 131 #define CONFIG_SYS_MEMTEST_END 0x00400000 132 #define CONFIG_SYS_ALT_MEMTEST 133 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 134 135 /* 136 * Config the L3 Cache as L3 SRAM 137 */ 138 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 139 #ifdef CONFIG_PHYS_64BIT 140 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) 141 #else 142 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 143 #endif 144 #define CONFIG_SYS_L3_SIZE (1024 << 10) 145 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 146 147 #ifdef CONFIG_PHYS_64BIT 148 #define CONFIG_SYS_DCSRBAR 0xf0000000 149 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 150 #endif 151 152 /* EEPROM */ 153 #define CONFIG_ID_EEPROM 154 #define CONFIG_SYS_I2C_EEPROM_NXID 155 #define CONFIG_SYS_EEPROM_BUS_NUM 0 156 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 157 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 158 159 /* 160 * DDR Setup 161 */ 162 #define CONFIG_VERY_BIG_RAM 163 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 164 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 165 166 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 167 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 168 169 #define CONFIG_DDR_SPD 170 171 #define CONFIG_SYS_SPD_BUS_NUM 1 172 #define SPD_EEPROM_ADDRESS1 0x51 173 #define SPD_EEPROM_ADDRESS2 0x52 174 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 175 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 176 177 /* 178 * Local Bus Definitions 179 */ 180 181 /* Set the local bus clock 1/8 of platform clock */ 182 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 183 184 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */ 185 #ifdef CONFIG_PHYS_64BIT 186 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 187 #else 188 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 189 #endif 190 191 #define CONFIG_SYS_FLASH_BR_PRELIM \ 192 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \ 193 | BR_PS_16 | BR_V) 194 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 195 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 196 197 #define CONFIG_SYS_BR1_PRELIM \ 198 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 199 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 200 201 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 202 #ifdef CONFIG_PHYS_64BIT 203 #define PIXIS_BASE_PHYS 0xfffdf0000ull 204 #else 205 #define PIXIS_BASE_PHYS PIXIS_BASE 206 #endif 207 208 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 209 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 210 211 #define PIXIS_LBMAP_SWITCH 7 212 #define PIXIS_LBMAP_MASK 0xf0 213 #define PIXIS_LBMAP_SHIFT 4 214 #define PIXIS_LBMAP_ALTBANK 0x40 215 216 #define CONFIG_SYS_FLASH_QUIET_TEST 217 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 218 219 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 220 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 221 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 222 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 223 224 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 225 226 #if defined(CONFIG_RAMBOOT_PBL) 227 #define CONFIG_SYS_RAMBOOT 228 #endif 229 230 /* Nand Flash */ 231 #ifdef CONFIG_NAND_FSL_ELBC 232 #define CONFIG_SYS_NAND_BASE 0xffa00000 233 #ifdef CONFIG_PHYS_64BIT 234 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 235 #else 236 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 237 #endif 238 239 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 240 #define CONFIG_SYS_MAX_NAND_DEVICE 1 241 #define CONFIG_CMD_NAND 242 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 243 244 /* NAND flash config */ 245 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 246 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 247 | BR_PS_8 /* Port Size = 8 bit */ \ 248 | BR_MS_FCM /* MSEL = FCM */ \ 249 | BR_V) /* valid */ 250 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 251 | OR_FCM_PGS /* Large Page*/ \ 252 | OR_FCM_CSCT \ 253 | OR_FCM_CST \ 254 | OR_FCM_CHT \ 255 | OR_FCM_SCY_1 \ 256 | OR_FCM_TRLX \ 257 | OR_FCM_EHTR) 258 259 #ifdef CONFIG_NAND 260 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 261 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 262 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 263 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 264 #else 265 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 266 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 267 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 268 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 269 #endif 270 #else 271 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 272 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 273 #endif /* CONFIG_NAND_FSL_ELBC */ 274 275 #define CONFIG_SYS_FLASH_EMPTY_INFO 276 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 277 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 278 279 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 280 #define CONFIG_MISC_INIT_R 281 282 #define CONFIG_HWCONFIG 283 284 /* define to use L1 as initial stack */ 285 #define CONFIG_L1_INIT_RAM 286 #define CONFIG_SYS_INIT_RAM_LOCK 287 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 288 #ifdef CONFIG_PHYS_64BIT 289 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 290 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 291 /* The assembler doesn't like typecast */ 292 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 293 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 294 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 295 #else 296 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ 297 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 298 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 299 #endif 300 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 301 302 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 303 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 304 305 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 306 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 307 308 /* Serial Port - controlled on board with jumper J8 309 * open - index 2 310 * shorted - index 1 311 */ 312 #define CONFIG_CONS_INDEX 1 313 #define CONFIG_SYS_NS16550_SERIAL 314 #define CONFIG_SYS_NS16550_REG_SIZE 1 315 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 316 317 #define CONFIG_SYS_BAUDRATE_TABLE \ 318 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 319 320 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 321 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 322 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 323 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 324 325 /* I2C */ 326 #define CONFIG_SYS_I2C 327 #define CONFIG_SYS_I2C_FSL 328 #define CONFIG_SYS_FSL_I2C_SPEED 400000 329 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 330 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 331 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 332 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 333 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 334 335 /* 336 * RapidIO 337 */ 338 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 339 #ifdef CONFIG_PHYS_64BIT 340 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 341 #else 342 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 343 #endif 344 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 345 346 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 347 #ifdef CONFIG_PHYS_64BIT 348 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 349 #else 350 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 351 #endif 352 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 353 354 /* 355 * for slave u-boot IMAGE instored in master memory space, 356 * PHYS must be aligned based on the SIZE 357 */ 358 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 359 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 360 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 361 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 362 /* 363 * for slave UCODE and ENV instored in master memory space, 364 * PHYS must be aligned based on the SIZE 365 */ 366 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 367 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 368 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 369 370 /* slave core release by master*/ 371 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 372 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 373 374 /* 375 * SRIO_PCIE_BOOT - SLAVE 376 */ 377 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 378 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 379 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 380 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 381 #endif 382 383 /* 384 * eSPI - Enhanced SPI 385 */ 386 #define CONFIG_SF_DEFAULT_SPEED 10000000 387 #define CONFIG_SF_DEFAULT_MODE 0 388 389 /* 390 * General PCI 391 * Memory space is mapped 1-1, but I/O space must start from 0. 392 */ 393 394 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 395 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 396 #ifdef CONFIG_PHYS_64BIT 397 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 398 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 399 #else 400 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 401 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 402 #endif 403 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 404 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 405 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 406 #ifdef CONFIG_PHYS_64BIT 407 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 408 #else 409 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 410 #endif 411 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 412 413 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 414 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 415 #ifdef CONFIG_PHYS_64BIT 416 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 417 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 418 #else 419 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 420 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 421 #endif 422 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 423 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 424 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 425 #ifdef CONFIG_PHYS_64BIT 426 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 427 #else 428 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 429 #endif 430 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 431 432 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 433 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 434 #ifdef CONFIG_PHYS_64BIT 435 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 436 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 437 #else 438 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 439 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 440 #endif 441 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 442 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 443 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 444 #ifdef CONFIG_PHYS_64BIT 445 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 446 #else 447 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 448 #endif 449 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 450 451 /* controller 4, Base address 203000 */ 452 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 453 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 454 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 455 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 456 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 457 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 458 459 /* Qman/Bman */ 460 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 461 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 462 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 463 #ifdef CONFIG_PHYS_64BIT 464 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 465 #else 466 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 467 #endif 468 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 469 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 470 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 471 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 472 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 473 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 474 CONFIG_SYS_BMAN_CENA_SIZE) 475 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 476 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 477 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 478 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 479 #ifdef CONFIG_PHYS_64BIT 480 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 481 #else 482 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 483 #endif 484 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 485 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 486 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 487 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 488 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 489 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 490 CONFIG_SYS_QMAN_CENA_SIZE) 491 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 492 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 493 494 #define CONFIG_SYS_DPAA_FMAN 495 #define CONFIG_SYS_DPAA_PME 496 /* Default address of microcode for the Linux Fman driver */ 497 #if defined(CONFIG_SPIFLASH) 498 /* 499 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 500 * env, so we got 0x110000. 501 */ 502 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 503 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 504 #elif defined(CONFIG_SDCARD) 505 /* 506 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 507 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 508 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 509 */ 510 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 511 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 512 #elif defined(CONFIG_NAND) 513 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 514 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 515 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 516 /* 517 * Slave has no ucode locally, it can fetch this from remote. When implementing 518 * in two corenet boards, slave's ucode could be stored in master's memory 519 * space, the address can be mapped from slave TLB->slave LAW-> 520 * slave SRIO or PCIE outbound window->master inbound window-> 521 * master LAW->the ucode address in master's memory space. 522 */ 523 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 524 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 525 #else 526 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 527 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 528 #endif 529 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 530 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 531 532 #ifdef CONFIG_SYS_DPAA_FMAN 533 #define CONFIG_FMAN_ENET 534 #define CONFIG_PHYLIB_10G 535 #define CONFIG_PHY_VITESSE 536 #define CONFIG_PHY_TERANETICS 537 #endif 538 539 #ifdef CONFIG_PCI 540 #define CONFIG_PCI_INDIRECT_BRIDGE 541 542 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 543 #endif /* CONFIG_PCI */ 544 545 /* SATA */ 546 #ifdef CONFIG_FSL_SATA_V2 547 #define CONFIG_LIBATA 548 #define CONFIG_FSL_SATA 549 550 #define CONFIG_SYS_SATA_MAX_DEVICE 2 551 #define CONFIG_SATA1 552 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 553 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 554 #define CONFIG_SATA2 555 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 556 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 557 558 #define CONFIG_LBA48 559 #endif 560 561 #ifdef CONFIG_FMAN_ENET 562 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c 563 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d 564 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e 565 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f 566 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 567 568 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c 569 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d 570 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e 571 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f 572 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0 573 574 #define CONFIG_SYS_TBIPA_VALUE 8 575 #define CONFIG_MII /* MII PHY management */ 576 #define CONFIG_ETHPRIME "FM1@DTSEC1" 577 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 578 #endif 579 580 /* 581 * Environment 582 */ 583 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 584 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 585 586 /* 587 * Command line configuration. 588 */ 589 #define CONFIG_CMD_REGINFO 590 591 #ifdef CONFIG_PCI 592 #define CONFIG_CMD_PCI 593 #endif 594 595 /* 596 * USB 597 */ 598 #define CONFIG_HAS_FSL_DR_USB 599 #define CONFIG_HAS_FSL_MPH_USB 600 601 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 602 #define CONFIG_USB_EHCI_FSL 603 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 604 #endif 605 606 #ifdef CONFIG_MMC 607 #define CONFIG_FSL_ESDHC 608 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 609 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 610 #endif 611 612 /* 613 * Miscellaneous configurable options 614 */ 615 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 616 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 617 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 618 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 619 #ifdef CONFIG_CMD_KGDB 620 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 621 #else 622 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 623 #endif 624 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 625 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 626 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 627 628 /* 629 * For booting Linux, the board info and command line data 630 * have to be in the first 64 MB of memory, since this is 631 * the maximum mapped by the Linux kernel during initialization. 632 */ 633 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 634 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 635 636 #ifdef CONFIG_CMD_KGDB 637 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 638 #endif 639 640 /* 641 * Environment Configuration 642 */ 643 #define CONFIG_ROOTPATH "/opt/nfsroot" 644 #define CONFIG_BOOTFILE "uImage" 645 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 646 647 /* default location for tftp and bootm */ 648 #define CONFIG_LOADADDR 1000000 649 650 #ifdef CONFIG_TARGET_P4080DS 651 #define __USB_PHY_TYPE ulpi 652 #else 653 #define __USB_PHY_TYPE utmi 654 #endif 655 656 #define CONFIG_EXTRA_ENV_SETTINGS \ 657 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 658 "bank_intlv=cs0_cs1;" \ 659 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 660 "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 661 "netdev=eth0\0" \ 662 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 663 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 664 "tftpflash=tftpboot $loadaddr $uboot && " \ 665 "protect off $ubootaddr +$filesize && " \ 666 "erase $ubootaddr +$filesize && " \ 667 "cp.b $loadaddr $ubootaddr $filesize && " \ 668 "protect on $ubootaddr +$filesize && " \ 669 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 670 "consoledev=ttyS0\0" \ 671 "ramdiskaddr=2000000\0" \ 672 "ramdiskfile=p4080ds/ramdisk.uboot\0" \ 673 "fdtaddr=1e00000\0" \ 674 "fdtfile=p4080ds/p4080ds.dtb\0" \ 675 "bdev=sda3\0" 676 677 #define CONFIG_HDBOOT \ 678 "setenv bootargs root=/dev/$bdev rw " \ 679 "console=$consoledev,$baudrate $othbootargs;" \ 680 "tftp $loadaddr $bootfile;" \ 681 "tftp $fdtaddr $fdtfile;" \ 682 "bootm $loadaddr - $fdtaddr" 683 684 #define CONFIG_NFSBOOTCOMMAND \ 685 "setenv bootargs root=/dev/nfs rw " \ 686 "nfsroot=$serverip:$rootpath " \ 687 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 688 "console=$consoledev,$baudrate $othbootargs;" \ 689 "tftp $loadaddr $bootfile;" \ 690 "tftp $fdtaddr $fdtfile;" \ 691 "bootm $loadaddr - $fdtaddr" 692 693 #define CONFIG_RAMBOOTCOMMAND \ 694 "setenv bootargs root=/dev/ram rw " \ 695 "console=$consoledev,$baudrate $othbootargs;" \ 696 "tftp $ramdiskaddr $ramdiskfile;" \ 697 "tftp $loadaddr $bootfile;" \ 698 "tftp $fdtaddr $fdtfile;" \ 699 "bootm $loadaddr $ramdiskaddr $fdtaddr" 700 701 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 702 703 #include <asm/fsl_secure_boot.h> 704 705 #endif /* __CONFIG_H */ 706