1 /* 2 * Copyright 2009-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * Corenet DS style board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #include "../board/freescale/common/ics307_clk.h" 14 15 #ifdef CONFIG_RAMBOOT_PBL 16 #ifdef CONFIG_SECURE_BOOT 17 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 18 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 19 #ifdef CONFIG_NAND 20 #define CONFIG_RAMBOOT_NAND 21 #endif 22 #define CONFIG_BOOTSCRIPT_COPY_RAM 23 #else 24 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 25 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 26 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg 27 #if defined(CONFIG_TARGET_P3041DS) 28 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg 29 #elif defined(CONFIG_TARGET_P4080DS) 30 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg 31 #elif defined(CONFIG_TARGET_P5020DS) 32 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg 33 #elif defined(CONFIG_TARGET_P5040DS) 34 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg 35 #endif 36 #endif 37 #endif 38 39 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 40 /* Set 1M boot space */ 41 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 42 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 43 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 44 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 45 #endif 46 47 /* High Level Configuration Options */ 48 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 49 #define CONFIG_MP /* support multiple processors */ 50 51 #ifndef CONFIG_SYS_TEXT_BASE 52 #define CONFIG_SYS_TEXT_BASE 0xeff40000 53 #endif 54 55 #ifndef CONFIG_RESET_VECTOR_ADDRESS 56 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 57 #endif 58 59 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 60 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 61 #define CONFIG_PCIE1 /* PCIE controller 1 */ 62 #define CONFIG_PCIE2 /* PCIE controller 2 */ 63 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 64 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 65 66 #define CONFIG_ENV_OVERWRITE 67 68 #ifndef CONFIG_MTD_NOR_FLASH 69 #else 70 #define CONFIG_FLASH_CFI_DRIVER 71 #define CONFIG_SYS_FLASH_CFI 72 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 73 #endif 74 75 #if defined(CONFIG_SPIFLASH) 76 #define CONFIG_SYS_EXTRA_ENV_RELOC 77 #define CONFIG_ENV_SPI_BUS 0 78 #define CONFIG_ENV_SPI_CS 0 79 #define CONFIG_ENV_SPI_MAX_HZ 10000000 80 #define CONFIG_ENV_SPI_MODE 0 81 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 82 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 83 #define CONFIG_ENV_SECT_SIZE 0x10000 84 #elif defined(CONFIG_SDCARD) 85 #define CONFIG_SYS_EXTRA_ENV_RELOC 86 #define CONFIG_FSL_FIXED_MMC_LOCATION 87 #define CONFIG_SYS_MMC_ENV_DEV 0 88 #define CONFIG_ENV_SIZE 0x2000 89 #define CONFIG_ENV_OFFSET (512 * 1658) 90 #elif defined(CONFIG_NAND) 91 #define CONFIG_SYS_EXTRA_ENV_RELOC 92 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 93 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 94 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 95 #define CONFIG_ENV_ADDR 0xffe20000 96 #define CONFIG_ENV_SIZE 0x2000 97 #elif defined(CONFIG_ENV_IS_NOWHERE) 98 #define CONFIG_ENV_SIZE 0x2000 99 #else 100 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 101 #define CONFIG_ENV_SIZE 0x2000 102 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 103 #endif 104 105 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 106 107 /* 108 * These can be toggled for performance analysis, otherwise use default. 109 */ 110 #define CONFIG_SYS_CACHE_STASHING 111 #define CONFIG_BACKSIDE_L2_CACHE 112 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 113 #define CONFIG_BTB /* toggle branch predition */ 114 #define CONFIG_DDR_ECC 115 #ifdef CONFIG_DDR_ECC 116 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 117 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 118 #endif 119 120 #define CONFIG_ENABLE_36BIT_PHYS 121 122 #ifdef CONFIG_PHYS_64BIT 123 #define CONFIG_ADDR_MAP 124 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 125 #endif 126 127 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 128 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 129 #define CONFIG_SYS_MEMTEST_END 0x00400000 130 #define CONFIG_SYS_ALT_MEMTEST 131 132 /* 133 * Config the L3 Cache as L3 SRAM 134 */ 135 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 136 #ifdef CONFIG_PHYS_64BIT 137 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) 138 #else 139 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 140 #endif 141 #define CONFIG_SYS_L3_SIZE (1024 << 10) 142 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 143 144 #ifdef CONFIG_PHYS_64BIT 145 #define CONFIG_SYS_DCSRBAR 0xf0000000 146 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 147 #endif 148 149 /* EEPROM */ 150 #define CONFIG_ID_EEPROM 151 #define CONFIG_SYS_I2C_EEPROM_NXID 152 #define CONFIG_SYS_EEPROM_BUS_NUM 0 153 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 154 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 155 156 /* 157 * DDR Setup 158 */ 159 #define CONFIG_VERY_BIG_RAM 160 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 161 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 162 163 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 164 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 165 166 #define CONFIG_DDR_SPD 167 168 #define CONFIG_SYS_SPD_BUS_NUM 1 169 #define SPD_EEPROM_ADDRESS1 0x51 170 #define SPD_EEPROM_ADDRESS2 0x52 171 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 172 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 173 174 /* 175 * Local Bus Definitions 176 */ 177 178 /* Set the local bus clock 1/8 of platform clock */ 179 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 180 181 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */ 182 #ifdef CONFIG_PHYS_64BIT 183 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 184 #else 185 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 186 #endif 187 188 #define CONFIG_SYS_FLASH_BR_PRELIM \ 189 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \ 190 | BR_PS_16 | BR_V) 191 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 192 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 193 194 #define CONFIG_SYS_BR1_PRELIM \ 195 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 196 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 197 198 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 199 #ifdef CONFIG_PHYS_64BIT 200 #define PIXIS_BASE_PHYS 0xfffdf0000ull 201 #else 202 #define PIXIS_BASE_PHYS PIXIS_BASE 203 #endif 204 205 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 206 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 207 208 #define PIXIS_LBMAP_SWITCH 7 209 #define PIXIS_LBMAP_MASK 0xf0 210 #define PIXIS_LBMAP_SHIFT 4 211 #define PIXIS_LBMAP_ALTBANK 0x40 212 213 #define CONFIG_SYS_FLASH_QUIET_TEST 214 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 215 216 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 217 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 218 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 219 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 220 221 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 222 223 #if defined(CONFIG_RAMBOOT_PBL) 224 #define CONFIG_SYS_RAMBOOT 225 #endif 226 227 /* Nand Flash */ 228 #ifdef CONFIG_NAND_FSL_ELBC 229 #define CONFIG_SYS_NAND_BASE 0xffa00000 230 #ifdef CONFIG_PHYS_64BIT 231 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 232 #else 233 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 234 #endif 235 236 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 237 #define CONFIG_SYS_MAX_NAND_DEVICE 1 238 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 239 240 /* NAND flash config */ 241 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 242 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 243 | BR_PS_8 /* Port Size = 8 bit */ \ 244 | BR_MS_FCM /* MSEL = FCM */ \ 245 | BR_V) /* valid */ 246 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 247 | OR_FCM_PGS /* Large Page*/ \ 248 | OR_FCM_CSCT \ 249 | OR_FCM_CST \ 250 | OR_FCM_CHT \ 251 | OR_FCM_SCY_1 \ 252 | OR_FCM_TRLX \ 253 | OR_FCM_EHTR) 254 255 #ifdef CONFIG_NAND 256 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 257 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 258 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 259 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 260 #else 261 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 262 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 263 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 264 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 265 #endif 266 #else 267 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 268 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 269 #endif /* CONFIG_NAND_FSL_ELBC */ 270 271 #define CONFIG_SYS_FLASH_EMPTY_INFO 272 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 273 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 274 275 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 276 #define CONFIG_MISC_INIT_R 277 278 #define CONFIG_HWCONFIG 279 280 /* define to use L1 as initial stack */ 281 #define CONFIG_L1_INIT_RAM 282 #define CONFIG_SYS_INIT_RAM_LOCK 283 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 284 #ifdef CONFIG_PHYS_64BIT 285 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 286 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 287 /* The assembler doesn't like typecast */ 288 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 289 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 290 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 291 #else 292 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ 293 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 294 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 295 #endif 296 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 297 298 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 299 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 300 301 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 302 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 303 304 /* Serial Port - controlled on board with jumper J8 305 * open - index 2 306 * shorted - index 1 307 */ 308 #define CONFIG_CONS_INDEX 1 309 #define CONFIG_SYS_NS16550_SERIAL 310 #define CONFIG_SYS_NS16550_REG_SIZE 1 311 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 312 313 #define CONFIG_SYS_BAUDRATE_TABLE \ 314 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 315 316 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 317 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 318 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 319 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 320 321 /* I2C */ 322 #define CONFIG_SYS_I2C 323 #define CONFIG_SYS_I2C_FSL 324 #define CONFIG_SYS_FSL_I2C_SPEED 400000 325 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 326 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 327 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 328 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 329 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 330 331 /* 332 * RapidIO 333 */ 334 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 335 #ifdef CONFIG_PHYS_64BIT 336 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 337 #else 338 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 339 #endif 340 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 341 342 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 343 #ifdef CONFIG_PHYS_64BIT 344 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 345 #else 346 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 347 #endif 348 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 349 350 /* 351 * for slave u-boot IMAGE instored in master memory space, 352 * PHYS must be aligned based on the SIZE 353 */ 354 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 355 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 356 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 357 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 358 /* 359 * for slave UCODE and ENV instored in master memory space, 360 * PHYS must be aligned based on the SIZE 361 */ 362 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 363 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 364 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 365 366 /* slave core release by master*/ 367 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 368 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 369 370 /* 371 * SRIO_PCIE_BOOT - SLAVE 372 */ 373 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 374 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 375 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 376 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 377 #endif 378 379 /* 380 * eSPI - Enhanced SPI 381 */ 382 #define CONFIG_SF_DEFAULT_SPEED 10000000 383 #define CONFIG_SF_DEFAULT_MODE 0 384 385 /* 386 * General PCI 387 * Memory space is mapped 1-1, but I/O space must start from 0. 388 */ 389 390 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 391 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 392 #ifdef CONFIG_PHYS_64BIT 393 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 394 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 395 #else 396 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 397 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 398 #endif 399 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 400 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 401 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 402 #ifdef CONFIG_PHYS_64BIT 403 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 404 #else 405 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 406 #endif 407 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 408 409 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 410 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 411 #ifdef CONFIG_PHYS_64BIT 412 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 413 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 414 #else 415 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 416 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 417 #endif 418 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 419 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 420 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 421 #ifdef CONFIG_PHYS_64BIT 422 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 423 #else 424 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 425 #endif 426 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 427 428 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 429 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 430 #ifdef CONFIG_PHYS_64BIT 431 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 432 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 433 #else 434 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 435 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 436 #endif 437 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 438 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 439 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 440 #ifdef CONFIG_PHYS_64BIT 441 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 442 #else 443 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 444 #endif 445 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 446 447 /* controller 4, Base address 203000 */ 448 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 449 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 450 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 451 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 452 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 453 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 454 455 /* Qman/Bman */ 456 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 457 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 458 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 459 #ifdef CONFIG_PHYS_64BIT 460 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 461 #else 462 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 463 #endif 464 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 465 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 466 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 467 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 468 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 469 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 470 CONFIG_SYS_BMAN_CENA_SIZE) 471 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 472 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 473 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 474 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 475 #ifdef CONFIG_PHYS_64BIT 476 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 477 #else 478 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 479 #endif 480 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 481 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 482 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 483 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 484 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 485 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 486 CONFIG_SYS_QMAN_CENA_SIZE) 487 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 488 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 489 490 #define CONFIG_SYS_DPAA_FMAN 491 #define CONFIG_SYS_DPAA_PME 492 /* Default address of microcode for the Linux Fman driver */ 493 #if defined(CONFIG_SPIFLASH) 494 /* 495 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 496 * env, so we got 0x110000. 497 */ 498 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 499 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 500 #elif defined(CONFIG_SDCARD) 501 /* 502 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 503 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 504 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 505 */ 506 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 507 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 508 #elif defined(CONFIG_NAND) 509 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 510 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 511 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 512 /* 513 * Slave has no ucode locally, it can fetch this from remote. When implementing 514 * in two corenet boards, slave's ucode could be stored in master's memory 515 * space, the address can be mapped from slave TLB->slave LAW-> 516 * slave SRIO or PCIE outbound window->master inbound window-> 517 * master LAW->the ucode address in master's memory space. 518 */ 519 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 520 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 521 #else 522 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 523 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 524 #endif 525 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 526 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 527 528 #ifdef CONFIG_SYS_DPAA_FMAN 529 #define CONFIG_FMAN_ENET 530 #define CONFIG_PHYLIB_10G 531 #define CONFIG_PHY_VITESSE 532 #define CONFIG_PHY_TERANETICS 533 #endif 534 535 #ifdef CONFIG_PCI 536 #define CONFIG_PCI_INDIRECT_BRIDGE 537 538 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 539 #endif /* CONFIG_PCI */ 540 541 /* SATA */ 542 #ifdef CONFIG_FSL_SATA_V2 543 #define CONFIG_SYS_SATA_MAX_DEVICE 2 544 #define CONFIG_SATA1 545 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 546 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 547 #define CONFIG_SATA2 548 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 549 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 550 551 #define CONFIG_LBA48 552 #endif 553 554 #ifdef CONFIG_FMAN_ENET 555 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c 556 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d 557 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e 558 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f 559 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 560 561 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c 562 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d 563 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e 564 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f 565 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0 566 567 #define CONFIG_SYS_TBIPA_VALUE 8 568 #define CONFIG_MII /* MII PHY management */ 569 #define CONFIG_ETHPRIME "FM1@DTSEC1" 570 #endif 571 572 /* 573 * Environment 574 */ 575 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 576 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 577 578 /* 579 * USB 580 */ 581 #define CONFIG_HAS_FSL_DR_USB 582 #define CONFIG_HAS_FSL_MPH_USB 583 584 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 585 #define CONFIG_USB_EHCI_FSL 586 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 587 #endif 588 589 #ifdef CONFIG_MMC 590 #define CONFIG_FSL_ESDHC 591 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 592 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 593 #endif 594 595 /* 596 * Miscellaneous configurable options 597 */ 598 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 599 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 600 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 601 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 602 603 /* 604 * For booting Linux, the board info and command line data 605 * have to be in the first 64 MB of memory, since this is 606 * the maximum mapped by the Linux kernel during initialization. 607 */ 608 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 609 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 610 611 #ifdef CONFIG_CMD_KGDB 612 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 613 #endif 614 615 /* 616 * Environment Configuration 617 */ 618 #define CONFIG_ROOTPATH "/opt/nfsroot" 619 #define CONFIG_BOOTFILE "uImage" 620 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 621 622 /* default location for tftp and bootm */ 623 #define CONFIG_LOADADDR 1000000 624 625 #ifdef CONFIG_TARGET_P4080DS 626 #define __USB_PHY_TYPE ulpi 627 #else 628 #define __USB_PHY_TYPE utmi 629 #endif 630 631 #define CONFIG_EXTRA_ENV_SETTINGS \ 632 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 633 "bank_intlv=cs0_cs1;" \ 634 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 635 "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 636 "netdev=eth0\0" \ 637 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 638 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 639 "tftpflash=tftpboot $loadaddr $uboot && " \ 640 "protect off $ubootaddr +$filesize && " \ 641 "erase $ubootaddr +$filesize && " \ 642 "cp.b $loadaddr $ubootaddr $filesize && " \ 643 "protect on $ubootaddr +$filesize && " \ 644 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 645 "consoledev=ttyS0\0" \ 646 "ramdiskaddr=2000000\0" \ 647 "ramdiskfile=p4080ds/ramdisk.uboot\0" \ 648 "fdtaddr=1e00000\0" \ 649 "fdtfile=p4080ds/p4080ds.dtb\0" \ 650 "bdev=sda3\0" 651 652 #define CONFIG_HDBOOT \ 653 "setenv bootargs root=/dev/$bdev rw " \ 654 "console=$consoledev,$baudrate $othbootargs;" \ 655 "tftp $loadaddr $bootfile;" \ 656 "tftp $fdtaddr $fdtfile;" \ 657 "bootm $loadaddr - $fdtaddr" 658 659 #define CONFIG_NFSBOOTCOMMAND \ 660 "setenv bootargs root=/dev/nfs rw " \ 661 "nfsroot=$serverip:$rootpath " \ 662 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 663 "console=$consoledev,$baudrate $othbootargs;" \ 664 "tftp $loadaddr $bootfile;" \ 665 "tftp $fdtaddr $fdtfile;" \ 666 "bootm $loadaddr - $fdtaddr" 667 668 #define CONFIG_RAMBOOTCOMMAND \ 669 "setenv bootargs root=/dev/ram rw " \ 670 "console=$consoledev,$baudrate $othbootargs;" \ 671 "tftp $ramdiskaddr $ramdiskfile;" \ 672 "tftp $loadaddr $bootfile;" \ 673 "tftp $fdtaddr $fdtfile;" \ 674 "bootm $loadaddr $ramdiskaddr $fdtaddr" 675 676 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 677 678 #include <asm/fsl_secure_boot.h> 679 680 #endif /* __CONFIG_H */ 681