1 /* 2 * Copyright 2009-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * Corenet DS style board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #include "../board/freescale/common/ics307_clk.h" 14 15 #ifdef CONFIG_RAMBOOT_PBL 16 #ifdef CONFIG_SECURE_BOOT 17 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 18 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 19 #ifdef CONFIG_NAND 20 #define CONFIG_RAMBOOT_NAND 21 #endif 22 #define CONFIG_BOOTSCRIPT_COPY_RAM 23 #else 24 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 25 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 26 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg 27 #if defined(CONFIG_P3041DS) 28 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg 29 #elif defined(CONFIG_P4080DS) 30 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg 31 #elif defined(CONFIG_P5020DS) 32 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg 33 #elif defined(CONFIG_P5040DS) 34 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg 35 #endif 36 #endif 37 #endif 38 39 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 40 /* Set 1M boot space */ 41 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 42 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 43 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 44 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 45 #define CONFIG_SYS_NO_FLASH 46 #endif 47 48 /* High Level Configuration Options */ 49 #define CONFIG_BOOKE 50 #define CONFIG_E500 /* BOOKE e500 family */ 51 #define CONFIG_E500MC /* BOOKE e500mc family */ 52 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 53 #define CONFIG_MP /* support multiple processors */ 54 55 #ifndef CONFIG_SYS_TEXT_BASE 56 #define CONFIG_SYS_TEXT_BASE 0xeff40000 57 #endif 58 59 #ifndef CONFIG_RESET_VECTOR_ADDRESS 60 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 61 #endif 62 63 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 64 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 65 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 66 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 67 #define CONFIG_PCI /* Enable PCI/PCIE */ 68 #define CONFIG_PCIE1 /* PCIE controller 1 */ 69 #define CONFIG_PCIE2 /* PCIE controller 2 */ 70 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 71 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 72 73 #define CONFIG_FSL_LAW /* Use common FSL init code */ 74 75 #define CONFIG_ENV_OVERWRITE 76 77 #ifdef CONFIG_SYS_NO_FLASH 78 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) 79 #define CONFIG_ENV_IS_NOWHERE 80 #endif 81 #else 82 #define CONFIG_FLASH_CFI_DRIVER 83 #define CONFIG_SYS_FLASH_CFI 84 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 85 #endif 86 87 #if defined(CONFIG_SPIFLASH) 88 #define CONFIG_SYS_EXTRA_ENV_RELOC 89 #define CONFIG_ENV_IS_IN_SPI_FLASH 90 #define CONFIG_ENV_SPI_BUS 0 91 #define CONFIG_ENV_SPI_CS 0 92 #define CONFIG_ENV_SPI_MAX_HZ 10000000 93 #define CONFIG_ENV_SPI_MODE 0 94 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 95 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 96 #define CONFIG_ENV_SECT_SIZE 0x10000 97 #elif defined(CONFIG_SDCARD) 98 #define CONFIG_SYS_EXTRA_ENV_RELOC 99 #define CONFIG_ENV_IS_IN_MMC 100 #define CONFIG_FSL_FIXED_MMC_LOCATION 101 #define CONFIG_SYS_MMC_ENV_DEV 0 102 #define CONFIG_ENV_SIZE 0x2000 103 #define CONFIG_ENV_OFFSET (512 * 1658) 104 #elif defined(CONFIG_NAND) 105 #define CONFIG_SYS_EXTRA_ENV_RELOC 106 #define CONFIG_ENV_IS_IN_NAND 107 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 108 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 109 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 110 #define CONFIG_ENV_IS_IN_REMOTE 111 #define CONFIG_ENV_ADDR 0xffe20000 112 #define CONFIG_ENV_SIZE 0x2000 113 #elif defined(CONFIG_ENV_IS_NOWHERE) 114 #define CONFIG_ENV_SIZE 0x2000 115 #else 116 #define CONFIG_ENV_IS_IN_FLASH 117 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 118 #define CONFIG_ENV_SIZE 0x2000 119 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 120 #endif 121 122 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 123 124 /* 125 * These can be toggled for performance analysis, otherwise use default. 126 */ 127 #define CONFIG_SYS_CACHE_STASHING 128 #define CONFIG_BACKSIDE_L2_CACHE 129 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 130 #define CONFIG_BTB /* toggle branch predition */ 131 #define CONFIG_DDR_ECC 132 #ifdef CONFIG_DDR_ECC 133 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 134 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 135 #endif 136 137 #define CONFIG_ENABLE_36BIT_PHYS 138 139 #ifdef CONFIG_PHYS_64BIT 140 #define CONFIG_ADDR_MAP 141 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 142 #endif 143 144 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 145 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 146 #define CONFIG_SYS_MEMTEST_END 0x00400000 147 #define CONFIG_SYS_ALT_MEMTEST 148 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 149 150 /* 151 * Config the L3 Cache as L3 SRAM 152 */ 153 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 154 #ifdef CONFIG_PHYS_64BIT 155 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) 156 #else 157 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 158 #endif 159 #define CONFIG_SYS_L3_SIZE (1024 << 10) 160 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 161 162 #ifdef CONFIG_PHYS_64BIT 163 #define CONFIG_SYS_DCSRBAR 0xf0000000 164 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 165 #endif 166 167 /* EEPROM */ 168 #define CONFIG_ID_EEPROM 169 #define CONFIG_SYS_I2C_EEPROM_NXID 170 #define CONFIG_SYS_EEPROM_BUS_NUM 0 171 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 172 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 173 174 /* 175 * DDR Setup 176 */ 177 #define CONFIG_VERY_BIG_RAM 178 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 179 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 180 181 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 182 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 183 184 #define CONFIG_DDR_SPD 185 #define CONFIG_SYS_FSL_DDR3 186 187 #define CONFIG_SYS_SPD_BUS_NUM 1 188 #define SPD_EEPROM_ADDRESS1 0x51 189 #define SPD_EEPROM_ADDRESS2 0x52 190 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 191 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 192 193 /* 194 * Local Bus Definitions 195 */ 196 197 /* Set the local bus clock 1/8 of platform clock */ 198 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 199 200 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */ 201 #ifdef CONFIG_PHYS_64BIT 202 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 203 #else 204 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 205 #endif 206 207 #define CONFIG_SYS_FLASH_BR_PRELIM \ 208 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \ 209 | BR_PS_16 | BR_V) 210 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 211 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 212 213 #define CONFIG_SYS_BR1_PRELIM \ 214 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 215 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 216 217 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 218 #ifdef CONFIG_PHYS_64BIT 219 #define PIXIS_BASE_PHYS 0xfffdf0000ull 220 #else 221 #define PIXIS_BASE_PHYS PIXIS_BASE 222 #endif 223 224 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 225 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 226 227 #define PIXIS_LBMAP_SWITCH 7 228 #define PIXIS_LBMAP_MASK 0xf0 229 #define PIXIS_LBMAP_SHIFT 4 230 #define PIXIS_LBMAP_ALTBANK 0x40 231 232 #define CONFIG_SYS_FLASH_QUIET_TEST 233 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 234 235 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 236 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 237 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 238 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 239 240 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 241 242 #if defined(CONFIG_RAMBOOT_PBL) 243 #define CONFIG_SYS_RAMBOOT 244 #endif 245 246 /* Nand Flash */ 247 #ifdef CONFIG_NAND_FSL_ELBC 248 #define CONFIG_SYS_NAND_BASE 0xffa00000 249 #ifdef CONFIG_PHYS_64BIT 250 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 251 #else 252 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 253 #endif 254 255 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 256 #define CONFIG_SYS_MAX_NAND_DEVICE 1 257 #define CONFIG_CMD_NAND 258 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 259 260 /* NAND flash config */ 261 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 262 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 263 | BR_PS_8 /* Port Size = 8 bit */ \ 264 | BR_MS_FCM /* MSEL = FCM */ \ 265 | BR_V) /* valid */ 266 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 267 | OR_FCM_PGS /* Large Page*/ \ 268 | OR_FCM_CSCT \ 269 | OR_FCM_CST \ 270 | OR_FCM_CHT \ 271 | OR_FCM_SCY_1 \ 272 | OR_FCM_TRLX \ 273 | OR_FCM_EHTR) 274 275 #ifdef CONFIG_NAND 276 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 277 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 278 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 279 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 280 #else 281 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 282 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 283 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 284 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 285 #endif 286 #else 287 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 288 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 289 #endif /* CONFIG_NAND_FSL_ELBC */ 290 291 #define CONFIG_SYS_FLASH_EMPTY_INFO 292 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 293 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 294 295 #define CONFIG_BOARD_EARLY_INIT_F 296 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 297 #define CONFIG_MISC_INIT_R 298 299 #define CONFIG_HWCONFIG 300 301 /* define to use L1 as initial stack */ 302 #define CONFIG_L1_INIT_RAM 303 #define CONFIG_SYS_INIT_RAM_LOCK 304 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 305 #ifdef CONFIG_PHYS_64BIT 306 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 307 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 308 /* The assembler doesn't like typecast */ 309 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 310 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 311 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 312 #else 313 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ 314 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 315 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 316 #endif 317 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 318 319 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 320 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 321 322 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 323 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 324 325 /* Serial Port - controlled on board with jumper J8 326 * open - index 2 327 * shorted - index 1 328 */ 329 #define CONFIG_CONS_INDEX 1 330 #define CONFIG_SYS_NS16550_SERIAL 331 #define CONFIG_SYS_NS16550_REG_SIZE 1 332 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 333 334 #define CONFIG_SYS_BAUDRATE_TABLE \ 335 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 336 337 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 338 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 339 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 340 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 341 342 /* I2C */ 343 #define CONFIG_SYS_I2C 344 #define CONFIG_SYS_I2C_FSL 345 #define CONFIG_SYS_FSL_I2C_SPEED 400000 346 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 347 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 348 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 349 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 350 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 351 352 /* 353 * RapidIO 354 */ 355 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 356 #ifdef CONFIG_PHYS_64BIT 357 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 358 #else 359 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 360 #endif 361 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 362 363 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 364 #ifdef CONFIG_PHYS_64BIT 365 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 366 #else 367 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 368 #endif 369 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 370 371 /* 372 * for slave u-boot IMAGE instored in master memory space, 373 * PHYS must be aligned based on the SIZE 374 */ 375 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 376 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 377 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 378 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 379 /* 380 * for slave UCODE and ENV instored in master memory space, 381 * PHYS must be aligned based on the SIZE 382 */ 383 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 384 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 385 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 386 387 /* slave core release by master*/ 388 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 389 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 390 391 /* 392 * SRIO_PCIE_BOOT - SLAVE 393 */ 394 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 395 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 396 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 397 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 398 #endif 399 400 /* 401 * eSPI - Enhanced SPI 402 */ 403 #define CONFIG_SF_DEFAULT_SPEED 10000000 404 #define CONFIG_SF_DEFAULT_MODE 0 405 406 /* 407 * General PCI 408 * Memory space is mapped 1-1, but I/O space must start from 0. 409 */ 410 411 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 412 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 413 #ifdef CONFIG_PHYS_64BIT 414 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 415 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 416 #else 417 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 418 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 419 #endif 420 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 421 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 422 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 423 #ifdef CONFIG_PHYS_64BIT 424 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 425 #else 426 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 427 #endif 428 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 429 430 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 431 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 432 #ifdef CONFIG_PHYS_64BIT 433 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 434 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 435 #else 436 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 437 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 438 #endif 439 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 440 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 441 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 442 #ifdef CONFIG_PHYS_64BIT 443 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 444 #else 445 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 446 #endif 447 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 448 449 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 450 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 451 #ifdef CONFIG_PHYS_64BIT 452 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 453 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 454 #else 455 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 456 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 457 #endif 458 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 459 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 460 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 461 #ifdef CONFIG_PHYS_64BIT 462 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 463 #else 464 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 465 #endif 466 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 467 468 /* controller 4, Base address 203000 */ 469 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 470 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 471 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 472 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 473 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 474 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 475 476 /* Qman/Bman */ 477 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 478 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 479 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 480 #ifdef CONFIG_PHYS_64BIT 481 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 482 #else 483 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 484 #endif 485 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 486 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 487 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 488 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 489 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 490 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 491 CONFIG_SYS_BMAN_CENA_SIZE) 492 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 493 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 494 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 495 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 496 #ifdef CONFIG_PHYS_64BIT 497 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 498 #else 499 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 500 #endif 501 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 502 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 503 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 504 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 505 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 506 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 507 CONFIG_SYS_QMAN_CENA_SIZE) 508 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 509 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 510 511 #define CONFIG_SYS_DPAA_FMAN 512 #define CONFIG_SYS_DPAA_PME 513 /* Default address of microcode for the Linux Fman driver */ 514 #if defined(CONFIG_SPIFLASH) 515 /* 516 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 517 * env, so we got 0x110000. 518 */ 519 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 520 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 521 #elif defined(CONFIG_SDCARD) 522 /* 523 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 524 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 525 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 526 */ 527 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 528 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 529 #elif defined(CONFIG_NAND) 530 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 531 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 532 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 533 /* 534 * Slave has no ucode locally, it can fetch this from remote. When implementing 535 * in two corenet boards, slave's ucode could be stored in master's memory 536 * space, the address can be mapped from slave TLB->slave LAW-> 537 * slave SRIO or PCIE outbound window->master inbound window-> 538 * master LAW->the ucode address in master's memory space. 539 */ 540 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 541 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 542 #else 543 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 544 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 545 #endif 546 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 547 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 548 549 #ifdef CONFIG_SYS_DPAA_FMAN 550 #define CONFIG_FMAN_ENET 551 #define CONFIG_PHYLIB_10G 552 #define CONFIG_PHY_VITESSE 553 #define CONFIG_PHY_TERANETICS 554 #endif 555 556 #ifdef CONFIG_PCI 557 #define CONFIG_PCI_INDIRECT_BRIDGE 558 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 559 560 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 561 #define CONFIG_DOS_PARTITION 562 #endif /* CONFIG_PCI */ 563 564 /* SATA */ 565 #ifdef CONFIG_FSL_SATA_V2 566 #define CONFIG_LIBATA 567 #define CONFIG_FSL_SATA 568 569 #define CONFIG_SYS_SATA_MAX_DEVICE 2 570 #define CONFIG_SATA1 571 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 572 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 573 #define CONFIG_SATA2 574 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 575 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 576 577 #define CONFIG_LBA48 578 #define CONFIG_CMD_SATA 579 #define CONFIG_DOS_PARTITION 580 #endif 581 582 #ifdef CONFIG_FMAN_ENET 583 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c 584 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d 585 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e 586 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f 587 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 588 589 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c 590 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d 591 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e 592 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f 593 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0 594 595 #define CONFIG_SYS_TBIPA_VALUE 8 596 #define CONFIG_MII /* MII PHY management */ 597 #define CONFIG_ETHPRIME "FM1@DTSEC1" 598 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 599 #endif 600 601 /* 602 * Environment 603 */ 604 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 605 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 606 607 /* 608 * Command line configuration. 609 */ 610 #define CONFIG_CMD_ERRATA 611 #define CONFIG_CMD_IRQ 612 #define CONFIG_CMD_REGINFO 613 614 #ifdef CONFIG_PCI 615 #define CONFIG_CMD_PCI 616 #endif 617 618 /* 619 * USB 620 */ 621 #define CONFIG_HAS_FSL_DR_USB 622 #define CONFIG_HAS_FSL_MPH_USB 623 624 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 625 #define CONFIG_USB_EHCI 626 #define CONFIG_USB_EHCI_FSL 627 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 628 #endif 629 630 #ifdef CONFIG_MMC 631 #define CONFIG_FSL_ESDHC 632 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 633 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 634 #define CONFIG_GENERIC_MMC 635 #define CONFIG_DOS_PARTITION 636 #endif 637 638 /* Hash command with SHA acceleration supported in hardware */ 639 #ifdef CONFIG_FSL_CAAM 640 #define CONFIG_CMD_HASH 641 #define CONFIG_SHA_HW_ACCEL 642 #endif 643 644 /* 645 * Miscellaneous configurable options 646 */ 647 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 648 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 649 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 650 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 651 #ifdef CONFIG_CMD_KGDB 652 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 653 #else 654 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 655 #endif 656 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 657 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 658 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 659 660 /* 661 * For booting Linux, the board info and command line data 662 * have to be in the first 64 MB of memory, since this is 663 * the maximum mapped by the Linux kernel during initialization. 664 */ 665 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 666 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 667 668 #ifdef CONFIG_CMD_KGDB 669 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 670 #endif 671 672 /* 673 * Environment Configuration 674 */ 675 #define CONFIG_ROOTPATH "/opt/nfsroot" 676 #define CONFIG_BOOTFILE "uImage" 677 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 678 679 /* default location for tftp and bootm */ 680 #define CONFIG_LOADADDR 1000000 681 682 683 #define CONFIG_BAUDRATE 115200 684 685 #ifdef CONFIG_P4080DS 686 #define __USB_PHY_TYPE ulpi 687 #else 688 #define __USB_PHY_TYPE utmi 689 #endif 690 691 #define CONFIG_EXTRA_ENV_SETTINGS \ 692 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 693 "bank_intlv=cs0_cs1;" \ 694 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 695 "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 696 "netdev=eth0\0" \ 697 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 698 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 699 "tftpflash=tftpboot $loadaddr $uboot && " \ 700 "protect off $ubootaddr +$filesize && " \ 701 "erase $ubootaddr +$filesize && " \ 702 "cp.b $loadaddr $ubootaddr $filesize && " \ 703 "protect on $ubootaddr +$filesize && " \ 704 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 705 "consoledev=ttyS0\0" \ 706 "ramdiskaddr=2000000\0" \ 707 "ramdiskfile=p4080ds/ramdisk.uboot\0" \ 708 "fdtaddr=1e00000\0" \ 709 "fdtfile=p4080ds/p4080ds.dtb\0" \ 710 "bdev=sda3\0" 711 712 #define CONFIG_HDBOOT \ 713 "setenv bootargs root=/dev/$bdev rw " \ 714 "console=$consoledev,$baudrate $othbootargs;" \ 715 "tftp $loadaddr $bootfile;" \ 716 "tftp $fdtaddr $fdtfile;" \ 717 "bootm $loadaddr - $fdtaddr" 718 719 #define CONFIG_NFSBOOTCOMMAND \ 720 "setenv bootargs root=/dev/nfs rw " \ 721 "nfsroot=$serverip:$rootpath " \ 722 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 723 "console=$consoledev,$baudrate $othbootargs;" \ 724 "tftp $loadaddr $bootfile;" \ 725 "tftp $fdtaddr $fdtfile;" \ 726 "bootm $loadaddr - $fdtaddr" 727 728 #define CONFIG_RAMBOOTCOMMAND \ 729 "setenv bootargs root=/dev/ram rw " \ 730 "console=$consoledev,$baudrate $othbootargs;" \ 731 "tftp $ramdiskaddr $ramdiskfile;" \ 732 "tftp $loadaddr $bootfile;" \ 733 "tftp $fdtaddr $fdtfile;" \ 734 "bootm $loadaddr $ramdiskaddr $fdtaddr" 735 736 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 737 738 #include <asm/fsl_secure_boot.h> 739 740 #endif /* __CONFIG_H */ 741