1 /* 2 * Copyright 2009-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * Corenet DS style board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #include "../board/freescale/common/ics307_clk.h" 14 15 #ifdef CONFIG_RAMBOOT_PBL 16 #ifdef CONFIG_SECURE_BOOT 17 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 18 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 19 #ifdef CONFIG_NAND 20 #define CONFIG_RAMBOOT_NAND 21 #endif 22 #define CONFIG_BOOTSCRIPT_COPY_RAM 23 #else 24 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 25 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 26 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg 27 #if defined(CONFIG_P3041DS) 28 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg 29 #elif defined(CONFIG_P4080DS) 30 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg 31 #elif defined(CONFIG_P5020DS) 32 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg 33 #elif defined(CONFIG_P5040DS) 34 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg 35 #endif 36 #endif 37 #endif 38 39 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 40 /* Set 1M boot space */ 41 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 42 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 43 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 44 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 45 #define CONFIG_SYS_NO_FLASH 46 #endif 47 48 /* High Level Configuration Options */ 49 #define CONFIG_BOOKE 50 #define CONFIG_E500 /* BOOKE e500 family */ 51 #define CONFIG_E500MC /* BOOKE e500mc family */ 52 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 53 #define CONFIG_MP /* support multiple processors */ 54 55 #ifndef CONFIG_SYS_TEXT_BASE 56 #define CONFIG_SYS_TEXT_BASE 0xeff40000 57 #endif 58 59 #ifndef CONFIG_RESET_VECTOR_ADDRESS 60 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 61 #endif 62 63 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 64 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 65 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 66 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 67 #define CONFIG_PCIE1 /* PCIE controller 1 */ 68 #define CONFIG_PCIE2 /* PCIE controller 2 */ 69 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 70 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 71 72 #define CONFIG_FSL_LAW /* Use common FSL init code */ 73 74 #define CONFIG_ENV_OVERWRITE 75 76 #ifdef CONFIG_SYS_NO_FLASH 77 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) 78 #define CONFIG_ENV_IS_NOWHERE 79 #endif 80 #else 81 #define CONFIG_FLASH_CFI_DRIVER 82 #define CONFIG_SYS_FLASH_CFI 83 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 84 #endif 85 86 #if defined(CONFIG_SPIFLASH) 87 #define CONFIG_SYS_EXTRA_ENV_RELOC 88 #define CONFIG_ENV_IS_IN_SPI_FLASH 89 #define CONFIG_ENV_SPI_BUS 0 90 #define CONFIG_ENV_SPI_CS 0 91 #define CONFIG_ENV_SPI_MAX_HZ 10000000 92 #define CONFIG_ENV_SPI_MODE 0 93 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 94 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 95 #define CONFIG_ENV_SECT_SIZE 0x10000 96 #elif defined(CONFIG_SDCARD) 97 #define CONFIG_SYS_EXTRA_ENV_RELOC 98 #define CONFIG_ENV_IS_IN_MMC 99 #define CONFIG_FSL_FIXED_MMC_LOCATION 100 #define CONFIG_SYS_MMC_ENV_DEV 0 101 #define CONFIG_ENV_SIZE 0x2000 102 #define CONFIG_ENV_OFFSET (512 * 1658) 103 #elif defined(CONFIG_NAND) 104 #define CONFIG_SYS_EXTRA_ENV_RELOC 105 #define CONFIG_ENV_IS_IN_NAND 106 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 107 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 108 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 109 #define CONFIG_ENV_IS_IN_REMOTE 110 #define CONFIG_ENV_ADDR 0xffe20000 111 #define CONFIG_ENV_SIZE 0x2000 112 #elif defined(CONFIG_ENV_IS_NOWHERE) 113 #define CONFIG_ENV_SIZE 0x2000 114 #else 115 #define CONFIG_ENV_IS_IN_FLASH 116 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 117 #define CONFIG_ENV_SIZE 0x2000 118 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 119 #endif 120 121 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 122 123 /* 124 * These can be toggled for performance analysis, otherwise use default. 125 */ 126 #define CONFIG_SYS_CACHE_STASHING 127 #define CONFIG_BACKSIDE_L2_CACHE 128 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 129 #define CONFIG_BTB /* toggle branch predition */ 130 #define CONFIG_DDR_ECC 131 #ifdef CONFIG_DDR_ECC 132 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 133 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 134 #endif 135 136 #define CONFIG_ENABLE_36BIT_PHYS 137 138 #ifdef CONFIG_PHYS_64BIT 139 #define CONFIG_ADDR_MAP 140 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 141 #endif 142 143 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 144 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 145 #define CONFIG_SYS_MEMTEST_END 0x00400000 146 #define CONFIG_SYS_ALT_MEMTEST 147 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 148 149 /* 150 * Config the L3 Cache as L3 SRAM 151 */ 152 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 153 #ifdef CONFIG_PHYS_64BIT 154 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) 155 #else 156 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 157 #endif 158 #define CONFIG_SYS_L3_SIZE (1024 << 10) 159 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 160 161 #ifdef CONFIG_PHYS_64BIT 162 #define CONFIG_SYS_DCSRBAR 0xf0000000 163 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 164 #endif 165 166 /* EEPROM */ 167 #define CONFIG_ID_EEPROM 168 #define CONFIG_SYS_I2C_EEPROM_NXID 169 #define CONFIG_SYS_EEPROM_BUS_NUM 0 170 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 171 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 172 173 /* 174 * DDR Setup 175 */ 176 #define CONFIG_VERY_BIG_RAM 177 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 178 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 179 180 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 181 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 182 183 #define CONFIG_DDR_SPD 184 #define CONFIG_SYS_FSL_DDR3 185 186 #define CONFIG_SYS_SPD_BUS_NUM 1 187 #define SPD_EEPROM_ADDRESS1 0x51 188 #define SPD_EEPROM_ADDRESS2 0x52 189 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 190 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 191 192 /* 193 * Local Bus Definitions 194 */ 195 196 /* Set the local bus clock 1/8 of platform clock */ 197 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 198 199 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */ 200 #ifdef CONFIG_PHYS_64BIT 201 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 202 #else 203 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 204 #endif 205 206 #define CONFIG_SYS_FLASH_BR_PRELIM \ 207 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \ 208 | BR_PS_16 | BR_V) 209 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 210 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 211 212 #define CONFIG_SYS_BR1_PRELIM \ 213 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 214 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 215 216 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 217 #ifdef CONFIG_PHYS_64BIT 218 #define PIXIS_BASE_PHYS 0xfffdf0000ull 219 #else 220 #define PIXIS_BASE_PHYS PIXIS_BASE 221 #endif 222 223 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 224 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 225 226 #define PIXIS_LBMAP_SWITCH 7 227 #define PIXIS_LBMAP_MASK 0xf0 228 #define PIXIS_LBMAP_SHIFT 4 229 #define PIXIS_LBMAP_ALTBANK 0x40 230 231 #define CONFIG_SYS_FLASH_QUIET_TEST 232 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 233 234 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 235 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 236 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 237 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 238 239 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 240 241 #if defined(CONFIG_RAMBOOT_PBL) 242 #define CONFIG_SYS_RAMBOOT 243 #endif 244 245 /* Nand Flash */ 246 #ifdef CONFIG_NAND_FSL_ELBC 247 #define CONFIG_SYS_NAND_BASE 0xffa00000 248 #ifdef CONFIG_PHYS_64BIT 249 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 250 #else 251 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 252 #endif 253 254 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 255 #define CONFIG_SYS_MAX_NAND_DEVICE 1 256 #define CONFIG_CMD_NAND 257 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 258 259 /* NAND flash config */ 260 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 261 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 262 | BR_PS_8 /* Port Size = 8 bit */ \ 263 | BR_MS_FCM /* MSEL = FCM */ \ 264 | BR_V) /* valid */ 265 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 266 | OR_FCM_PGS /* Large Page*/ \ 267 | OR_FCM_CSCT \ 268 | OR_FCM_CST \ 269 | OR_FCM_CHT \ 270 | OR_FCM_SCY_1 \ 271 | OR_FCM_TRLX \ 272 | OR_FCM_EHTR) 273 274 #ifdef CONFIG_NAND 275 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 276 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 277 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 278 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 279 #else 280 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 281 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 282 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 283 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 284 #endif 285 #else 286 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 287 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 288 #endif /* CONFIG_NAND_FSL_ELBC */ 289 290 #define CONFIG_SYS_FLASH_EMPTY_INFO 291 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 292 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 293 294 #define CONFIG_BOARD_EARLY_INIT_F 295 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 296 #define CONFIG_MISC_INIT_R 297 298 #define CONFIG_HWCONFIG 299 300 /* define to use L1 as initial stack */ 301 #define CONFIG_L1_INIT_RAM 302 #define CONFIG_SYS_INIT_RAM_LOCK 303 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 304 #ifdef CONFIG_PHYS_64BIT 305 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 306 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 307 /* The assembler doesn't like typecast */ 308 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 309 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 310 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 311 #else 312 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ 313 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 314 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 315 #endif 316 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 317 318 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 319 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 320 321 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 322 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 323 324 /* Serial Port - controlled on board with jumper J8 325 * open - index 2 326 * shorted - index 1 327 */ 328 #define CONFIG_CONS_INDEX 1 329 #define CONFIG_SYS_NS16550_SERIAL 330 #define CONFIG_SYS_NS16550_REG_SIZE 1 331 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 332 333 #define CONFIG_SYS_BAUDRATE_TABLE \ 334 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 335 336 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 337 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 338 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 339 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 340 341 /* I2C */ 342 #define CONFIG_SYS_I2C 343 #define CONFIG_SYS_I2C_FSL 344 #define CONFIG_SYS_FSL_I2C_SPEED 400000 345 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 346 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 347 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 348 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 349 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 350 351 /* 352 * RapidIO 353 */ 354 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 355 #ifdef CONFIG_PHYS_64BIT 356 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 357 #else 358 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 359 #endif 360 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 361 362 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 363 #ifdef CONFIG_PHYS_64BIT 364 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 365 #else 366 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 367 #endif 368 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 369 370 /* 371 * for slave u-boot IMAGE instored in master memory space, 372 * PHYS must be aligned based on the SIZE 373 */ 374 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 375 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 376 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 377 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 378 /* 379 * for slave UCODE and ENV instored in master memory space, 380 * PHYS must be aligned based on the SIZE 381 */ 382 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 383 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 384 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 385 386 /* slave core release by master*/ 387 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 388 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 389 390 /* 391 * SRIO_PCIE_BOOT - SLAVE 392 */ 393 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 394 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 395 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 396 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 397 #endif 398 399 /* 400 * eSPI - Enhanced SPI 401 */ 402 #define CONFIG_SF_DEFAULT_SPEED 10000000 403 #define CONFIG_SF_DEFAULT_MODE 0 404 405 /* 406 * General PCI 407 * Memory space is mapped 1-1, but I/O space must start from 0. 408 */ 409 410 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 411 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 412 #ifdef CONFIG_PHYS_64BIT 413 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 414 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 415 #else 416 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 417 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 418 #endif 419 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 420 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 421 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 422 #ifdef CONFIG_PHYS_64BIT 423 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 424 #else 425 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 426 #endif 427 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 428 429 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 430 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 431 #ifdef CONFIG_PHYS_64BIT 432 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 433 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 434 #else 435 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 436 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 437 #endif 438 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 439 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 440 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 441 #ifdef CONFIG_PHYS_64BIT 442 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 443 #else 444 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 445 #endif 446 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 447 448 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 449 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 450 #ifdef CONFIG_PHYS_64BIT 451 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 452 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 453 #else 454 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 455 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 456 #endif 457 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 458 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 459 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 460 #ifdef CONFIG_PHYS_64BIT 461 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 462 #else 463 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 464 #endif 465 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 466 467 /* controller 4, Base address 203000 */ 468 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 469 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 470 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 471 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 472 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 473 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 474 475 /* Qman/Bman */ 476 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 477 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 478 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 479 #ifdef CONFIG_PHYS_64BIT 480 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 481 #else 482 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 483 #endif 484 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 485 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 486 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 487 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 488 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 489 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 490 CONFIG_SYS_BMAN_CENA_SIZE) 491 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 492 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 493 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 494 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 495 #ifdef CONFIG_PHYS_64BIT 496 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 497 #else 498 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 499 #endif 500 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 501 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 502 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 503 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 504 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 505 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 506 CONFIG_SYS_QMAN_CENA_SIZE) 507 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 508 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 509 510 #define CONFIG_SYS_DPAA_FMAN 511 #define CONFIG_SYS_DPAA_PME 512 /* Default address of microcode for the Linux Fman driver */ 513 #if defined(CONFIG_SPIFLASH) 514 /* 515 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 516 * env, so we got 0x110000. 517 */ 518 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 519 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 520 #elif defined(CONFIG_SDCARD) 521 /* 522 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 523 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 524 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 525 */ 526 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 527 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 528 #elif defined(CONFIG_NAND) 529 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 530 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 531 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 532 /* 533 * Slave has no ucode locally, it can fetch this from remote. When implementing 534 * in two corenet boards, slave's ucode could be stored in master's memory 535 * space, the address can be mapped from slave TLB->slave LAW-> 536 * slave SRIO or PCIE outbound window->master inbound window-> 537 * master LAW->the ucode address in master's memory space. 538 */ 539 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 540 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 541 #else 542 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 543 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 544 #endif 545 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 546 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 547 548 #ifdef CONFIG_SYS_DPAA_FMAN 549 #define CONFIG_FMAN_ENET 550 #define CONFIG_PHYLIB_10G 551 #define CONFIG_PHY_VITESSE 552 #define CONFIG_PHY_TERANETICS 553 #endif 554 555 #ifdef CONFIG_PCI 556 #define CONFIG_PCI_INDIRECT_BRIDGE 557 558 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 559 #define CONFIG_DOS_PARTITION 560 #endif /* CONFIG_PCI */ 561 562 /* SATA */ 563 #ifdef CONFIG_FSL_SATA_V2 564 #define CONFIG_LIBATA 565 #define CONFIG_FSL_SATA 566 567 #define CONFIG_SYS_SATA_MAX_DEVICE 2 568 #define CONFIG_SATA1 569 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 570 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 571 #define CONFIG_SATA2 572 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 573 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 574 575 #define CONFIG_LBA48 576 #define CONFIG_CMD_SATA 577 #define CONFIG_DOS_PARTITION 578 #endif 579 580 #ifdef CONFIG_FMAN_ENET 581 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c 582 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d 583 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e 584 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f 585 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 586 587 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c 588 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d 589 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e 590 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f 591 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0 592 593 #define CONFIG_SYS_TBIPA_VALUE 8 594 #define CONFIG_MII /* MII PHY management */ 595 #define CONFIG_ETHPRIME "FM1@DTSEC1" 596 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 597 #endif 598 599 /* 600 * Environment 601 */ 602 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 603 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 604 605 /* 606 * Command line configuration. 607 */ 608 #define CONFIG_CMD_ERRATA 609 #define CONFIG_CMD_IRQ 610 #define CONFIG_CMD_REGINFO 611 612 #ifdef CONFIG_PCI 613 #define CONFIG_CMD_PCI 614 #endif 615 616 /* 617 * USB 618 */ 619 #define CONFIG_HAS_FSL_DR_USB 620 #define CONFIG_HAS_FSL_MPH_USB 621 622 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 623 #define CONFIG_USB_EHCI 624 #define CONFIG_USB_EHCI_FSL 625 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 626 #endif 627 628 #ifdef CONFIG_MMC 629 #define CONFIG_FSL_ESDHC 630 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 631 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 632 #define CONFIG_GENERIC_MMC 633 #define CONFIG_DOS_PARTITION 634 #endif 635 636 /* Hash command with SHA acceleration supported in hardware */ 637 #ifdef CONFIG_FSL_CAAM 638 #define CONFIG_CMD_HASH 639 #define CONFIG_SHA_HW_ACCEL 640 #endif 641 642 /* 643 * Miscellaneous configurable options 644 */ 645 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 646 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 647 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 648 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 649 #ifdef CONFIG_CMD_KGDB 650 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 651 #else 652 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 653 #endif 654 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 655 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 656 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 657 658 /* 659 * For booting Linux, the board info and command line data 660 * have to be in the first 64 MB of memory, since this is 661 * the maximum mapped by the Linux kernel during initialization. 662 */ 663 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 664 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 665 666 #ifdef CONFIG_CMD_KGDB 667 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 668 #endif 669 670 /* 671 * Environment Configuration 672 */ 673 #define CONFIG_ROOTPATH "/opt/nfsroot" 674 #define CONFIG_BOOTFILE "uImage" 675 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 676 677 /* default location for tftp and bootm */ 678 #define CONFIG_LOADADDR 1000000 679 680 681 #define CONFIG_BAUDRATE 115200 682 683 #ifdef CONFIG_P4080DS 684 #define __USB_PHY_TYPE ulpi 685 #else 686 #define __USB_PHY_TYPE utmi 687 #endif 688 689 #define CONFIG_EXTRA_ENV_SETTINGS \ 690 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 691 "bank_intlv=cs0_cs1;" \ 692 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 693 "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 694 "netdev=eth0\0" \ 695 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 696 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 697 "tftpflash=tftpboot $loadaddr $uboot && " \ 698 "protect off $ubootaddr +$filesize && " \ 699 "erase $ubootaddr +$filesize && " \ 700 "cp.b $loadaddr $ubootaddr $filesize && " \ 701 "protect on $ubootaddr +$filesize && " \ 702 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 703 "consoledev=ttyS0\0" \ 704 "ramdiskaddr=2000000\0" \ 705 "ramdiskfile=p4080ds/ramdisk.uboot\0" \ 706 "fdtaddr=1e00000\0" \ 707 "fdtfile=p4080ds/p4080ds.dtb\0" \ 708 "bdev=sda3\0" 709 710 #define CONFIG_HDBOOT \ 711 "setenv bootargs root=/dev/$bdev rw " \ 712 "console=$consoledev,$baudrate $othbootargs;" \ 713 "tftp $loadaddr $bootfile;" \ 714 "tftp $fdtaddr $fdtfile;" \ 715 "bootm $loadaddr - $fdtaddr" 716 717 #define CONFIG_NFSBOOTCOMMAND \ 718 "setenv bootargs root=/dev/nfs rw " \ 719 "nfsroot=$serverip:$rootpath " \ 720 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 721 "console=$consoledev,$baudrate $othbootargs;" \ 722 "tftp $loadaddr $bootfile;" \ 723 "tftp $fdtaddr $fdtfile;" \ 724 "bootm $loadaddr - $fdtaddr" 725 726 #define CONFIG_RAMBOOTCOMMAND \ 727 "setenv bootargs root=/dev/ram rw " \ 728 "console=$consoledev,$baudrate $othbootargs;" \ 729 "tftp $ramdiskaddr $ramdiskfile;" \ 730 "tftp $loadaddr $bootfile;" \ 731 "tftp $fdtaddr $fdtfile;" \ 732 "bootm $loadaddr $ramdiskaddr $fdtaddr" 733 734 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 735 736 #include <asm/fsl_secure_boot.h> 737 738 #endif /* __CONFIG_H */ 739