1 /* 2 * Copyright 2009-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * Corenet DS style board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_SYS_GENERIC_BOARD 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 #include "../board/freescale/common/ics307_clk.h" 17 18 #ifdef CONFIG_RAMBOOT_PBL 19 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 20 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 21 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg 22 #if defined(CONFIG_P3041DS) 23 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg 24 #elif defined(CONFIG_P4080DS) 25 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg 26 #elif defined(CONFIG_P5020DS) 27 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg 28 #elif defined(CONFIG_P5040DS) 29 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg 30 #endif 31 #endif 32 33 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 34 /* Set 1M boot space */ 35 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 36 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 37 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 38 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 39 #define CONFIG_SYS_NO_FLASH 40 #endif 41 42 /* High Level Configuration Options */ 43 #define CONFIG_BOOKE 44 #define CONFIG_E500 /* BOOKE e500 family */ 45 #define CONFIG_E500MC /* BOOKE e500mc family */ 46 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 47 #define CONFIG_MP /* support multiple processors */ 48 49 #ifndef CONFIG_SYS_TEXT_BASE 50 #define CONFIG_SYS_TEXT_BASE 0xeff40000 51 #endif 52 53 #ifndef CONFIG_RESET_VECTOR_ADDRESS 54 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 55 #endif 56 57 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 58 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 59 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 60 #define CONFIG_PCI /* Enable PCI/PCIE */ 61 #define CONFIG_PCIE1 /* PCIE controler 1 */ 62 #define CONFIG_PCIE2 /* PCIE controler 2 */ 63 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 64 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 65 66 #define CONFIG_FSL_LAW /* Use common FSL init code */ 67 68 #define CONFIG_ENV_OVERWRITE 69 70 #ifdef CONFIG_SYS_NO_FLASH 71 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) 72 #define CONFIG_ENV_IS_NOWHERE 73 #endif 74 #else 75 #define CONFIG_FLASH_CFI_DRIVER 76 #define CONFIG_SYS_FLASH_CFI 77 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 78 #endif 79 80 #if defined(CONFIG_SPIFLASH) 81 #define CONFIG_SYS_EXTRA_ENV_RELOC 82 #define CONFIG_ENV_IS_IN_SPI_FLASH 83 #define CONFIG_ENV_SPI_BUS 0 84 #define CONFIG_ENV_SPI_CS 0 85 #define CONFIG_ENV_SPI_MAX_HZ 10000000 86 #define CONFIG_ENV_SPI_MODE 0 87 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 88 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 89 #define CONFIG_ENV_SECT_SIZE 0x10000 90 #elif defined(CONFIG_SDCARD) 91 #define CONFIG_SYS_EXTRA_ENV_RELOC 92 #define CONFIG_ENV_IS_IN_MMC 93 #define CONFIG_FSL_FIXED_MMC_LOCATION 94 #define CONFIG_SYS_MMC_ENV_DEV 0 95 #define CONFIG_ENV_SIZE 0x2000 96 #define CONFIG_ENV_OFFSET (512 * 1658) 97 #elif defined(CONFIG_NAND) 98 #define CONFIG_SYS_EXTRA_ENV_RELOC 99 #define CONFIG_ENV_IS_IN_NAND 100 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 101 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 102 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 103 #define CONFIG_ENV_IS_IN_REMOTE 104 #define CONFIG_ENV_ADDR 0xffe20000 105 #define CONFIG_ENV_SIZE 0x2000 106 #elif defined(CONFIG_ENV_IS_NOWHERE) 107 #define CONFIG_ENV_SIZE 0x2000 108 #else 109 #define CONFIG_ENV_IS_IN_FLASH 110 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 111 #define CONFIG_ENV_SIZE 0x2000 112 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 113 #endif 114 115 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 116 117 /* 118 * These can be toggled for performance analysis, otherwise use default. 119 */ 120 #define CONFIG_SYS_CACHE_STASHING 121 #define CONFIG_BACKSIDE_L2_CACHE 122 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 123 #define CONFIG_BTB /* toggle branch predition */ 124 #define CONFIG_DDR_ECC 125 #ifdef CONFIG_DDR_ECC 126 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 127 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 128 #endif 129 130 #define CONFIG_ENABLE_36BIT_PHYS 131 132 #ifdef CONFIG_PHYS_64BIT 133 #define CONFIG_ADDR_MAP 134 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 135 #endif 136 137 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 138 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 139 #define CONFIG_SYS_MEMTEST_END 0x00400000 140 #define CONFIG_SYS_ALT_MEMTEST 141 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 142 143 /* 144 * Config the L3 Cache as L3 SRAM 145 */ 146 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 147 #ifdef CONFIG_PHYS_64BIT 148 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) 149 #else 150 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 151 #endif 152 #define CONFIG_SYS_L3_SIZE (1024 << 10) 153 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 154 155 #ifdef CONFIG_PHYS_64BIT 156 #define CONFIG_SYS_DCSRBAR 0xf0000000 157 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 158 #endif 159 160 /* EEPROM */ 161 #define CONFIG_ID_EEPROM 162 #define CONFIG_SYS_I2C_EEPROM_NXID 163 #define CONFIG_SYS_EEPROM_BUS_NUM 0 164 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 165 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 166 167 /* 168 * DDR Setup 169 */ 170 #define CONFIG_VERY_BIG_RAM 171 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 172 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 173 174 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 175 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 176 177 #define CONFIG_DDR_SPD 178 #define CONFIG_SYS_FSL_DDR3 179 180 #define CONFIG_SYS_SPD_BUS_NUM 1 181 #define SPD_EEPROM_ADDRESS1 0x51 182 #define SPD_EEPROM_ADDRESS2 0x52 183 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 184 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 185 186 /* 187 * Local Bus Definitions 188 */ 189 190 /* Set the local bus clock 1/8 of platform clock */ 191 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 192 193 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */ 194 #ifdef CONFIG_PHYS_64BIT 195 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 196 #else 197 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 198 #endif 199 200 #define CONFIG_SYS_FLASH_BR_PRELIM \ 201 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \ 202 | BR_PS_16 | BR_V) 203 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 204 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 205 206 #define CONFIG_SYS_BR1_PRELIM \ 207 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 208 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 209 210 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 211 #ifdef CONFIG_PHYS_64BIT 212 #define PIXIS_BASE_PHYS 0xfffdf0000ull 213 #else 214 #define PIXIS_BASE_PHYS PIXIS_BASE 215 #endif 216 217 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 218 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 219 220 #define PIXIS_LBMAP_SWITCH 7 221 #define PIXIS_LBMAP_MASK 0xf0 222 #define PIXIS_LBMAP_SHIFT 4 223 #define PIXIS_LBMAP_ALTBANK 0x40 224 225 #define CONFIG_SYS_FLASH_QUIET_TEST 226 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 227 228 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 229 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 230 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 231 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 232 233 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 234 235 #if defined(CONFIG_RAMBOOT_PBL) 236 #define CONFIG_SYS_RAMBOOT 237 #endif 238 239 /* Nand Flash */ 240 #ifdef CONFIG_NAND_FSL_ELBC 241 #define CONFIG_SYS_NAND_BASE 0xffa00000 242 #ifdef CONFIG_PHYS_64BIT 243 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 244 #else 245 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 246 #endif 247 248 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 249 #define CONFIG_SYS_MAX_NAND_DEVICE 1 250 #define CONFIG_MTD_NAND_VERIFY_WRITE 251 #define CONFIG_CMD_NAND 252 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 253 254 /* NAND flash config */ 255 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 256 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 257 | BR_PS_8 /* Port Size = 8 bit */ \ 258 | BR_MS_FCM /* MSEL = FCM */ \ 259 | BR_V) /* valid */ 260 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 261 | OR_FCM_PGS /* Large Page*/ \ 262 | OR_FCM_CSCT \ 263 | OR_FCM_CST \ 264 | OR_FCM_CHT \ 265 | OR_FCM_SCY_1 \ 266 | OR_FCM_TRLX \ 267 | OR_FCM_EHTR) 268 269 #ifdef CONFIG_NAND 270 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 271 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 272 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 273 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 274 #else 275 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 276 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 277 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 278 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 279 #endif 280 #else 281 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 282 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 283 #endif /* CONFIG_NAND_FSL_ELBC */ 284 285 #define CONFIG_SYS_FLASH_EMPTY_INFO 286 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 287 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 288 289 #define CONFIG_BOARD_EARLY_INIT_F 290 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 291 #define CONFIG_MISC_INIT_R 292 293 #define CONFIG_HWCONFIG 294 295 /* define to use L1 as initial stack */ 296 #define CONFIG_L1_INIT_RAM 297 #define CONFIG_SYS_INIT_RAM_LOCK 298 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 299 #ifdef CONFIG_PHYS_64BIT 300 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 301 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 302 /* The assembler doesn't like typecast */ 303 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 304 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 305 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 306 #else 307 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ 308 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 309 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 310 #endif 311 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 312 313 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 314 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 315 316 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 317 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 318 319 /* Serial Port - controlled on board with jumper J8 320 * open - index 2 321 * shorted - index 1 322 */ 323 #define CONFIG_CONS_INDEX 1 324 #define CONFIG_SYS_NS16550 325 #define CONFIG_SYS_NS16550_SERIAL 326 #define CONFIG_SYS_NS16550_REG_SIZE 1 327 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 328 329 #define CONFIG_SYS_BAUDRATE_TABLE \ 330 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 331 332 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 333 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 334 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 335 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 336 337 /* Use the HUSH parser */ 338 #define CONFIG_SYS_HUSH_PARSER 339 340 /* pass open firmware flat tree */ 341 #define CONFIG_OF_LIBFDT 342 #define CONFIG_OF_BOARD_SETUP 343 #define CONFIG_OF_STDOUT_VIA_ALIAS 344 345 /* new uImage format support */ 346 #define CONFIG_FIT 347 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 348 349 /* I2C */ 350 #define CONFIG_SYS_I2C 351 #define CONFIG_SYS_I2C_FSL 352 #define CONFIG_SYS_FSL_I2C_SPEED 400000 353 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 354 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 355 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 356 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 357 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 358 359 /* 360 * RapidIO 361 */ 362 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 363 #ifdef CONFIG_PHYS_64BIT 364 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 365 #else 366 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 367 #endif 368 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 369 370 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 371 #ifdef CONFIG_PHYS_64BIT 372 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 373 #else 374 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 375 #endif 376 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 377 378 /* 379 * for slave u-boot IMAGE instored in master memory space, 380 * PHYS must be aligned based on the SIZE 381 */ 382 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 383 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 384 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 385 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 386 /* 387 * for slave UCODE and ENV instored in master memory space, 388 * PHYS must be aligned based on the SIZE 389 */ 390 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 391 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 392 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 393 394 /* slave core release by master*/ 395 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 396 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 397 398 /* 399 * SRIO_PCIE_BOOT - SLAVE 400 */ 401 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 402 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 403 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 404 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 405 #endif 406 407 /* 408 * eSPI - Enhanced SPI 409 */ 410 #define CONFIG_FSL_ESPI 411 #define CONFIG_SPI_FLASH 412 #define CONFIG_SPI_FLASH_SPANSION 413 #define CONFIG_CMD_SF 414 #define CONFIG_SF_DEFAULT_SPEED 10000000 415 #define CONFIG_SF_DEFAULT_MODE 0 416 417 /* 418 * General PCI 419 * Memory space is mapped 1-1, but I/O space must start from 0. 420 */ 421 422 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 423 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 424 #ifdef CONFIG_PHYS_64BIT 425 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 426 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 427 #else 428 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 429 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 430 #endif 431 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 432 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 433 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 434 #ifdef CONFIG_PHYS_64BIT 435 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 436 #else 437 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 438 #endif 439 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 440 441 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 442 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 443 #ifdef CONFIG_PHYS_64BIT 444 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 445 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 446 #else 447 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 448 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 449 #endif 450 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 451 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 452 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 453 #ifdef CONFIG_PHYS_64BIT 454 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 455 #else 456 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 457 #endif 458 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 459 460 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 461 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 462 #ifdef CONFIG_PHYS_64BIT 463 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 464 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 465 #else 466 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 467 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 468 #endif 469 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 470 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 471 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 472 #ifdef CONFIG_PHYS_64BIT 473 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 474 #else 475 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 476 #endif 477 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 478 479 /* controller 4, Base address 203000 */ 480 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 481 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 482 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 483 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 484 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 485 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 486 487 /* Qman/Bman */ 488 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 489 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 490 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 491 #ifdef CONFIG_PHYS_64BIT 492 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 493 #else 494 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 495 #endif 496 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 497 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 498 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 499 #ifdef CONFIG_PHYS_64BIT 500 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 501 #else 502 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 503 #endif 504 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 505 506 #define CONFIG_SYS_DPAA_FMAN 507 #define CONFIG_SYS_DPAA_PME 508 /* Default address of microcode for the Linux Fman driver */ 509 #if defined(CONFIG_SPIFLASH) 510 /* 511 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 512 * env, so we got 0x110000. 513 */ 514 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 515 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 516 #elif defined(CONFIG_SDCARD) 517 /* 518 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 519 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 520 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 521 */ 522 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 523 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 524 #elif defined(CONFIG_NAND) 525 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 526 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 527 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 528 /* 529 * Slave has no ucode locally, it can fetch this from remote. When implementing 530 * in two corenet boards, slave's ucode could be stored in master's memory 531 * space, the address can be mapped from slave TLB->slave LAW-> 532 * slave SRIO or PCIE outbound window->master inbound window-> 533 * master LAW->the ucode address in master's memory space. 534 */ 535 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 536 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 537 #else 538 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 539 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 540 #endif 541 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 542 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 543 544 #ifdef CONFIG_SYS_DPAA_FMAN 545 #define CONFIG_FMAN_ENET 546 #define CONFIG_PHYLIB_10G 547 #define CONFIG_PHY_VITESSE 548 #define CONFIG_PHY_TERANETICS 549 #endif 550 551 #ifdef CONFIG_PCI 552 #define CONFIG_PCI_INDIRECT_BRIDGE 553 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 554 #define CONFIG_E1000 555 556 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 557 #define CONFIG_DOS_PARTITION 558 #endif /* CONFIG_PCI */ 559 560 /* SATA */ 561 #ifdef CONFIG_FSL_SATA_V2 562 #define CONFIG_LIBATA 563 #define CONFIG_FSL_SATA 564 565 #define CONFIG_SYS_SATA_MAX_DEVICE 2 566 #define CONFIG_SATA1 567 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 568 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 569 #define CONFIG_SATA2 570 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 571 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 572 573 #define CONFIG_LBA48 574 #define CONFIG_CMD_SATA 575 #define CONFIG_DOS_PARTITION 576 #define CONFIG_CMD_EXT2 577 #endif 578 579 #ifdef CONFIG_FMAN_ENET 580 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c 581 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d 582 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e 583 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f 584 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 585 586 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c 587 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d 588 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e 589 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f 590 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0 591 592 #define CONFIG_SYS_TBIPA_VALUE 8 593 #define CONFIG_MII /* MII PHY management */ 594 #define CONFIG_ETHPRIME "FM1@DTSEC1" 595 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 596 #endif 597 598 /* 599 * Environment 600 */ 601 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 602 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 603 604 /* 605 * Command line configuration. 606 */ 607 #include <config_cmd_default.h> 608 609 #define CONFIG_CMD_DHCP 610 #define CONFIG_CMD_ELF 611 #define CONFIG_CMD_ERRATA 612 #define CONFIG_CMD_GREPENV 613 #define CONFIG_CMD_IRQ 614 #define CONFIG_CMD_I2C 615 #define CONFIG_CMD_MII 616 #define CONFIG_CMD_PING 617 #define CONFIG_CMD_SETEXPR 618 #define CONFIG_CMD_REGINFO 619 620 #ifdef CONFIG_PCI 621 #define CONFIG_CMD_PCI 622 #define CONFIG_CMD_NET 623 #endif 624 625 /* 626 * USB 627 */ 628 #define CONFIG_HAS_FSL_DR_USB 629 #define CONFIG_HAS_FSL_MPH_USB 630 631 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 632 #define CONFIG_CMD_USB 633 #define CONFIG_USB_STORAGE 634 #define CONFIG_USB_EHCI 635 #define CONFIG_USB_EHCI_FSL 636 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 637 #define CONFIG_CMD_EXT2 638 #endif 639 640 #ifdef CONFIG_MMC 641 #define CONFIG_FSL_ESDHC 642 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 643 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 644 #define CONFIG_CMD_MMC 645 #define CONFIG_GENERIC_MMC 646 #define CONFIG_CMD_EXT2 647 #define CONFIG_CMD_FAT 648 #define CONFIG_DOS_PARTITION 649 #endif 650 651 /* 652 * Miscellaneous configurable options 653 */ 654 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 655 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 656 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 657 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 658 #ifdef CONFIG_CMD_KGDB 659 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 660 #else 661 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 662 #endif 663 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 664 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 665 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 666 667 /* 668 * For booting Linux, the board info and command line data 669 * have to be in the first 64 MB of memory, since this is 670 * the maximum mapped by the Linux kernel during initialization. 671 */ 672 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 673 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 674 675 #ifdef CONFIG_CMD_KGDB 676 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 677 #endif 678 679 /* 680 * Environment Configuration 681 */ 682 #define CONFIG_ROOTPATH "/opt/nfsroot" 683 #define CONFIG_BOOTFILE "uImage" 684 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 685 686 /* default location for tftp and bootm */ 687 #define CONFIG_LOADADDR 1000000 688 689 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 690 691 #define CONFIG_BAUDRATE 115200 692 693 #ifdef CONFIG_P4080DS 694 #define __USB_PHY_TYPE ulpi 695 #else 696 #define __USB_PHY_TYPE utmi 697 #endif 698 699 #define CONFIG_EXTRA_ENV_SETTINGS \ 700 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 701 "bank_intlv=cs0_cs1;" \ 702 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 703 "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 704 "netdev=eth0\0" \ 705 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 706 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 707 "tftpflash=tftpboot $loadaddr $uboot && " \ 708 "protect off $ubootaddr +$filesize && " \ 709 "erase $ubootaddr +$filesize && " \ 710 "cp.b $loadaddr $ubootaddr $filesize && " \ 711 "protect on $ubootaddr +$filesize && " \ 712 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 713 "consoledev=ttyS0\0" \ 714 "ramdiskaddr=2000000\0" \ 715 "ramdiskfile=p4080ds/ramdisk.uboot\0" \ 716 "fdtaddr=c00000\0" \ 717 "fdtfile=p4080ds/p4080ds.dtb\0" \ 718 "bdev=sda3\0" 719 720 #define CONFIG_HDBOOT \ 721 "setenv bootargs root=/dev/$bdev rw " \ 722 "console=$consoledev,$baudrate $othbootargs;" \ 723 "tftp $loadaddr $bootfile;" \ 724 "tftp $fdtaddr $fdtfile;" \ 725 "bootm $loadaddr - $fdtaddr" 726 727 #define CONFIG_NFSBOOTCOMMAND \ 728 "setenv bootargs root=/dev/nfs rw " \ 729 "nfsroot=$serverip:$rootpath " \ 730 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 731 "console=$consoledev,$baudrate $othbootargs;" \ 732 "tftp $loadaddr $bootfile;" \ 733 "tftp $fdtaddr $fdtfile;" \ 734 "bootm $loadaddr - $fdtaddr" 735 736 #define CONFIG_RAMBOOTCOMMAND \ 737 "setenv bootargs root=/dev/ram rw " \ 738 "console=$consoledev,$baudrate $othbootargs;" \ 739 "tftp $ramdiskaddr $ramdiskfile;" \ 740 "tftp $loadaddr $bootfile;" \ 741 "tftp $fdtaddr $fdtfile;" \ 742 "bootm $loadaddr $ramdiskaddr $fdtaddr" 743 744 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 745 746 #include <asm/fsl_secure_boot.h> 747 748 #endif /* __CONFIG_H */ 749