1 /* 2 * Copyright 2009-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * Corenet DS style board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #include "../board/freescale/common/ics307_clk.h" 14 15 #ifdef CONFIG_RAMBOOT_PBL 16 #ifdef CONFIG_SECURE_BOOT 17 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 18 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 19 #ifdef CONFIG_NAND 20 #define CONFIG_RAMBOOT_NAND 21 #endif 22 #define CONFIG_BOOTSCRIPT_COPY_RAM 23 #else 24 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 25 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 26 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg 27 #if defined(CONFIG_TARGET_P3041DS) 28 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg 29 #elif defined(CONFIG_TARGET_P4080DS) 30 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg 31 #elif defined(CONFIG_TARGET_P5020DS) 32 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg 33 #elif defined(CONFIG_TARGET_P5040DS) 34 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg 35 #endif 36 #endif 37 #endif 38 39 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 40 /* Set 1M boot space */ 41 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 42 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 43 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 44 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 45 #endif 46 47 /* High Level Configuration Options */ 48 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 49 #define CONFIG_MP /* support multiple processors */ 50 51 #ifndef CONFIG_SYS_TEXT_BASE 52 #define CONFIG_SYS_TEXT_BASE 0xeff40000 53 #endif 54 55 #ifndef CONFIG_RESET_VECTOR_ADDRESS 56 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 57 #endif 58 59 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 60 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 61 #define CONFIG_PCIE1 /* PCIE controller 1 */ 62 #define CONFIG_PCIE2 /* PCIE controller 2 */ 63 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 64 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 65 66 #define CONFIG_ENV_OVERWRITE 67 68 #ifndef CONFIG_MTD_NOR_FLASH 69 #else 70 #define CONFIG_FLASH_CFI_DRIVER 71 #define CONFIG_SYS_FLASH_CFI 72 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 73 #endif 74 75 #if defined(CONFIG_SPIFLASH) 76 #define CONFIG_SYS_EXTRA_ENV_RELOC 77 #define CONFIG_ENV_SPI_BUS 0 78 #define CONFIG_ENV_SPI_CS 0 79 #define CONFIG_ENV_SPI_MAX_HZ 10000000 80 #define CONFIG_ENV_SPI_MODE 0 81 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 82 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 83 #define CONFIG_ENV_SECT_SIZE 0x10000 84 #elif defined(CONFIG_SDCARD) 85 #define CONFIG_SYS_EXTRA_ENV_RELOC 86 #define CONFIG_FSL_FIXED_MMC_LOCATION 87 #define CONFIG_SYS_MMC_ENV_DEV 0 88 #define CONFIG_ENV_SIZE 0x2000 89 #define CONFIG_ENV_OFFSET (512 * 1658) 90 #elif defined(CONFIG_NAND) 91 #define CONFIG_SYS_EXTRA_ENV_RELOC 92 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 93 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 94 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 95 #define CONFIG_ENV_ADDR 0xffe20000 96 #define CONFIG_ENV_SIZE 0x2000 97 #elif defined(CONFIG_ENV_IS_NOWHERE) 98 #define CONFIG_ENV_SIZE 0x2000 99 #else 100 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 101 #define CONFIG_ENV_SIZE 0x2000 102 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 103 #endif 104 105 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 106 107 /* 108 * These can be toggled for performance analysis, otherwise use default. 109 */ 110 #define CONFIG_SYS_CACHE_STASHING 111 #define CONFIG_BACKSIDE_L2_CACHE 112 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 113 #define CONFIG_BTB /* toggle branch predition */ 114 #define CONFIG_DDR_ECC 115 #ifdef CONFIG_DDR_ECC 116 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 117 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 118 #endif 119 120 #define CONFIG_ENABLE_36BIT_PHYS 121 122 #ifdef CONFIG_PHYS_64BIT 123 #define CONFIG_ADDR_MAP 124 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 125 #endif 126 127 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 128 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 129 #define CONFIG_SYS_MEMTEST_END 0x00400000 130 #define CONFIG_SYS_ALT_MEMTEST 131 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 132 133 /* 134 * Config the L3 Cache as L3 SRAM 135 */ 136 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 137 #ifdef CONFIG_PHYS_64BIT 138 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) 139 #else 140 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 141 #endif 142 #define CONFIG_SYS_L3_SIZE (1024 << 10) 143 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 144 145 #ifdef CONFIG_PHYS_64BIT 146 #define CONFIG_SYS_DCSRBAR 0xf0000000 147 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 148 #endif 149 150 /* EEPROM */ 151 #define CONFIG_ID_EEPROM 152 #define CONFIG_SYS_I2C_EEPROM_NXID 153 #define CONFIG_SYS_EEPROM_BUS_NUM 0 154 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 155 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 156 157 /* 158 * DDR Setup 159 */ 160 #define CONFIG_VERY_BIG_RAM 161 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 162 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 163 164 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 165 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 166 167 #define CONFIG_DDR_SPD 168 169 #define CONFIG_SYS_SPD_BUS_NUM 1 170 #define SPD_EEPROM_ADDRESS1 0x51 171 #define SPD_EEPROM_ADDRESS2 0x52 172 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 173 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 174 175 /* 176 * Local Bus Definitions 177 */ 178 179 /* Set the local bus clock 1/8 of platform clock */ 180 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 181 182 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */ 183 #ifdef CONFIG_PHYS_64BIT 184 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 185 #else 186 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 187 #endif 188 189 #define CONFIG_SYS_FLASH_BR_PRELIM \ 190 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \ 191 | BR_PS_16 | BR_V) 192 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 193 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 194 195 #define CONFIG_SYS_BR1_PRELIM \ 196 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 197 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 198 199 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 200 #ifdef CONFIG_PHYS_64BIT 201 #define PIXIS_BASE_PHYS 0xfffdf0000ull 202 #else 203 #define PIXIS_BASE_PHYS PIXIS_BASE 204 #endif 205 206 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 207 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 208 209 #define PIXIS_LBMAP_SWITCH 7 210 #define PIXIS_LBMAP_MASK 0xf0 211 #define PIXIS_LBMAP_SHIFT 4 212 #define PIXIS_LBMAP_ALTBANK 0x40 213 214 #define CONFIG_SYS_FLASH_QUIET_TEST 215 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 216 217 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 218 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 219 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 220 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 221 222 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 223 224 #if defined(CONFIG_RAMBOOT_PBL) 225 #define CONFIG_SYS_RAMBOOT 226 #endif 227 228 /* Nand Flash */ 229 #ifdef CONFIG_NAND_FSL_ELBC 230 #define CONFIG_SYS_NAND_BASE 0xffa00000 231 #ifdef CONFIG_PHYS_64BIT 232 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 233 #else 234 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 235 #endif 236 237 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 238 #define CONFIG_SYS_MAX_NAND_DEVICE 1 239 #define CONFIG_CMD_NAND 240 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 241 242 /* NAND flash config */ 243 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 244 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 245 | BR_PS_8 /* Port Size = 8 bit */ \ 246 | BR_MS_FCM /* MSEL = FCM */ \ 247 | BR_V) /* valid */ 248 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 249 | OR_FCM_PGS /* Large Page*/ \ 250 | OR_FCM_CSCT \ 251 | OR_FCM_CST \ 252 | OR_FCM_CHT \ 253 | OR_FCM_SCY_1 \ 254 | OR_FCM_TRLX \ 255 | OR_FCM_EHTR) 256 257 #ifdef CONFIG_NAND 258 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 259 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 260 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 261 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 262 #else 263 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 264 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 265 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 266 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 267 #endif 268 #else 269 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 270 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 271 #endif /* CONFIG_NAND_FSL_ELBC */ 272 273 #define CONFIG_SYS_FLASH_EMPTY_INFO 274 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 275 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 276 277 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 278 #define CONFIG_MISC_INIT_R 279 280 #define CONFIG_HWCONFIG 281 282 /* define to use L1 as initial stack */ 283 #define CONFIG_L1_INIT_RAM 284 #define CONFIG_SYS_INIT_RAM_LOCK 285 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 286 #ifdef CONFIG_PHYS_64BIT 287 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 288 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 289 /* The assembler doesn't like typecast */ 290 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 291 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 292 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 293 #else 294 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ 295 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 296 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 297 #endif 298 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 299 300 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 301 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 302 303 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 304 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 305 306 /* Serial Port - controlled on board with jumper J8 307 * open - index 2 308 * shorted - index 1 309 */ 310 #define CONFIG_CONS_INDEX 1 311 #define CONFIG_SYS_NS16550_SERIAL 312 #define CONFIG_SYS_NS16550_REG_SIZE 1 313 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 314 315 #define CONFIG_SYS_BAUDRATE_TABLE \ 316 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 317 318 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 319 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 320 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 321 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 322 323 /* I2C */ 324 #define CONFIG_SYS_I2C 325 #define CONFIG_SYS_I2C_FSL 326 #define CONFIG_SYS_FSL_I2C_SPEED 400000 327 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 328 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 329 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 330 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 331 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 332 333 /* 334 * RapidIO 335 */ 336 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 337 #ifdef CONFIG_PHYS_64BIT 338 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 339 #else 340 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 341 #endif 342 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 343 344 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 345 #ifdef CONFIG_PHYS_64BIT 346 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 347 #else 348 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 349 #endif 350 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 351 352 /* 353 * for slave u-boot IMAGE instored in master memory space, 354 * PHYS must be aligned based on the SIZE 355 */ 356 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 357 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 358 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 359 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 360 /* 361 * for slave UCODE and ENV instored in master memory space, 362 * PHYS must be aligned based on the SIZE 363 */ 364 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 365 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 366 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 367 368 /* slave core release by master*/ 369 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 370 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 371 372 /* 373 * SRIO_PCIE_BOOT - SLAVE 374 */ 375 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 376 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 377 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 378 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 379 #endif 380 381 /* 382 * eSPI - Enhanced SPI 383 */ 384 #define CONFIG_SF_DEFAULT_SPEED 10000000 385 #define CONFIG_SF_DEFAULT_MODE 0 386 387 /* 388 * General PCI 389 * Memory space is mapped 1-1, but I/O space must start from 0. 390 */ 391 392 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 393 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 394 #ifdef CONFIG_PHYS_64BIT 395 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 396 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 397 #else 398 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 399 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 400 #endif 401 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 402 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 403 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 404 #ifdef CONFIG_PHYS_64BIT 405 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 406 #else 407 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 408 #endif 409 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 410 411 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 412 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 413 #ifdef CONFIG_PHYS_64BIT 414 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 415 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 416 #else 417 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 418 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 419 #endif 420 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 421 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 422 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 423 #ifdef CONFIG_PHYS_64BIT 424 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 425 #else 426 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 427 #endif 428 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 429 430 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 431 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 432 #ifdef CONFIG_PHYS_64BIT 433 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 434 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 435 #else 436 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 437 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 438 #endif 439 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 440 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 441 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 442 #ifdef CONFIG_PHYS_64BIT 443 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 444 #else 445 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 446 #endif 447 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 448 449 /* controller 4, Base address 203000 */ 450 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 451 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 452 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 453 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 454 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 455 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 456 457 /* Qman/Bman */ 458 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 459 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 460 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 461 #ifdef CONFIG_PHYS_64BIT 462 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 463 #else 464 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 465 #endif 466 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 467 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 468 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 469 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 470 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 471 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 472 CONFIG_SYS_BMAN_CENA_SIZE) 473 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 474 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 475 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 476 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 477 #ifdef CONFIG_PHYS_64BIT 478 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 479 #else 480 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 481 #endif 482 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 483 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 484 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 485 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 486 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 487 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 488 CONFIG_SYS_QMAN_CENA_SIZE) 489 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 490 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 491 492 #define CONFIG_SYS_DPAA_FMAN 493 #define CONFIG_SYS_DPAA_PME 494 /* Default address of microcode for the Linux Fman driver */ 495 #if defined(CONFIG_SPIFLASH) 496 /* 497 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 498 * env, so we got 0x110000. 499 */ 500 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 501 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 502 #elif defined(CONFIG_SDCARD) 503 /* 504 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 505 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 506 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 507 */ 508 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 509 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 510 #elif defined(CONFIG_NAND) 511 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 512 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 513 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 514 /* 515 * Slave has no ucode locally, it can fetch this from remote. When implementing 516 * in two corenet boards, slave's ucode could be stored in master's memory 517 * space, the address can be mapped from slave TLB->slave LAW-> 518 * slave SRIO or PCIE outbound window->master inbound window-> 519 * master LAW->the ucode address in master's memory space. 520 */ 521 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 522 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 523 #else 524 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 525 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 526 #endif 527 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 528 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 529 530 #ifdef CONFIG_SYS_DPAA_FMAN 531 #define CONFIG_FMAN_ENET 532 #define CONFIG_PHYLIB_10G 533 #define CONFIG_PHY_VITESSE 534 #define CONFIG_PHY_TERANETICS 535 #endif 536 537 #ifdef CONFIG_PCI 538 #define CONFIG_PCI_INDIRECT_BRIDGE 539 540 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 541 #endif /* CONFIG_PCI */ 542 543 /* SATA */ 544 #ifdef CONFIG_FSL_SATA_V2 545 #define CONFIG_LIBATA 546 #define CONFIG_FSL_SATA 547 548 #define CONFIG_SYS_SATA_MAX_DEVICE 2 549 #define CONFIG_SATA1 550 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 551 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 552 #define CONFIG_SATA2 553 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 554 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 555 556 #define CONFIG_LBA48 557 #endif 558 559 #ifdef CONFIG_FMAN_ENET 560 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c 561 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d 562 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e 563 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f 564 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 565 566 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c 567 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d 568 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e 569 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f 570 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0 571 572 #define CONFIG_SYS_TBIPA_VALUE 8 573 #define CONFIG_MII /* MII PHY management */ 574 #define CONFIG_ETHPRIME "FM1@DTSEC1" 575 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 576 #endif 577 578 /* 579 * Environment 580 */ 581 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 582 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 583 584 /* 585 * Command line configuration. 586 */ 587 #define CONFIG_CMD_REGINFO 588 589 #ifdef CONFIG_PCI 590 #define CONFIG_CMD_PCI 591 #endif 592 593 /* 594 * USB 595 */ 596 #define CONFIG_HAS_FSL_DR_USB 597 #define CONFIG_HAS_FSL_MPH_USB 598 599 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 600 #define CONFIG_USB_EHCI_FSL 601 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 602 #endif 603 604 #ifdef CONFIG_MMC 605 #define CONFIG_FSL_ESDHC 606 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 607 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 608 #endif 609 610 /* 611 * Miscellaneous configurable options 612 */ 613 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 614 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 615 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 616 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 617 #ifdef CONFIG_CMD_KGDB 618 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 619 #else 620 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 621 #endif 622 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 623 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 624 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 625 626 /* 627 * For booting Linux, the board info and command line data 628 * have to be in the first 64 MB of memory, since this is 629 * the maximum mapped by the Linux kernel during initialization. 630 */ 631 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 632 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 633 634 #ifdef CONFIG_CMD_KGDB 635 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 636 #endif 637 638 /* 639 * Environment Configuration 640 */ 641 #define CONFIG_ROOTPATH "/opt/nfsroot" 642 #define CONFIG_BOOTFILE "uImage" 643 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 644 645 /* default location for tftp and bootm */ 646 #define CONFIG_LOADADDR 1000000 647 648 #ifdef CONFIG_TARGET_P4080DS 649 #define __USB_PHY_TYPE ulpi 650 #else 651 #define __USB_PHY_TYPE utmi 652 #endif 653 654 #define CONFIG_EXTRA_ENV_SETTINGS \ 655 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 656 "bank_intlv=cs0_cs1;" \ 657 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 658 "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 659 "netdev=eth0\0" \ 660 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 661 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 662 "tftpflash=tftpboot $loadaddr $uboot && " \ 663 "protect off $ubootaddr +$filesize && " \ 664 "erase $ubootaddr +$filesize && " \ 665 "cp.b $loadaddr $ubootaddr $filesize && " \ 666 "protect on $ubootaddr +$filesize && " \ 667 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 668 "consoledev=ttyS0\0" \ 669 "ramdiskaddr=2000000\0" \ 670 "ramdiskfile=p4080ds/ramdisk.uboot\0" \ 671 "fdtaddr=1e00000\0" \ 672 "fdtfile=p4080ds/p4080ds.dtb\0" \ 673 "bdev=sda3\0" 674 675 #define CONFIG_HDBOOT \ 676 "setenv bootargs root=/dev/$bdev rw " \ 677 "console=$consoledev,$baudrate $othbootargs;" \ 678 "tftp $loadaddr $bootfile;" \ 679 "tftp $fdtaddr $fdtfile;" \ 680 "bootm $loadaddr - $fdtaddr" 681 682 #define CONFIG_NFSBOOTCOMMAND \ 683 "setenv bootargs root=/dev/nfs rw " \ 684 "nfsroot=$serverip:$rootpath " \ 685 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 686 "console=$consoledev,$baudrate $othbootargs;" \ 687 "tftp $loadaddr $bootfile;" \ 688 "tftp $fdtaddr $fdtfile;" \ 689 "bootm $loadaddr - $fdtaddr" 690 691 #define CONFIG_RAMBOOTCOMMAND \ 692 "setenv bootargs root=/dev/ram rw " \ 693 "console=$consoledev,$baudrate $othbootargs;" \ 694 "tftp $ramdiskaddr $ramdiskfile;" \ 695 "tftp $loadaddr $bootfile;" \ 696 "tftp $fdtaddr $fdtfile;" \ 697 "bootm $loadaddr $ramdiskaddr $fdtaddr" 698 699 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 700 701 #include <asm/fsl_secure_boot.h> 702 703 #endif /* __CONFIG_H */ 704