1 /* 2 * Copyright 2009-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * Corenet DS style board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #include "../board/freescale/common/ics307_clk.h" 14 15 #ifdef CONFIG_RAMBOOT_PBL 16 #ifdef CONFIG_SECURE_BOOT 17 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 18 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 19 #ifdef CONFIG_NAND 20 #define CONFIG_RAMBOOT_NAND 21 #endif 22 #define CONFIG_BOOTSCRIPT_COPY_RAM 23 #else 24 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 25 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 26 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg 27 #if defined(CONFIG_TARGET_P3041DS) 28 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg 29 #elif defined(CONFIG_TARGET_P4080DS) 30 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg 31 #elif defined(CONFIG_TARGET_P5020DS) 32 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg 33 #elif defined(CONFIG_TARGET_P5040DS) 34 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg 35 #endif 36 #endif 37 #endif 38 39 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 40 /* Set 1M boot space */ 41 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 42 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 43 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 44 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 45 #define CONFIG_SYS_NO_FLASH 46 #endif 47 48 /* High Level Configuration Options */ 49 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 50 #define CONFIG_MP /* support multiple processors */ 51 52 #ifndef CONFIG_SYS_TEXT_BASE 53 #define CONFIG_SYS_TEXT_BASE 0xeff40000 54 #endif 55 56 #ifndef CONFIG_RESET_VECTOR_ADDRESS 57 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 58 #endif 59 60 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 61 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 62 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 63 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 64 #define CONFIG_PCIE1 /* PCIE controller 1 */ 65 #define CONFIG_PCIE2 /* PCIE controller 2 */ 66 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 67 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 68 69 #define CONFIG_ENV_OVERWRITE 70 71 #ifdef CONFIG_SYS_NO_FLASH 72 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) 73 #define CONFIG_ENV_IS_NOWHERE 74 #endif 75 #else 76 #define CONFIG_FLASH_CFI_DRIVER 77 #define CONFIG_SYS_FLASH_CFI 78 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 79 #endif 80 81 #if defined(CONFIG_SPIFLASH) 82 #define CONFIG_SYS_EXTRA_ENV_RELOC 83 #define CONFIG_ENV_IS_IN_SPI_FLASH 84 #define CONFIG_ENV_SPI_BUS 0 85 #define CONFIG_ENV_SPI_CS 0 86 #define CONFIG_ENV_SPI_MAX_HZ 10000000 87 #define CONFIG_ENV_SPI_MODE 0 88 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 89 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 90 #define CONFIG_ENV_SECT_SIZE 0x10000 91 #elif defined(CONFIG_SDCARD) 92 #define CONFIG_SYS_EXTRA_ENV_RELOC 93 #define CONFIG_ENV_IS_IN_MMC 94 #define CONFIG_FSL_FIXED_MMC_LOCATION 95 #define CONFIG_SYS_MMC_ENV_DEV 0 96 #define CONFIG_ENV_SIZE 0x2000 97 #define CONFIG_ENV_OFFSET (512 * 1658) 98 #elif defined(CONFIG_NAND) 99 #define CONFIG_SYS_EXTRA_ENV_RELOC 100 #define CONFIG_ENV_IS_IN_NAND 101 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 102 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 103 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 104 #define CONFIG_ENV_IS_IN_REMOTE 105 #define CONFIG_ENV_ADDR 0xffe20000 106 #define CONFIG_ENV_SIZE 0x2000 107 #elif defined(CONFIG_ENV_IS_NOWHERE) 108 #define CONFIG_ENV_SIZE 0x2000 109 #else 110 #define CONFIG_ENV_IS_IN_FLASH 111 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 112 #define CONFIG_ENV_SIZE 0x2000 113 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 114 #endif 115 116 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 117 118 /* 119 * These can be toggled for performance analysis, otherwise use default. 120 */ 121 #define CONFIG_SYS_CACHE_STASHING 122 #define CONFIG_BACKSIDE_L2_CACHE 123 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 124 #define CONFIG_BTB /* toggle branch predition */ 125 #define CONFIG_DDR_ECC 126 #ifdef CONFIG_DDR_ECC 127 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 128 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 129 #endif 130 131 #define CONFIG_ENABLE_36BIT_PHYS 132 133 #ifdef CONFIG_PHYS_64BIT 134 #define CONFIG_ADDR_MAP 135 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 136 #endif 137 138 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 139 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 140 #define CONFIG_SYS_MEMTEST_END 0x00400000 141 #define CONFIG_SYS_ALT_MEMTEST 142 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 143 144 /* 145 * Config the L3 Cache as L3 SRAM 146 */ 147 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 148 #ifdef CONFIG_PHYS_64BIT 149 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) 150 #else 151 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 152 #endif 153 #define CONFIG_SYS_L3_SIZE (1024 << 10) 154 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 155 156 #ifdef CONFIG_PHYS_64BIT 157 #define CONFIG_SYS_DCSRBAR 0xf0000000 158 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 159 #endif 160 161 /* EEPROM */ 162 #define CONFIG_ID_EEPROM 163 #define CONFIG_SYS_I2C_EEPROM_NXID 164 #define CONFIG_SYS_EEPROM_BUS_NUM 0 165 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 166 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 167 168 /* 169 * DDR Setup 170 */ 171 #define CONFIG_VERY_BIG_RAM 172 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 173 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 174 175 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 176 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 177 178 #define CONFIG_DDR_SPD 179 180 #define CONFIG_SYS_SPD_BUS_NUM 1 181 #define SPD_EEPROM_ADDRESS1 0x51 182 #define SPD_EEPROM_ADDRESS2 0x52 183 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 184 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 185 186 /* 187 * Local Bus Definitions 188 */ 189 190 /* Set the local bus clock 1/8 of platform clock */ 191 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 192 193 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */ 194 #ifdef CONFIG_PHYS_64BIT 195 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 196 #else 197 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 198 #endif 199 200 #define CONFIG_SYS_FLASH_BR_PRELIM \ 201 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \ 202 | BR_PS_16 | BR_V) 203 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 204 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 205 206 #define CONFIG_SYS_BR1_PRELIM \ 207 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 208 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 209 210 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 211 #ifdef CONFIG_PHYS_64BIT 212 #define PIXIS_BASE_PHYS 0xfffdf0000ull 213 #else 214 #define PIXIS_BASE_PHYS PIXIS_BASE 215 #endif 216 217 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 218 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 219 220 #define PIXIS_LBMAP_SWITCH 7 221 #define PIXIS_LBMAP_MASK 0xf0 222 #define PIXIS_LBMAP_SHIFT 4 223 #define PIXIS_LBMAP_ALTBANK 0x40 224 225 #define CONFIG_SYS_FLASH_QUIET_TEST 226 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 227 228 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 229 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 230 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 231 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 232 233 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 234 235 #if defined(CONFIG_RAMBOOT_PBL) 236 #define CONFIG_SYS_RAMBOOT 237 #endif 238 239 /* Nand Flash */ 240 #ifdef CONFIG_NAND_FSL_ELBC 241 #define CONFIG_SYS_NAND_BASE 0xffa00000 242 #ifdef CONFIG_PHYS_64BIT 243 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 244 #else 245 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 246 #endif 247 248 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 249 #define CONFIG_SYS_MAX_NAND_DEVICE 1 250 #define CONFIG_CMD_NAND 251 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 252 253 /* NAND flash config */ 254 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 255 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 256 | BR_PS_8 /* Port Size = 8 bit */ \ 257 | BR_MS_FCM /* MSEL = FCM */ \ 258 | BR_V) /* valid */ 259 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 260 | OR_FCM_PGS /* Large Page*/ \ 261 | OR_FCM_CSCT \ 262 | OR_FCM_CST \ 263 | OR_FCM_CHT \ 264 | OR_FCM_SCY_1 \ 265 | OR_FCM_TRLX \ 266 | OR_FCM_EHTR) 267 268 #ifdef CONFIG_NAND 269 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 270 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 271 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 272 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 273 #else 274 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 275 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 276 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 277 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 278 #endif 279 #else 280 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 281 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 282 #endif /* CONFIG_NAND_FSL_ELBC */ 283 284 #define CONFIG_SYS_FLASH_EMPTY_INFO 285 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 286 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 287 288 #define CONFIG_BOARD_EARLY_INIT_F 289 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 290 #define CONFIG_MISC_INIT_R 291 292 #define CONFIG_HWCONFIG 293 294 /* define to use L1 as initial stack */ 295 #define CONFIG_L1_INIT_RAM 296 #define CONFIG_SYS_INIT_RAM_LOCK 297 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 298 #ifdef CONFIG_PHYS_64BIT 299 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 300 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 301 /* The assembler doesn't like typecast */ 302 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 303 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 304 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 305 #else 306 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ 307 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 308 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 309 #endif 310 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 311 312 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 313 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 314 315 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 316 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 317 318 /* Serial Port - controlled on board with jumper J8 319 * open - index 2 320 * shorted - index 1 321 */ 322 #define CONFIG_CONS_INDEX 1 323 #define CONFIG_SYS_NS16550_SERIAL 324 #define CONFIG_SYS_NS16550_REG_SIZE 1 325 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 326 327 #define CONFIG_SYS_BAUDRATE_TABLE \ 328 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 329 330 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 331 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 332 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 333 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 334 335 /* I2C */ 336 #define CONFIG_SYS_I2C 337 #define CONFIG_SYS_I2C_FSL 338 #define CONFIG_SYS_FSL_I2C_SPEED 400000 339 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 340 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 341 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 342 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 343 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 344 345 /* 346 * RapidIO 347 */ 348 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 349 #ifdef CONFIG_PHYS_64BIT 350 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 351 #else 352 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 353 #endif 354 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 355 356 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 357 #ifdef CONFIG_PHYS_64BIT 358 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 359 #else 360 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 361 #endif 362 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 363 364 /* 365 * for slave u-boot IMAGE instored in master memory space, 366 * PHYS must be aligned based on the SIZE 367 */ 368 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 369 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 370 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 371 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 372 /* 373 * for slave UCODE and ENV instored in master memory space, 374 * PHYS must be aligned based on the SIZE 375 */ 376 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 377 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 378 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 379 380 /* slave core release by master*/ 381 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 382 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 383 384 /* 385 * SRIO_PCIE_BOOT - SLAVE 386 */ 387 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 388 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 389 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 390 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 391 #endif 392 393 /* 394 * eSPI - Enhanced SPI 395 */ 396 #define CONFIG_SF_DEFAULT_SPEED 10000000 397 #define CONFIG_SF_DEFAULT_MODE 0 398 399 /* 400 * General PCI 401 * Memory space is mapped 1-1, but I/O space must start from 0. 402 */ 403 404 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 405 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 406 #ifdef CONFIG_PHYS_64BIT 407 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 408 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 409 #else 410 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 411 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 412 #endif 413 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 414 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 415 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 416 #ifdef CONFIG_PHYS_64BIT 417 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 418 #else 419 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 420 #endif 421 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 422 423 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 424 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 425 #ifdef CONFIG_PHYS_64BIT 426 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 427 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 428 #else 429 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 430 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 431 #endif 432 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 433 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 434 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 435 #ifdef CONFIG_PHYS_64BIT 436 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 437 #else 438 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 439 #endif 440 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 441 442 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 443 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 444 #ifdef CONFIG_PHYS_64BIT 445 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 446 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 447 #else 448 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 449 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 450 #endif 451 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 452 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 453 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 454 #ifdef CONFIG_PHYS_64BIT 455 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 456 #else 457 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 458 #endif 459 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 460 461 /* controller 4, Base address 203000 */ 462 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 463 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 464 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 465 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 466 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 467 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 468 469 /* Qman/Bman */ 470 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 471 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 472 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 473 #ifdef CONFIG_PHYS_64BIT 474 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 475 #else 476 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 477 #endif 478 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 479 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 480 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 481 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 482 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 483 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 484 CONFIG_SYS_BMAN_CENA_SIZE) 485 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 486 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 487 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 488 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 489 #ifdef CONFIG_PHYS_64BIT 490 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 491 #else 492 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 493 #endif 494 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 495 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 496 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 497 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 498 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 499 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 500 CONFIG_SYS_QMAN_CENA_SIZE) 501 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 502 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 503 504 #define CONFIG_SYS_DPAA_FMAN 505 #define CONFIG_SYS_DPAA_PME 506 /* Default address of microcode for the Linux Fman driver */ 507 #if defined(CONFIG_SPIFLASH) 508 /* 509 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 510 * env, so we got 0x110000. 511 */ 512 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 513 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 514 #elif defined(CONFIG_SDCARD) 515 /* 516 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 517 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 518 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 519 */ 520 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 521 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 522 #elif defined(CONFIG_NAND) 523 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 524 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 525 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 526 /* 527 * Slave has no ucode locally, it can fetch this from remote. When implementing 528 * in two corenet boards, slave's ucode could be stored in master's memory 529 * space, the address can be mapped from slave TLB->slave LAW-> 530 * slave SRIO or PCIE outbound window->master inbound window-> 531 * master LAW->the ucode address in master's memory space. 532 */ 533 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 534 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 535 #else 536 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 537 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 538 #endif 539 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 540 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 541 542 #ifdef CONFIG_SYS_DPAA_FMAN 543 #define CONFIG_FMAN_ENET 544 #define CONFIG_PHYLIB_10G 545 #define CONFIG_PHY_VITESSE 546 #define CONFIG_PHY_TERANETICS 547 #endif 548 549 #ifdef CONFIG_PCI 550 #define CONFIG_PCI_INDIRECT_BRIDGE 551 552 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 553 #define CONFIG_DOS_PARTITION 554 #endif /* CONFIG_PCI */ 555 556 /* SATA */ 557 #ifdef CONFIG_FSL_SATA_V2 558 #define CONFIG_LIBATA 559 #define CONFIG_FSL_SATA 560 561 #define CONFIG_SYS_SATA_MAX_DEVICE 2 562 #define CONFIG_SATA1 563 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 564 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 565 #define CONFIG_SATA2 566 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 567 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 568 569 #define CONFIG_LBA48 570 #define CONFIG_CMD_SATA 571 #define CONFIG_DOS_PARTITION 572 #endif 573 574 #ifdef CONFIG_FMAN_ENET 575 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c 576 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d 577 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e 578 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f 579 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 580 581 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c 582 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d 583 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e 584 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f 585 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0 586 587 #define CONFIG_SYS_TBIPA_VALUE 8 588 #define CONFIG_MII /* MII PHY management */ 589 #define CONFIG_ETHPRIME "FM1@DTSEC1" 590 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 591 #endif 592 593 /* 594 * Environment 595 */ 596 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 597 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 598 599 /* 600 * Command line configuration. 601 */ 602 #define CONFIG_CMD_ERRATA 603 #define CONFIG_CMD_IRQ 604 #define CONFIG_CMD_REGINFO 605 606 #ifdef CONFIG_PCI 607 #define CONFIG_CMD_PCI 608 #endif 609 610 /* 611 * USB 612 */ 613 #define CONFIG_HAS_FSL_DR_USB 614 #define CONFIG_HAS_FSL_MPH_USB 615 616 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 617 #define CONFIG_USB_EHCI 618 #define CONFIG_USB_EHCI_FSL 619 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 620 #endif 621 622 #ifdef CONFIG_MMC 623 #define CONFIG_FSL_ESDHC 624 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 625 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 626 #define CONFIG_GENERIC_MMC 627 #define CONFIG_DOS_PARTITION 628 #endif 629 630 /* Hash command with SHA acceleration supported in hardware */ 631 #ifdef CONFIG_FSL_CAAM 632 #define CONFIG_CMD_HASH 633 #define CONFIG_SHA_HW_ACCEL 634 #endif 635 636 /* 637 * Miscellaneous configurable options 638 */ 639 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 640 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 641 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 642 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 643 #ifdef CONFIG_CMD_KGDB 644 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 645 #else 646 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 647 #endif 648 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 649 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 650 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 651 652 /* 653 * For booting Linux, the board info and command line data 654 * have to be in the first 64 MB of memory, since this is 655 * the maximum mapped by the Linux kernel during initialization. 656 */ 657 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 658 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 659 660 #ifdef CONFIG_CMD_KGDB 661 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 662 #endif 663 664 /* 665 * Environment Configuration 666 */ 667 #define CONFIG_ROOTPATH "/opt/nfsroot" 668 #define CONFIG_BOOTFILE "uImage" 669 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 670 671 /* default location for tftp and bootm */ 672 #define CONFIG_LOADADDR 1000000 673 674 675 #define CONFIG_BAUDRATE 115200 676 677 #ifdef CONFIG_TARGET_P4080DS 678 #define __USB_PHY_TYPE ulpi 679 #else 680 #define __USB_PHY_TYPE utmi 681 #endif 682 683 #define CONFIG_EXTRA_ENV_SETTINGS \ 684 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 685 "bank_intlv=cs0_cs1;" \ 686 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 687 "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 688 "netdev=eth0\0" \ 689 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 690 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 691 "tftpflash=tftpboot $loadaddr $uboot && " \ 692 "protect off $ubootaddr +$filesize && " \ 693 "erase $ubootaddr +$filesize && " \ 694 "cp.b $loadaddr $ubootaddr $filesize && " \ 695 "protect on $ubootaddr +$filesize && " \ 696 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 697 "consoledev=ttyS0\0" \ 698 "ramdiskaddr=2000000\0" \ 699 "ramdiskfile=p4080ds/ramdisk.uboot\0" \ 700 "fdtaddr=1e00000\0" \ 701 "fdtfile=p4080ds/p4080ds.dtb\0" \ 702 "bdev=sda3\0" 703 704 #define CONFIG_HDBOOT \ 705 "setenv bootargs root=/dev/$bdev rw " \ 706 "console=$consoledev,$baudrate $othbootargs;" \ 707 "tftp $loadaddr $bootfile;" \ 708 "tftp $fdtaddr $fdtfile;" \ 709 "bootm $loadaddr - $fdtaddr" 710 711 #define CONFIG_NFSBOOTCOMMAND \ 712 "setenv bootargs root=/dev/nfs rw " \ 713 "nfsroot=$serverip:$rootpath " \ 714 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 715 "console=$consoledev,$baudrate $othbootargs;" \ 716 "tftp $loadaddr $bootfile;" \ 717 "tftp $fdtaddr $fdtfile;" \ 718 "bootm $loadaddr - $fdtaddr" 719 720 #define CONFIG_RAMBOOTCOMMAND \ 721 "setenv bootargs root=/dev/ram rw " \ 722 "console=$consoledev,$baudrate $othbootargs;" \ 723 "tftp $ramdiskaddr $ramdiskfile;" \ 724 "tftp $loadaddr $bootfile;" \ 725 "tftp $fdtaddr $fdtfile;" \ 726 "bootm $loadaddr $ramdiskaddr $fdtaddr" 727 728 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 729 730 #include <asm/fsl_secure_boot.h> 731 732 #endif /* __CONFIG_H */ 733