1 /* 2 * Copyright 2009-2010 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * Corenet DS style board configuration file 25 */ 26 #ifndef __CONFIG_H 27 #define __CONFIG_H 28 29 #include "../board/freescale/common/ics307_clk.h" 30 31 /* High Level Configuration Options */ 32 #define CONFIG_BOOKE 33 #define CONFIG_E500 /* BOOKE e500 family */ 34 #define CONFIG_E500MC /* BOOKE e500mc family */ 35 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 36 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ 37 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 38 #define CONFIG_MP /* support multiple processors */ 39 40 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 41 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 42 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 43 #define CONFIG_PCI /* Enable PCI/PCIE */ 44 #define CONFIG_PCIE1 /* PCIE controler 1 */ 45 #define CONFIG_PCIE2 /* PCIE controler 2 */ 46 #define CONFIG_PCIE3 /* PCIE controler 3 */ 47 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 48 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 49 #define CONFIG_SYS_HAS_SERDES /* has SERDES */ 50 51 #define CONFIG_SRIO1 /* SRIO port 1 */ 52 #define CONFIG_SRIO2 /* SRIO port 2 */ 53 54 #define CONFIG_FSL_LAW /* Use common FSL init code */ 55 56 #define CONFIG_ENV_OVERWRITE 57 58 #ifdef CONFIG_SYS_NO_FLASH 59 #define CONFIG_ENV_IS_NOWHERE 60 #else 61 #define CONFIG_ENV_IS_IN_FLASH 62 #define CONFIG_FLASH_CFI_DRIVER 63 #define CONFIG_SYS_FLASH_CFI 64 #endif 65 66 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 67 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 68 69 /* 70 * These can be toggled for performance analysis, otherwise use default. 71 */ 72 #define CONFIG_SYS_CACHE_STASHING 73 #define CONFIG_BACKSIDE_L2_CACHE 74 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 75 #define CONFIG_BTB /* toggle branch predition */ 76 //#define CONFIG_DDR_ECC 77 #ifdef CONFIG_DDR_ECC 78 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 79 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 80 #endif 81 82 #define CONFIG_ENABLE_36BIT_PHYS 83 84 #ifdef CONFIG_PHYS_64BIT 85 #define CONFIG_ADDR_MAP 86 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 87 #endif 88 89 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 90 #define CONFIG_SYS_MEMTEST_END 0x00400000 91 #define CONFIG_SYS_ALT_MEMTEST 92 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 93 94 /* 95 * Base addresses -- Note these are effective addresses where the 96 * actual resources get mapped (not physical addresses) 97 */ 98 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 /* CCSRBAR Default */ 99 #define CONFIG_SYS_CCSRBAR 0xfe000000 /* relocated CCSRBAR */ 100 #ifdef CONFIG_PHYS_64BIT 101 #define CONFIG_SYS_CCSRBAR_PHYS 0xffe000000ull /* physical addr of CCSRBAR */ 102 #else 103 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ 104 #endif 105 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 106 107 #ifdef CONFIG_PHYS_64BIT 108 #define CONFIG_SYS_DCSRBAR 0xf0000000 109 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 110 #endif 111 112 /* EEPROM */ 113 #define CONFIG_ID_EEPROM 114 #define CONFIG_SYS_I2C_EEPROM_NXID 115 #define CONFIG_SYS_EEPROM_BUS_NUM 0 116 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 117 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 118 119 /* 120 * DDR Setup 121 */ 122 #define CONFIG_VERY_BIG_RAM 123 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 124 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 125 126 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 127 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 128 129 #define CONFIG_DDR_SPD 130 #define CONFIG_FSL_DDR3 131 132 #ifdef CONFIG_DDR_SPD 133 #define CONFIG_SYS_SPD_BUS_NUM 1 134 #define SPD_EEPROM_ADDRESS1 0x51 135 #define SPD_EEPROM_ADDRESS2 0x52 136 #else 137 #define CONFIG_SYS_SDRAM_SIZE 4096 138 139 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 140 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f 141 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 142 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202 143 #define CONFIG_SYS_DDR_TIMING_3 0x01031000 144 #define CONFIG_SYS_DDR_TIMING_0 0x55440804 145 #define CONFIG_SYS_DDR_TIMING_1 0x74713a66 146 #define CONFIG_SYS_DDR_TIMING_2 0x0fb8911b 147 #define CONFIG_SYS_DDR_MODE_1 0x00421850 148 #define CONFIG_SYS_DDR_MODE_2 0x00100000 149 #define CONFIG_SYS_DDR_MODE_CTRL 0x00000000 150 #define CONFIG_SYS_DDR_INTERVAL 0x10400100 151 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 152 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 153 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 154 #define CONFIG_SYS_DDR_TIMING_5 0x03401500 155 #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 156 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x8655a608 157 #define CONFIG_SYS_DDR_CONTROL 0xc7048000 158 #define CONFIG_SYS_DDR_CONTROL2 0x24400011 159 #define CONFIG_SYS_DDR_CDR1 0x00000000 160 #define CONFIG_SYS_DDR_CDR2 0x00000000 161 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 162 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 163 #define CONFIG_SYS_DDR_SBE 0x00010000 164 #define CONFIG_SYS_DDR_DEBUG_18 0x40100400 165 166 #define CONFIG_SYS_DDR2_CS0_BNDS 0x008000bf 167 #define CONFIG_SYS_DDR2_CS1_BNDS 0x00C000ff 168 #define CONFIG_SYS_DDR2_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG 169 #define CONFIG_SYS_DDR2_CS1_CONFIG CONFIG_SYS_DDR_CS1_CONFIG 170 #define CONFIG_SYS_DDR2_TIMING_3 CONFIG_SYS_DDR_TIMING_3 171 #define CONFIG_SYS_DDR2_TIMING_0 CONFIG_SYS_DDR_TIMING_0 172 #define CONFIG_SYS_DDR2_TIMING_1 CONFIG_SYS_DDR_TIMING_1 173 #define CONFIG_SYS_DDR2_TIMING_2 CONFIG_SYS_DDR_TIMING_2 174 #define CONFIG_SYS_DDR2_MODE_1 CONFIG_SYS_DDR_MODE_1 175 #define CONFIG_SYS_DDR2_MODE_2 CONFIG_SYS_DDR_MODE_2 176 #define CONFIG_SYS_DDR2_MODE_CTRL CONFIG_SYS_DDR_MODE_CTRL 177 #define CONFIG_SYS_DDR2_INTERVAL CONFIG_SYS_DDR_INTERVAL 178 #define CONFIG_SYS_DDR2_DATA_INIT CONFIG_SYS_DDR_DATA_INIT 179 #define CONFIG_SYS_DDR2_CLK_CTRL CONFIG_SYS_DDR_CLK_CTRL 180 #define CONFIG_SYS_DDR2_TIMING_4 CONFIG_SYS_DDR_TIMING_4 181 #define CONFIG_SYS_DDR2_TIMING_5 CONFIG_SYS_DDR_TIMING_5 182 #define CONFIG_SYS_DDR2_ZQ_CNTL CONFIG_SYS_DDR_ZQ_CNTL 183 #define CONFIG_SYS_DDR2_WRLVL_CNTL CONFIG_SYS_DDR_WRLVL_CNTL 184 #define CONFIG_SYS_DDR2_CONTROL CONFIG_SYS_DDR_CONTROL 185 #define CONFIG_SYS_DDR2_CONTROL2 CONFIG_SYS_DDR_CONTROL2 186 #define CONFIG_SYS_DDR2_CDR1 CONFIG_SYS_DDR_CDR1 187 #define CONFIG_SYS_DDR2_CDR2 CONFIG_SYS_DDR_CDR2 188 #define CONFIG_SYS_DDR2_ERR_INT_EN CONFIG_SYS_DDR_ERR_INT_EN 189 #define CONFIG_SYS_DDR2_ERR_DIS CONFIG_SYS_DDR_ERR_DIS 190 #define CONFIG_SYS_DDR2_SBE CONFIG_SYS_DDR_SBE 191 #define CONFIG_SYS_DDR2_DEBUG_18 CONFIG_SYS_DDR_DEBUG_18 192 193 #endif 194 195 /* 196 * Local Bus Definitions 197 */ 198 199 /* Set the local bus clock 1/8 of platform clock */ 200 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 201 202 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */ 203 #ifdef CONFIG_PHYS_64BIT 204 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 205 #else 206 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 207 #endif 208 209 #define CONFIG_SYS_BR0_PRELIM \ 210 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \ 211 BR_PS_16 | BR_V) 212 #define CONFIG_SYS_OR0_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 213 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 214 215 #define CONFIG_SYS_BR1_PRELIM \ 216 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 217 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 218 219 #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ 220 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 221 #ifdef CONFIG_PHYS_64BIT 222 #define PIXIS_BASE_PHYS 0xfffdf0000ull 223 #else 224 #define PIXIS_BASE_PHYS PIXIS_BASE 225 #endif 226 227 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 228 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 229 230 #define PIXIS_LBMAP_SWITCH 7 231 #define PIXIS_LBMAP_MASK 0xf0 232 #define PIXIS_LBMAP_SHIFT 4 233 #define PIXIS_LBMAP_ALTBANK 0x40 234 235 #define CONFIG_SYS_FLASH_QUIET_TEST 236 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 237 238 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 239 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 240 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 241 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 242 243 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 244 245 #define CONFIG_SYS_FLASH_EMPTY_INFO 246 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 247 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 248 249 #define CONFIG_BOARD_EARLY_INIT_F 250 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 251 #define CONFIG_MISC_INIT_R 252 253 #define CONFIG_HWCONFIG 254 255 /* define to use L1 as initial stack */ 256 #define CONFIG_L1_INIT_RAM 257 #define CONFIG_SYS_INIT_RAM_LOCK 258 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 259 #ifdef CONFIG_PHYS_64BIT 260 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 261 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 262 /* The assembler doesn't like typecast */ 263 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 264 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 265 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 266 #else 267 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ 268 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 269 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 270 #endif 271 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ 272 273 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 274 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 275 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 276 277 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 278 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 279 280 /* Serial Port - controlled on board with jumper J8 281 * open - index 2 282 * shorted - index 1 283 */ 284 #define CONFIG_CONS_INDEX 1 285 #define CONFIG_SYS_NS16550 286 #define CONFIG_SYS_NS16550_SERIAL 287 #define CONFIG_SYS_NS16550_REG_SIZE 1 288 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 289 290 #define CONFIG_SYS_BAUDRATE_TABLE \ 291 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 292 293 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 294 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 295 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 296 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 297 298 /* Use the HUSH parser */ 299 #define CONFIG_SYS_HUSH_PARSER 300 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 301 302 /* pass open firmware flat tree */ 303 #define CONFIG_OF_LIBFDT 304 #define CONFIG_OF_BOARD_SETUP 305 #define CONFIG_OF_STDOUT_VIA_ALIAS 306 307 /* new uImage format support */ 308 #define CONFIG_FIT 309 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 310 311 /* I2C */ 312 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 313 #define CONFIG_HARD_I2C /* I2C with hardware support */ 314 #define CONFIG_I2C_MULTI_BUS 315 #define CONFIG_I2C_CMD_TREE 316 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 317 #define CONFIG_SYS_I2C_SLAVE 0x7F 318 #define CONFIG_SYS_I2C_OFFSET 0x118000 319 #define CONFIG_SYS_I2C2_OFFSET 0x118100 320 321 /* 322 * RapidIO 323 */ 324 #define CONFIG_SYS_RIO1_MEM_VIRT 0xa0000000 325 #ifdef CONFIG_PHYS_64BIT 326 #define CONFIG_SYS_RIO1_MEM_PHYS 0xc20000000ull 327 #else 328 #define CONFIG_SYS_RIO1_MEM_PHYS 0xa0000000 329 #endif 330 #define CONFIG_SYS_RIO1_MEM_SIZE 0x10000000 /* 256M */ 331 332 #define CONFIG_SYS_RIO2_MEM_VIRT 0xb0000000 333 #ifdef CONFIG_PHYS_64BIT 334 #define CONFIG_SYS_RIO2_MEM_PHYS 0xc30000000ull 335 #else 336 #define CONFIG_SYS_RIO2_MEM_PHYS 0xb0000000 337 #endif 338 #define CONFIG_SYS_RIO2_MEM_SIZE 0x10000000 /* 256M */ 339 340 /* 341 * General PCI 342 * Memory space is mapped 1-1, but I/O space must start from 0. 343 */ 344 345 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 346 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 347 #ifdef CONFIG_PHYS_64BIT 348 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 349 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 350 #else 351 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 352 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 353 #endif 354 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 355 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 356 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 357 #ifdef CONFIG_PHYS_64BIT 358 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 359 #else 360 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 361 #endif 362 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 363 364 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 365 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 366 #ifdef CONFIG_PHYS_64BIT 367 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 368 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 369 #else 370 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 371 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 372 #endif 373 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 374 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 375 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 376 #ifdef CONFIG_PHYS_64BIT 377 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 378 #else 379 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 380 #endif 381 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 382 383 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 384 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xe0000000 385 #ifdef CONFIG_PHYS_64BIT 386 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 387 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 388 #else 389 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 390 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 391 #endif 392 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 393 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 394 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 395 #ifdef CONFIG_PHYS_64BIT 396 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 397 #else 398 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 399 #endif 400 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 401 402 /* Qman/Bman */ 403 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 404 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 405 #ifdef CONFIG_PHYS_64BIT 406 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 407 #else 408 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 409 #endif 410 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 411 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 412 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 413 #ifdef CONFIG_PHYS_64BIT 414 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 415 #else 416 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 417 #endif 418 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 419 420 #define CONFIG_SYS_DPAA_FMAN 421 #define CONFIG_SYS_DPAA_PME 422 /* Default address of microcode for the Linux Fman driver */ 423 #define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000 424 #ifdef CONFIG_PHYS_64BIT 425 #define CONFIG_SYS_FMAN_FW_ADDR_PHYS 0xFEF000000ULL 426 #else 427 #define CONFIG_SYS_FMAN_FW_ADDR_PHYS CONFIG_SYS_FMAN_FW_ADDR 428 #endif 429 430 #ifdef CONFIG_SYS_DPAA_FMAN 431 #define CONFIG_FMAN_ENET 432 #endif 433 434 #ifdef CONFIG_PCI 435 436 /*PCIE video card used*/ 437 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 438 439 /* video */ 440 #define CONFIG_VIDEO 441 442 #ifdef CONFIG_VIDEO 443 #define CONFIG_BIOSEMU 444 #define CONFIG_CFB_CONSOLE 445 #define CONFIG_VIDEO_SW_CURSOR 446 #define CONFIG_VGA_AS_SINGLE_DEVICE 447 #define CONFIG_ATI_RADEON_FB 448 #define CONFIG_VIDEO_LOGO 449 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 450 #endif 451 452 #define CONFIG_NET_MULTI 453 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 454 #define CONFIG_E1000 455 456 #ifndef CONFIG_PCI_PNP 457 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS 458 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS 459 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 460 #endif 461 462 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 463 #define CONFIG_DOS_PARTITION 464 #endif /* CONFIG_PCI */ 465 466 /* SATA */ 467 #ifdef CONFIG_FSL_SATA_V2 468 #define CONFIG_LIBATA 469 #define CONFIG_FSL_SATA 470 471 #define CONFIG_SYS_SATA_MAX_DEVICE 2 472 #define CONFIG_SATA1 473 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 474 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 475 #define CONFIG_SATA2 476 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 477 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 478 479 #define CONFIG_LBA48 480 #define CONFIG_CMD_SATA 481 #define CONFIG_DOS_PARTITION 482 #define CONFIG_CMD_EXT2 483 #endif 484 485 #ifdef CONFIG_FMAN_ENET 486 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c 487 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d 488 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e 489 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f 490 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 491 492 #if (CONFIG_SYS_NUM_FMAN == 2) 493 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c 494 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d 495 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e 496 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f 497 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0 498 #endif 499 500 #define CONFIG_SYS_TBIPA_VALUE 8 501 #define CONFIG_MII /* MII PHY management */ 502 #define CONFIG_ETHPRIME "FM1@DTSEC1" 503 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 504 #endif 505 506 /* 507 * Environment 508 */ 509 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 510 #define CONFIG_ENV_SIZE 0x2000 511 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 512 513 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 514 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 515 516 /* 517 * Command line configuration. 518 */ 519 #include <config_cmd_default.h> 520 521 #define CONFIG_CMD_ELF 522 #define CONFIG_CMD_ERRATA 523 #define CONFIG_CMD_IRQ 524 #define CONFIG_CMD_I2C 525 #define CONFIG_CMD_MII 526 #define CONFIG_CMD_PING 527 #define CONFIG_CMD_SETEXPR 528 529 #ifdef CONFIG_PCI 530 #define CONFIG_CMD_PCI 531 #define CONFIG_CMD_NET 532 #endif 533 534 /* 535 * USB 536 */ 537 #define CONFIG_CMD_USB 538 #define CONFIG_USB_STORAGE 539 #define CONFIG_USB_EHCI 540 #define CONFIG_USB_EHCI_FSL 541 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 542 #define CONFIG_CMD_EXT2 543 544 #define CONFIG_MMC 545 546 #ifdef CONFIG_MMC 547 #define CONFIG_FSL_ESDHC 548 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 549 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 550 #define CONFIG_CMD_MMC 551 #define CONFIG_GENERIC_MMC 552 #define CONFIG_CMD_EXT2 553 #define CONFIG_CMD_FAT 554 #define CONFIG_DOS_PARTITION 555 #endif 556 557 /* 558 * Miscellaneous configurable options 559 */ 560 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 561 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 562 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 563 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 564 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 565 #ifdef CONFIG_CMD_KGDB 566 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 567 #else 568 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 569 #endif 570 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 571 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 572 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 573 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 574 575 /* 576 * For booting Linux, the board info and command line data 577 * have to be in the first 16 MB of memory, since this is 578 * the maximum mapped by the Linux kernel during initialization. 579 */ 580 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 581 582 /* 583 * Internal Definitions 584 * 585 * Boot Flags 586 */ 587 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 588 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 589 590 #ifdef CONFIG_CMD_KGDB 591 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 592 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 593 #endif 594 595 /* 596 * Environment Configuration 597 */ 598 #define CONFIG_ROOTPATH /opt/nfsroot 599 #define CONFIG_BOOTFILE uImage 600 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 601 602 /* default location for tftp and bootm */ 603 #define CONFIG_LOADADDR 1000000 604 605 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 606 607 #define CONFIG_BAUDRATE 115200 608 609 #define CONFIG_EXTRA_ENV_SETTINGS \ 610 "netdev=eth0\0" \ 611 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 612 "tftpflash=tftpboot $loadaddr $uboot; " \ 613 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 614 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 615 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 616 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 617 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 618 "consoledev=ttyS0\0" \ 619 "ramdiskaddr=2000000\0" \ 620 "ramdiskfile=p4080ds/ramdisk.uboot\0" \ 621 "fdtaddr=c00000\0" \ 622 "fdtfile=p4080ds/p4080ds.dtb\0" \ 623 "bdev=sda3\0" \ 624 "c=ffe\0" \ 625 "fman_ucode="MK_STR(CONFIG_SYS_FMAN_FW_ADDR_PHYS)"\0" 626 627 #define CONFIG_HDBOOT \ 628 "setenv bootargs root=/dev/$bdev rw " \ 629 "console=$consoledev,$baudrate $othbootargs;" \ 630 "tftp $loadaddr $bootfile;" \ 631 "tftp $fdtaddr $fdtfile;" \ 632 "bootm $loadaddr - $fdtaddr" 633 634 #define CONFIG_NFSBOOTCOMMAND \ 635 "setenv bootargs root=/dev/nfs rw " \ 636 "nfsroot=$serverip:$rootpath " \ 637 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 638 "console=$consoledev,$baudrate $othbootargs;" \ 639 "tftp $loadaddr $bootfile;" \ 640 "tftp $fdtaddr $fdtfile;" \ 641 "bootm $loadaddr - $fdtaddr" 642 643 #define CONFIG_RAMBOOTCOMMAND \ 644 "setenv bootargs root=/dev/ram rw " \ 645 "console=$consoledev,$baudrate $othbootargs;" \ 646 "tftp $ramdiskaddr $ramdiskfile;" \ 647 "tftp $loadaddr $bootfile;" \ 648 "tftp $fdtaddr $fdtfile;" \ 649 "bootm $loadaddr $ramdiskaddr $fdtaddr" 650 651 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 652 653 #endif /* __CONFIG_H */ 654