1 /* 2 * Copyright 2009-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * Corenet DS style board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #include "../board/freescale/common/ics307_clk.h" 14 15 #ifdef CONFIG_RAMBOOT_PBL 16 #ifdef CONFIG_SECURE_BOOT 17 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 18 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 19 #ifdef CONFIG_NAND 20 #define CONFIG_RAMBOOT_NAND 21 #endif 22 #define CONFIG_BOOTSCRIPT_COPY_RAM 23 #else 24 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 25 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 26 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg 27 #if defined(CONFIG_TARGET_P3041DS) 28 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg 29 #elif defined(CONFIG_TARGET_P4080DS) 30 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg 31 #elif defined(CONFIG_TARGET_P5020DS) 32 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg 33 #elif defined(CONFIG_TARGET_P5040DS) 34 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg 35 #endif 36 #endif 37 #endif 38 39 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 40 /* Set 1M boot space */ 41 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 42 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 43 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 44 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 45 #endif 46 47 /* High Level Configuration Options */ 48 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 49 #define CONFIG_MP /* support multiple processors */ 50 51 #ifndef CONFIG_SYS_TEXT_BASE 52 #define CONFIG_SYS_TEXT_BASE 0xeff40000 53 #endif 54 55 #ifndef CONFIG_RESET_VECTOR_ADDRESS 56 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 57 #endif 58 59 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 60 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 61 #define CONFIG_PCIE1 /* PCIE controller 1 */ 62 #define CONFIG_PCIE2 /* PCIE controller 2 */ 63 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 64 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 65 66 #define CONFIG_ENV_OVERWRITE 67 68 #ifndef CONFIG_MTD_NOR_FLASH 69 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) 70 #define CONFIG_ENV_IS_NOWHERE 71 #endif 72 #else 73 #define CONFIG_FLASH_CFI_DRIVER 74 #define CONFIG_SYS_FLASH_CFI 75 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 76 #endif 77 78 #if defined(CONFIG_SPIFLASH) 79 #define CONFIG_SYS_EXTRA_ENV_RELOC 80 #define CONFIG_ENV_IS_IN_SPI_FLASH 81 #define CONFIG_ENV_SPI_BUS 0 82 #define CONFIG_ENV_SPI_CS 0 83 #define CONFIG_ENV_SPI_MAX_HZ 10000000 84 #define CONFIG_ENV_SPI_MODE 0 85 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 86 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 87 #define CONFIG_ENV_SECT_SIZE 0x10000 88 #elif defined(CONFIG_SDCARD) 89 #define CONFIG_SYS_EXTRA_ENV_RELOC 90 #define CONFIG_ENV_IS_IN_MMC 91 #define CONFIG_FSL_FIXED_MMC_LOCATION 92 #define CONFIG_SYS_MMC_ENV_DEV 0 93 #define CONFIG_ENV_SIZE 0x2000 94 #define CONFIG_ENV_OFFSET (512 * 1658) 95 #elif defined(CONFIG_NAND) 96 #define CONFIG_SYS_EXTRA_ENV_RELOC 97 #define CONFIG_ENV_IS_IN_NAND 98 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 99 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 100 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 101 #define CONFIG_ENV_IS_IN_REMOTE 102 #define CONFIG_ENV_ADDR 0xffe20000 103 #define CONFIG_ENV_SIZE 0x2000 104 #elif defined(CONFIG_ENV_IS_NOWHERE) 105 #define CONFIG_ENV_SIZE 0x2000 106 #else 107 #define CONFIG_ENV_IS_IN_FLASH 108 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 109 #define CONFIG_ENV_SIZE 0x2000 110 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 111 #endif 112 113 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 114 115 /* 116 * These can be toggled for performance analysis, otherwise use default. 117 */ 118 #define CONFIG_SYS_CACHE_STASHING 119 #define CONFIG_BACKSIDE_L2_CACHE 120 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 121 #define CONFIG_BTB /* toggle branch predition */ 122 #define CONFIG_DDR_ECC 123 #ifdef CONFIG_DDR_ECC 124 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 125 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 126 #endif 127 128 #define CONFIG_ENABLE_36BIT_PHYS 129 130 #ifdef CONFIG_PHYS_64BIT 131 #define CONFIG_ADDR_MAP 132 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 133 #endif 134 135 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 136 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 137 #define CONFIG_SYS_MEMTEST_END 0x00400000 138 #define CONFIG_SYS_ALT_MEMTEST 139 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 140 141 /* 142 * Config the L3 Cache as L3 SRAM 143 */ 144 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 145 #ifdef CONFIG_PHYS_64BIT 146 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) 147 #else 148 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 149 #endif 150 #define CONFIG_SYS_L3_SIZE (1024 << 10) 151 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 152 153 #ifdef CONFIG_PHYS_64BIT 154 #define CONFIG_SYS_DCSRBAR 0xf0000000 155 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 156 #endif 157 158 /* EEPROM */ 159 #define CONFIG_ID_EEPROM 160 #define CONFIG_SYS_I2C_EEPROM_NXID 161 #define CONFIG_SYS_EEPROM_BUS_NUM 0 162 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 163 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 164 165 /* 166 * DDR Setup 167 */ 168 #define CONFIG_VERY_BIG_RAM 169 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 170 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 171 172 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 173 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 174 175 #define CONFIG_DDR_SPD 176 177 #define CONFIG_SYS_SPD_BUS_NUM 1 178 #define SPD_EEPROM_ADDRESS1 0x51 179 #define SPD_EEPROM_ADDRESS2 0x52 180 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 181 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 182 183 /* 184 * Local Bus Definitions 185 */ 186 187 /* Set the local bus clock 1/8 of platform clock */ 188 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 189 190 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */ 191 #ifdef CONFIG_PHYS_64BIT 192 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 193 #else 194 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 195 #endif 196 197 #define CONFIG_SYS_FLASH_BR_PRELIM \ 198 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \ 199 | BR_PS_16 | BR_V) 200 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 201 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 202 203 #define CONFIG_SYS_BR1_PRELIM \ 204 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 205 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 206 207 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 208 #ifdef CONFIG_PHYS_64BIT 209 #define PIXIS_BASE_PHYS 0xfffdf0000ull 210 #else 211 #define PIXIS_BASE_PHYS PIXIS_BASE 212 #endif 213 214 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 215 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 216 217 #define PIXIS_LBMAP_SWITCH 7 218 #define PIXIS_LBMAP_MASK 0xf0 219 #define PIXIS_LBMAP_SHIFT 4 220 #define PIXIS_LBMAP_ALTBANK 0x40 221 222 #define CONFIG_SYS_FLASH_QUIET_TEST 223 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 224 225 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 226 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 227 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 228 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 229 230 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 231 232 #if defined(CONFIG_RAMBOOT_PBL) 233 #define CONFIG_SYS_RAMBOOT 234 #endif 235 236 /* Nand Flash */ 237 #ifdef CONFIG_NAND_FSL_ELBC 238 #define CONFIG_SYS_NAND_BASE 0xffa00000 239 #ifdef CONFIG_PHYS_64BIT 240 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 241 #else 242 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 243 #endif 244 245 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 246 #define CONFIG_SYS_MAX_NAND_DEVICE 1 247 #define CONFIG_CMD_NAND 248 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 249 250 /* NAND flash config */ 251 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 252 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 253 | BR_PS_8 /* Port Size = 8 bit */ \ 254 | BR_MS_FCM /* MSEL = FCM */ \ 255 | BR_V) /* valid */ 256 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 257 | OR_FCM_PGS /* Large Page*/ \ 258 | OR_FCM_CSCT \ 259 | OR_FCM_CST \ 260 | OR_FCM_CHT \ 261 | OR_FCM_SCY_1 \ 262 | OR_FCM_TRLX \ 263 | OR_FCM_EHTR) 264 265 #ifdef CONFIG_NAND 266 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 267 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 268 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 269 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 270 #else 271 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 272 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 273 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 274 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 275 #endif 276 #else 277 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 278 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 279 #endif /* CONFIG_NAND_FSL_ELBC */ 280 281 #define CONFIG_SYS_FLASH_EMPTY_INFO 282 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 283 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 284 285 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 286 #define CONFIG_MISC_INIT_R 287 288 #define CONFIG_HWCONFIG 289 290 /* define to use L1 as initial stack */ 291 #define CONFIG_L1_INIT_RAM 292 #define CONFIG_SYS_INIT_RAM_LOCK 293 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 294 #ifdef CONFIG_PHYS_64BIT 295 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 296 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 297 /* The assembler doesn't like typecast */ 298 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 299 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 300 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 301 #else 302 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ 303 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 304 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 305 #endif 306 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 307 308 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 309 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 310 311 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 312 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 313 314 /* Serial Port - controlled on board with jumper J8 315 * open - index 2 316 * shorted - index 1 317 */ 318 #define CONFIG_CONS_INDEX 1 319 #define CONFIG_SYS_NS16550_SERIAL 320 #define CONFIG_SYS_NS16550_REG_SIZE 1 321 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 322 323 #define CONFIG_SYS_BAUDRATE_TABLE \ 324 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 325 326 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 327 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 328 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 329 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 330 331 /* I2C */ 332 #define CONFIG_SYS_I2C 333 #define CONFIG_SYS_I2C_FSL 334 #define CONFIG_SYS_FSL_I2C_SPEED 400000 335 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 336 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 337 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 338 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 339 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 340 341 /* 342 * RapidIO 343 */ 344 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 345 #ifdef CONFIG_PHYS_64BIT 346 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 347 #else 348 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 349 #endif 350 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 351 352 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 353 #ifdef CONFIG_PHYS_64BIT 354 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 355 #else 356 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 357 #endif 358 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 359 360 /* 361 * for slave u-boot IMAGE instored in master memory space, 362 * PHYS must be aligned based on the SIZE 363 */ 364 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 365 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 366 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 367 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 368 /* 369 * for slave UCODE and ENV instored in master memory space, 370 * PHYS must be aligned based on the SIZE 371 */ 372 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 373 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 374 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 375 376 /* slave core release by master*/ 377 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 378 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 379 380 /* 381 * SRIO_PCIE_BOOT - SLAVE 382 */ 383 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 384 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 385 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 386 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 387 #endif 388 389 /* 390 * eSPI - Enhanced SPI 391 */ 392 #define CONFIG_SF_DEFAULT_SPEED 10000000 393 #define CONFIG_SF_DEFAULT_MODE 0 394 395 /* 396 * General PCI 397 * Memory space is mapped 1-1, but I/O space must start from 0. 398 */ 399 400 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 401 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 402 #ifdef CONFIG_PHYS_64BIT 403 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 404 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 405 #else 406 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 407 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 408 #endif 409 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 410 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 411 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 412 #ifdef CONFIG_PHYS_64BIT 413 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 414 #else 415 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 416 #endif 417 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 418 419 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 420 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 421 #ifdef CONFIG_PHYS_64BIT 422 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 423 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 424 #else 425 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 426 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 427 #endif 428 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 429 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 430 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 431 #ifdef CONFIG_PHYS_64BIT 432 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 433 #else 434 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 435 #endif 436 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 437 438 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 439 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 440 #ifdef CONFIG_PHYS_64BIT 441 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 442 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 443 #else 444 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 445 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 446 #endif 447 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 448 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 449 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 450 #ifdef CONFIG_PHYS_64BIT 451 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 452 #else 453 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 454 #endif 455 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 456 457 /* controller 4, Base address 203000 */ 458 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 459 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 460 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 461 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 462 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 463 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 464 465 /* Qman/Bman */ 466 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 467 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 468 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 469 #ifdef CONFIG_PHYS_64BIT 470 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 471 #else 472 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 473 #endif 474 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 475 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 476 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 477 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 478 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 479 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 480 CONFIG_SYS_BMAN_CENA_SIZE) 481 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 482 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 483 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 484 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 485 #ifdef CONFIG_PHYS_64BIT 486 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 487 #else 488 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 489 #endif 490 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 491 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 492 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 493 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 494 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 495 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 496 CONFIG_SYS_QMAN_CENA_SIZE) 497 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 498 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 499 500 #define CONFIG_SYS_DPAA_FMAN 501 #define CONFIG_SYS_DPAA_PME 502 /* Default address of microcode for the Linux Fman driver */ 503 #if defined(CONFIG_SPIFLASH) 504 /* 505 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 506 * env, so we got 0x110000. 507 */ 508 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 509 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 510 #elif defined(CONFIG_SDCARD) 511 /* 512 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 513 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 514 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 515 */ 516 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 517 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 518 #elif defined(CONFIG_NAND) 519 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 520 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 521 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 522 /* 523 * Slave has no ucode locally, it can fetch this from remote. When implementing 524 * in two corenet boards, slave's ucode could be stored in master's memory 525 * space, the address can be mapped from slave TLB->slave LAW-> 526 * slave SRIO or PCIE outbound window->master inbound window-> 527 * master LAW->the ucode address in master's memory space. 528 */ 529 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 530 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 531 #else 532 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 533 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 534 #endif 535 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 536 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 537 538 #ifdef CONFIG_SYS_DPAA_FMAN 539 #define CONFIG_FMAN_ENET 540 #define CONFIG_PHYLIB_10G 541 #define CONFIG_PHY_VITESSE 542 #define CONFIG_PHY_TERANETICS 543 #endif 544 545 #ifdef CONFIG_PCI 546 #define CONFIG_PCI_INDIRECT_BRIDGE 547 548 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 549 #endif /* CONFIG_PCI */ 550 551 /* SATA */ 552 #ifdef CONFIG_FSL_SATA_V2 553 #define CONFIG_LIBATA 554 #define CONFIG_FSL_SATA 555 556 #define CONFIG_SYS_SATA_MAX_DEVICE 2 557 #define CONFIG_SATA1 558 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 559 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 560 #define CONFIG_SATA2 561 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 562 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 563 564 #define CONFIG_LBA48 565 #define CONFIG_CMD_SATA 566 #endif 567 568 #ifdef CONFIG_FMAN_ENET 569 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c 570 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d 571 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e 572 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f 573 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 574 575 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c 576 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d 577 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e 578 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f 579 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0 580 581 #define CONFIG_SYS_TBIPA_VALUE 8 582 #define CONFIG_MII /* MII PHY management */ 583 #define CONFIG_ETHPRIME "FM1@DTSEC1" 584 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 585 #endif 586 587 /* 588 * Environment 589 */ 590 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 591 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 592 593 /* 594 * Command line configuration. 595 */ 596 #define CONFIG_CMD_ERRATA 597 #define CONFIG_CMD_IRQ 598 #define CONFIG_CMD_REGINFO 599 600 #ifdef CONFIG_PCI 601 #define CONFIG_CMD_PCI 602 #endif 603 604 /* 605 * USB 606 */ 607 #define CONFIG_HAS_FSL_DR_USB 608 #define CONFIG_HAS_FSL_MPH_USB 609 610 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 611 #define CONFIG_USB_EHCI 612 #define CONFIG_USB_EHCI_FSL 613 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 614 #endif 615 616 #ifdef CONFIG_MMC 617 #define CONFIG_FSL_ESDHC 618 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 619 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 620 #endif 621 622 /* Hash command with SHA acceleration supported in hardware */ 623 #ifdef CONFIG_FSL_CAAM 624 #define CONFIG_CMD_HASH 625 #define CONFIG_SHA_HW_ACCEL 626 #endif 627 628 /* 629 * Miscellaneous configurable options 630 */ 631 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 632 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 633 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 634 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 635 #ifdef CONFIG_CMD_KGDB 636 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 637 #else 638 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 639 #endif 640 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 641 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 642 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 643 644 /* 645 * For booting Linux, the board info and command line data 646 * have to be in the first 64 MB of memory, since this is 647 * the maximum mapped by the Linux kernel during initialization. 648 */ 649 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 650 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 651 652 #ifdef CONFIG_CMD_KGDB 653 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 654 #endif 655 656 /* 657 * Environment Configuration 658 */ 659 #define CONFIG_ROOTPATH "/opt/nfsroot" 660 #define CONFIG_BOOTFILE "uImage" 661 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 662 663 /* default location for tftp and bootm */ 664 #define CONFIG_LOADADDR 1000000 665 666 #ifdef CONFIG_TARGET_P4080DS 667 #define __USB_PHY_TYPE ulpi 668 #else 669 #define __USB_PHY_TYPE utmi 670 #endif 671 672 #define CONFIG_EXTRA_ENV_SETTINGS \ 673 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 674 "bank_intlv=cs0_cs1;" \ 675 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 676 "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 677 "netdev=eth0\0" \ 678 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 679 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 680 "tftpflash=tftpboot $loadaddr $uboot && " \ 681 "protect off $ubootaddr +$filesize && " \ 682 "erase $ubootaddr +$filesize && " \ 683 "cp.b $loadaddr $ubootaddr $filesize && " \ 684 "protect on $ubootaddr +$filesize && " \ 685 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 686 "consoledev=ttyS0\0" \ 687 "ramdiskaddr=2000000\0" \ 688 "ramdiskfile=p4080ds/ramdisk.uboot\0" \ 689 "fdtaddr=1e00000\0" \ 690 "fdtfile=p4080ds/p4080ds.dtb\0" \ 691 "bdev=sda3\0" 692 693 #define CONFIG_HDBOOT \ 694 "setenv bootargs root=/dev/$bdev rw " \ 695 "console=$consoledev,$baudrate $othbootargs;" \ 696 "tftp $loadaddr $bootfile;" \ 697 "tftp $fdtaddr $fdtfile;" \ 698 "bootm $loadaddr - $fdtaddr" 699 700 #define CONFIG_NFSBOOTCOMMAND \ 701 "setenv bootargs root=/dev/nfs rw " \ 702 "nfsroot=$serverip:$rootpath " \ 703 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 704 "console=$consoledev,$baudrate $othbootargs;" \ 705 "tftp $loadaddr $bootfile;" \ 706 "tftp $fdtaddr $fdtfile;" \ 707 "bootm $loadaddr - $fdtaddr" 708 709 #define CONFIG_RAMBOOTCOMMAND \ 710 "setenv bootargs root=/dev/ram rw " \ 711 "console=$consoledev,$baudrate $othbootargs;" \ 712 "tftp $ramdiskaddr $ramdiskfile;" \ 713 "tftp $loadaddr $bootfile;" \ 714 "tftp $fdtaddr $fdtfile;" \ 715 "bootm $loadaddr $ramdiskaddr $fdtaddr" 716 717 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 718 719 #include <asm/fsl_secure_boot.h> 720 721 #endif /* __CONFIG_H */ 722