1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2009-2012 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * Corenet DS style board configuration file 8 */ 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include "../board/freescale/common/ics307_clk.h" 13 14 #ifdef CONFIG_RAMBOOT_PBL 15 #ifdef CONFIG_SECURE_BOOT 16 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 17 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 18 #ifdef CONFIG_NAND 19 #define CONFIG_RAMBOOT_NAND 20 #endif 21 #define CONFIG_BOOTSCRIPT_COPY_RAM 22 #else 23 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 24 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 25 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg 26 #if defined(CONFIG_TARGET_P3041DS) 27 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg 28 #elif defined(CONFIG_TARGET_P4080DS) 29 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg 30 #elif defined(CONFIG_TARGET_P5020DS) 31 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg 32 #elif defined(CONFIG_TARGET_P5040DS) 33 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg 34 #endif 35 #endif 36 #endif 37 38 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 39 /* Set 1M boot space */ 40 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 41 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 42 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 43 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 44 #endif 45 46 /* High Level Configuration Options */ 47 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 48 49 #ifndef CONFIG_RESET_VECTOR_ADDRESS 50 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 51 #endif 52 53 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 54 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 55 #define CONFIG_PCIE1 /* PCIE controller 1 */ 56 #define CONFIG_PCIE2 /* PCIE controller 2 */ 57 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 58 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 59 60 #define CONFIG_ENV_OVERWRITE 61 62 #if defined(CONFIG_SPIFLASH) 63 #define CONFIG_ENV_SPI_BUS 0 64 #define CONFIG_ENV_SPI_CS 0 65 #define CONFIG_ENV_SPI_MAX_HZ 10000000 66 #define CONFIG_ENV_SPI_MODE 0 67 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 68 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 69 #define CONFIG_ENV_SECT_SIZE 0x10000 70 #elif defined(CONFIG_SDCARD) 71 #define CONFIG_FSL_FIXED_MMC_LOCATION 72 #define CONFIG_SYS_MMC_ENV_DEV 0 73 #define CONFIG_ENV_SIZE 0x2000 74 #define CONFIG_ENV_OFFSET (512 * 1658) 75 #elif defined(CONFIG_NAND) 76 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 77 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 78 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 79 #define CONFIG_ENV_ADDR 0xffe20000 80 #define CONFIG_ENV_SIZE 0x2000 81 #elif defined(CONFIG_ENV_IS_NOWHERE) 82 #define CONFIG_ENV_SIZE 0x2000 83 #else 84 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 85 #define CONFIG_ENV_SIZE 0x2000 86 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 87 #endif 88 89 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 90 91 /* 92 * These can be toggled for performance analysis, otherwise use default. 93 */ 94 #define CONFIG_SYS_CACHE_STASHING 95 #define CONFIG_BACKSIDE_L2_CACHE 96 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 97 #define CONFIG_BTB /* toggle branch predition */ 98 #define CONFIG_DDR_ECC 99 #ifdef CONFIG_DDR_ECC 100 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 101 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 102 #endif 103 104 #define CONFIG_ENABLE_36BIT_PHYS 105 106 #ifdef CONFIG_PHYS_64BIT 107 #define CONFIG_ADDR_MAP 108 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 109 #endif 110 111 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 112 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 113 #define CONFIG_SYS_MEMTEST_END 0x00400000 114 115 /* 116 * Config the L3 Cache as L3 SRAM 117 */ 118 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 119 #ifdef CONFIG_PHYS_64BIT 120 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) 121 #else 122 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 123 #endif 124 #define CONFIG_SYS_L3_SIZE (1024 << 10) 125 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 126 127 #ifdef CONFIG_PHYS_64BIT 128 #define CONFIG_SYS_DCSRBAR 0xf0000000 129 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 130 #endif 131 132 /* EEPROM */ 133 #define CONFIG_ID_EEPROM 134 #define CONFIG_SYS_I2C_EEPROM_NXID 135 #define CONFIG_SYS_EEPROM_BUS_NUM 0 136 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 137 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 138 139 /* 140 * DDR Setup 141 */ 142 #define CONFIG_VERY_BIG_RAM 143 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 144 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 145 146 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 147 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 148 149 #define CONFIG_DDR_SPD 150 151 #define CONFIG_SYS_SPD_BUS_NUM 1 152 #define SPD_EEPROM_ADDRESS1 0x51 153 #define SPD_EEPROM_ADDRESS2 0x52 154 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 155 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 156 157 /* 158 * Local Bus Definitions 159 */ 160 161 /* Set the local bus clock 1/8 of platform clock */ 162 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 163 164 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */ 165 #ifdef CONFIG_PHYS_64BIT 166 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 167 #else 168 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 169 #endif 170 171 #define CONFIG_SYS_FLASH_BR_PRELIM \ 172 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \ 173 | BR_PS_16 | BR_V) 174 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 175 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 176 177 #define CONFIG_SYS_BR1_PRELIM \ 178 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 179 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 180 181 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 182 #ifdef CONFIG_PHYS_64BIT 183 #define PIXIS_BASE_PHYS 0xfffdf0000ull 184 #else 185 #define PIXIS_BASE_PHYS PIXIS_BASE 186 #endif 187 188 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 189 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 190 191 #define PIXIS_LBMAP_SWITCH 7 192 #define PIXIS_LBMAP_MASK 0xf0 193 #define PIXIS_LBMAP_SHIFT 4 194 #define PIXIS_LBMAP_ALTBANK 0x40 195 196 #define CONFIG_SYS_FLASH_QUIET_TEST 197 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 198 199 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 200 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 201 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 202 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 203 204 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 205 206 #if defined(CONFIG_RAMBOOT_PBL) 207 #define CONFIG_SYS_RAMBOOT 208 #endif 209 210 /* Nand Flash */ 211 #ifdef CONFIG_NAND_FSL_ELBC 212 #define CONFIG_SYS_NAND_BASE 0xffa00000 213 #ifdef CONFIG_PHYS_64BIT 214 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 215 #else 216 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 217 #endif 218 219 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 220 #define CONFIG_SYS_MAX_NAND_DEVICE 1 221 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 222 223 /* NAND flash config */ 224 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 225 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 226 | BR_PS_8 /* Port Size = 8 bit */ \ 227 | BR_MS_FCM /* MSEL = FCM */ \ 228 | BR_V) /* valid */ 229 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 230 | OR_FCM_PGS /* Large Page*/ \ 231 | OR_FCM_CSCT \ 232 | OR_FCM_CST \ 233 | OR_FCM_CHT \ 234 | OR_FCM_SCY_1 \ 235 | OR_FCM_TRLX \ 236 | OR_FCM_EHTR) 237 238 #ifdef CONFIG_NAND 239 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 240 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 241 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 242 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 243 #else 244 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 245 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 246 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 247 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 248 #endif 249 #else 250 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 251 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 252 #endif /* CONFIG_NAND_FSL_ELBC */ 253 254 #define CONFIG_SYS_FLASH_EMPTY_INFO 255 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 256 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 257 258 #define CONFIG_HWCONFIG 259 260 /* define to use L1 as initial stack */ 261 #define CONFIG_L1_INIT_RAM 262 #define CONFIG_SYS_INIT_RAM_LOCK 263 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 264 #ifdef CONFIG_PHYS_64BIT 265 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 266 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 267 /* The assembler doesn't like typecast */ 268 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 269 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 270 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 271 #else 272 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ 273 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 274 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 275 #endif 276 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 277 278 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 279 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 280 281 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 282 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 283 284 /* Serial Port - controlled on board with jumper J8 285 * open - index 2 286 * shorted - index 1 287 */ 288 #define CONFIG_SYS_NS16550_SERIAL 289 #define CONFIG_SYS_NS16550_REG_SIZE 1 290 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 291 292 #define CONFIG_SYS_BAUDRATE_TABLE \ 293 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 294 295 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 296 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 297 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 298 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 299 300 /* I2C */ 301 #define CONFIG_SYS_I2C 302 #define CONFIG_SYS_I2C_FSL 303 #define CONFIG_SYS_FSL_I2C_SPEED 400000 304 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 305 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 306 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 307 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 308 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 309 310 /* 311 * RapidIO 312 */ 313 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 314 #ifdef CONFIG_PHYS_64BIT 315 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 316 #else 317 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 318 #endif 319 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 320 321 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 322 #ifdef CONFIG_PHYS_64BIT 323 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 324 #else 325 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 326 #endif 327 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 328 329 /* 330 * for slave u-boot IMAGE instored in master memory space, 331 * PHYS must be aligned based on the SIZE 332 */ 333 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 334 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 335 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 336 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 337 /* 338 * for slave UCODE and ENV instored in master memory space, 339 * PHYS must be aligned based on the SIZE 340 */ 341 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 342 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 343 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 344 345 /* slave core release by master*/ 346 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 347 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 348 349 /* 350 * SRIO_PCIE_BOOT - SLAVE 351 */ 352 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 353 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 354 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 355 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 356 #endif 357 358 /* 359 * eSPI - Enhanced SPI 360 */ 361 362 /* 363 * General PCI 364 * Memory space is mapped 1-1, but I/O space must start from 0. 365 */ 366 367 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 368 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 369 #ifdef CONFIG_PHYS_64BIT 370 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 371 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 372 #else 373 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 374 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 375 #endif 376 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 377 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 378 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 379 #ifdef CONFIG_PHYS_64BIT 380 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 381 #else 382 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 383 #endif 384 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 385 386 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 387 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 388 #ifdef CONFIG_PHYS_64BIT 389 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 390 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 391 #else 392 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 393 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 394 #endif 395 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 396 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 397 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 398 #ifdef CONFIG_PHYS_64BIT 399 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 400 #else 401 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 402 #endif 403 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 404 405 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 406 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 407 #ifdef CONFIG_PHYS_64BIT 408 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 409 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 410 #else 411 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 412 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 413 #endif 414 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 415 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 416 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 417 #ifdef CONFIG_PHYS_64BIT 418 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 419 #else 420 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 421 #endif 422 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 423 424 /* controller 4, Base address 203000 */ 425 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 426 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 427 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 428 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 429 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 430 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 431 432 /* Qman/Bman */ 433 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 434 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 435 #ifdef CONFIG_PHYS_64BIT 436 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 437 #else 438 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 439 #endif 440 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 441 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 442 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 443 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 444 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 445 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 446 CONFIG_SYS_BMAN_CENA_SIZE) 447 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 448 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 449 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 450 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 451 #ifdef CONFIG_PHYS_64BIT 452 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 453 #else 454 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 455 #endif 456 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 457 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 458 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 459 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 460 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 461 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 462 CONFIG_SYS_QMAN_CENA_SIZE) 463 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 464 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 465 466 #define CONFIG_SYS_DPAA_FMAN 467 #define CONFIG_SYS_DPAA_PME 468 /* Default address of microcode for the Linux Fman driver */ 469 #if defined(CONFIG_SPIFLASH) 470 /* 471 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 472 * env, so we got 0x110000. 473 */ 474 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 475 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 476 #elif defined(CONFIG_SDCARD) 477 /* 478 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 479 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 480 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 481 */ 482 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 483 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 484 #elif defined(CONFIG_NAND) 485 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 486 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 487 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 488 /* 489 * Slave has no ucode locally, it can fetch this from remote. When implementing 490 * in two corenet boards, slave's ucode could be stored in master's memory 491 * space, the address can be mapped from slave TLB->slave LAW-> 492 * slave SRIO or PCIE outbound window->master inbound window-> 493 * master LAW->the ucode address in master's memory space. 494 */ 495 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 496 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 497 #else 498 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 499 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 500 #endif 501 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 502 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 503 504 #ifdef CONFIG_SYS_DPAA_FMAN 505 #define CONFIG_FMAN_ENET 506 #define CONFIG_PHYLIB_10G 507 #define CONFIG_PHY_VITESSE 508 #define CONFIG_PHY_TERANETICS 509 #endif 510 511 #ifdef CONFIG_PCI 512 #define CONFIG_PCI_INDIRECT_BRIDGE 513 514 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 515 #endif /* CONFIG_PCI */ 516 517 /* SATA */ 518 #ifdef CONFIG_FSL_SATA_V2 519 #define CONFIG_SYS_SATA_MAX_DEVICE 2 520 #define CONFIG_SATA1 521 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 522 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 523 #define CONFIG_SATA2 524 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 525 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 526 527 #define CONFIG_LBA48 528 #endif 529 530 #ifdef CONFIG_FMAN_ENET 531 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c 532 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d 533 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e 534 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f 535 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 536 537 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c 538 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d 539 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e 540 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f 541 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0 542 543 #define CONFIG_SYS_TBIPA_VALUE 8 544 #define CONFIG_ETHPRIME "FM1@DTSEC1" 545 #endif 546 547 /* 548 * Environment 549 */ 550 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 551 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 552 553 /* 554 * USB 555 */ 556 #define CONFIG_HAS_FSL_DR_USB 557 #define CONFIG_HAS_FSL_MPH_USB 558 559 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 560 #define CONFIG_USB_EHCI_FSL 561 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 562 #endif 563 564 #ifdef CONFIG_MMC 565 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 566 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 567 #endif 568 569 /* 570 * Miscellaneous configurable options 571 */ 572 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 573 574 /* 575 * For booting Linux, the board info and command line data 576 * have to be in the first 64 MB of memory, since this is 577 * the maximum mapped by the Linux kernel during initialization. 578 */ 579 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 580 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 581 582 #ifdef CONFIG_CMD_KGDB 583 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 584 #endif 585 586 /* 587 * Environment Configuration 588 */ 589 #define CONFIG_ROOTPATH "/opt/nfsroot" 590 #define CONFIG_BOOTFILE "uImage" 591 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 592 593 /* default location for tftp and bootm */ 594 #define CONFIG_LOADADDR 1000000 595 596 #ifdef CONFIG_TARGET_P4080DS 597 #define __USB_PHY_TYPE ulpi 598 #else 599 #define __USB_PHY_TYPE utmi 600 #endif 601 602 #define CONFIG_EXTRA_ENV_SETTINGS \ 603 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 604 "bank_intlv=cs0_cs1;" \ 605 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 606 "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 607 "netdev=eth0\0" \ 608 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 609 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 610 "tftpflash=tftpboot $loadaddr $uboot && " \ 611 "protect off $ubootaddr +$filesize && " \ 612 "erase $ubootaddr +$filesize && " \ 613 "cp.b $loadaddr $ubootaddr $filesize && " \ 614 "protect on $ubootaddr +$filesize && " \ 615 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 616 "consoledev=ttyS0\0" \ 617 "ramdiskaddr=2000000\0" \ 618 "ramdiskfile=p4080ds/ramdisk.uboot\0" \ 619 "fdtaddr=1e00000\0" \ 620 "fdtfile=p4080ds/p4080ds.dtb\0" \ 621 "bdev=sda3\0" 622 623 #define CONFIG_HDBOOT \ 624 "setenv bootargs root=/dev/$bdev rw " \ 625 "console=$consoledev,$baudrate $othbootargs;" \ 626 "tftp $loadaddr $bootfile;" \ 627 "tftp $fdtaddr $fdtfile;" \ 628 "bootm $loadaddr - $fdtaddr" 629 630 #define CONFIG_NFSBOOTCOMMAND \ 631 "setenv bootargs root=/dev/nfs rw " \ 632 "nfsroot=$serverip:$rootpath " \ 633 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 634 "console=$consoledev,$baudrate $othbootargs;" \ 635 "tftp $loadaddr $bootfile;" \ 636 "tftp $fdtaddr $fdtfile;" \ 637 "bootm $loadaddr - $fdtaddr" 638 639 #define CONFIG_RAMBOOTCOMMAND \ 640 "setenv bootargs root=/dev/ram rw " \ 641 "console=$consoledev,$baudrate $othbootargs;" \ 642 "tftp $ramdiskaddr $ramdiskfile;" \ 643 "tftp $loadaddr $bootfile;" \ 644 "tftp $fdtaddr $fdtfile;" \ 645 "bootm $loadaddr $ramdiskaddr $fdtaddr" 646 647 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 648 649 #include <asm/fsl_secure_boot.h> 650 651 #endif /* __CONFIG_H */ 652