1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * (C) Copyright 2008 4 * Graeme Russ, graeme.russ@gmail.com. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * board/config.h - configuration options, board specific 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 #include <configs/x86-common.h> 17 18 /* 19 * High Level Configuration Options 20 * (easy to change) 21 */ 22 #define CONFIG_SYS_COREBOOT 23 #define CONFIG_LAST_STAGE_INIT 24 #define CONFIG_SYS_EARLY_PCI_INIT 25 26 #define CONFIG_SYS_CAR_ADDR 0x19200000 27 #define CONFIG_SYS_CAR_SIZE (16 * 1024) 28 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 29 30 #define CONFIG_TRACE_EARLY_SIZE (8 << 20) 31 #define CONFIG_TRACE_EARLY 32 #define CONFIG_TRACE_EARLY_ADDR 0x01400000 33 34 #define CONFIG_BOOTSTAGE 35 #define CONFIG_BOOTSTAGE_REPORT 36 #define CONFIG_BOOTSTAGE_FDT 37 #define CONFIG_CMD_BOOTSTAGE 38 /* Place to stash bootstage data from first-stage U-Boot */ 39 #define CONFIG_BOOTSTAGE_STASH 0x0110f000 40 #define CONFIG_BOOTSTAGE_STASH_SIZE 0x7fc 41 #define CONFIG_BOOTSTAGE_USER_COUNT 60 42 43 #define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \ 44 PCI_DEVICE_ID_INTEL_NM10_AHCI}, \ 45 {PCI_VENDOR_ID_INTEL, \ 46 PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \ 47 {PCI_VENDOR_ID_INTEL, \ 48 PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \ 49 {PCI_VENDOR_ID_INTEL, \ 50 PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE} 51 52 #define CONFIG_X86_SERIAL 53 54 #define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \ 55 "stdout=vga,serial,cbmem\0" \ 56 "stderr=vga,serial,cbmem\0" 57 58 #define CONFIG_CBMEM_CONSOLE 59 60 #define CONFIG_VIDEO_COREBOOT 61 62 #define CONFIG_NR_DRAM_BANKS 4 63 64 #define CONFIG_TRACE 65 #define CONFIG_CMD_TRACE 66 #define CONFIG_TRACE_BUFFER_SIZE (16 << 20) 67 68 #define CONFIG_BOOTDELAY 2 69 70 #define CONFIG_CROS_EC 71 #define CONFIG_CROS_EC_LPC 72 #define CONFIG_CMD_CROS_EC 73 #define CONFIG_ARCH_EARLY_INIT_R 74 75 #endif /* __CONFIG_H */ 76