1 /* 2 * Copyright (C) 2014 Stefan Roese <sr@denx.de> 3 * Copyright (C) 2016 Mario Six <mario.six@gdsys.cc> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _CONFIG_CONTROLCENTERDC_H 9 #define _CONFIG_CONTROLCENTERDC_H 10 11 /* 12 * High Level Configuration Options (easy to change) 13 */ 14 #define CONFIG_CUSTOMER_BOARD_SUPPORT 15 16 #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ 17 #define CONFIG_DISPLAY_BOARDINFO_LATE 18 #define CONFIG_BOARD_LATE_INIT 19 #define CONFIG_LAST_STAGE_INIT 20 #define CONFIG_SPL_BOARD_INIT 21 22 /* 23 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed 24 * for DDR ECC byte filling in the SPL before loading the main 25 * U-Boot into it. 26 */ 27 #define CONFIG_SYS_TEXT_BASE 0x00800000 28 29 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 30 31 #define CONFIG_LOADADDR 1000000 32 33 /* 34 * Commands configuration 35 */ 36 #define CONFIG_CMD_ENV 37 #define CONFIG_CMD_I2C 38 #define CONFIG_CMD_PCI 39 #define CONFIG_CMD_SCSI 40 #define CONFIG_CMD_SPI 41 42 /* SPI NOR flash default params, used by sf commands */ 43 #define CONFIG_SF_DEFAULT_BUS 1 44 #define CONFIG_SF_DEFAULT_SPEED 1000000 45 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 46 47 /* 48 * SDIO/MMC Card Configuration 49 */ 50 #define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE 51 52 /* 53 * SATA/SCSI/AHCI configuration 54 */ 55 #define CONFIG_LIBATA 56 #define CONFIG_SCSI 57 #define CONFIG_SCSI_AHCI 58 #define CONFIG_SCSI_AHCI_PLAT 59 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 60 #define CONFIG_SYS_SCSI_MAX_LUN 1 61 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 62 CONFIG_SYS_SCSI_MAX_LUN) 63 64 /* Additional FS support/configuration */ 65 #define CONFIG_SUPPORT_VFAT 66 67 /* USB/EHCI configuration */ 68 #define CONFIG_EHCI_IS_TDI 69 70 /* Environment in SPI NOR flash */ 71 #define CONFIG_ENV_IS_IN_SPI_FLASH 72 #define CONFIG_ENV_SPI_BUS 1 73 #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 74 #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 75 #define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */ 76 77 #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 78 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 79 80 /* PCIe support */ 81 #ifndef CONFIG_SPL_BUILD 82 #define CONFIG_PCI 83 #define CONFIG_PCI_MVEBU 84 #define CONFIG_PCI_PNP 85 #define CONFIG_PCI_SCAN_SHOW 86 #endif 87 88 #define CONFIG_SYS_ALT_MEMTEST 89 90 /* 91 * Software (bit-bang) MII driver configuration 92 */ 93 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ 94 #define CONFIG_BITBANGMII_MULTI 95 96 /* SPL */ 97 /* 98 * Select the boot device here 99 * 100 * Currently supported are: 101 * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash 102 * SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1) 103 */ 104 #define SPL_BOOT_SPI_NOR_FLASH 1 105 #define SPL_BOOT_SDIO_MMC_CARD 2 106 #define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH 107 108 /* Defines for SPL */ 109 #define CONFIG_SPL_FRAMEWORK 110 #define CONFIG_SPL_SIZE (160 << 10) 111 112 #if defined(CONFIG_SECURED_MODE_IMAGE) 113 #define CONFIG_SPL_TEXT_BASE 0x40002614 114 #define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x2614) 115 #else 116 #define CONFIG_SPL_TEXT_BASE 0x40000030 117 #define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x30) 118 #endif 119 120 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) 121 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 122 123 #ifdef CONFIG_SPL_BUILD 124 #define CONFIG_SYS_MALLOC_SIMPLE 125 #endif 126 127 #define CONFIG_SPL_STACK (0x40000000 + ((212 - 16) << 10)) 128 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 129 130 #define CONFIG_SPL_LIBCOMMON_SUPPORT 131 #define CONFIG_SPL_LIBGENERIC_SUPPORT 132 #define CONFIG_SPL_SERIAL_SUPPORT 133 #define CONFIG_SPL_I2C_SUPPORT 134 135 #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH 136 /* SPL related SPI defines */ 137 #define CONFIG_SPL_SPI_LOAD 138 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x30000 139 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS 140 #endif 141 142 #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD 143 /* SPL related MMC defines */ 144 #define CONFIG_SPL_MMC_SUPPORT 145 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1 146 #define CONFIG_SYS_MMC_U_BOOT_OFFS (168 << 10) 147 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS 148 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR (CONFIG_SYS_U_BOOT_OFFS / 512) 149 #ifdef CONFIG_SPL_BUILD 150 #define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ 151 #endif 152 #endif 153 154 /* 155 * Environment Configuration 156 */ 157 #define CONFIG_ENV_OVERWRITE 158 159 #define CONFIG_BAUDRATE 115200 160 161 #define CONFIG_HOSTNAME ccdc 162 #define CONFIG_ROOTPATH "/opt/nfsroot" 163 #define CONFIG_BOOTFILE "ccdc.img" 164 165 #define CONFIG_PREBOOT /* enable preboot variable */ 166 167 #define CONFIG_EXTRA_ENV_SETTINGS \ 168 "netdev=eth1\0" \ 169 "consoledev=ttyS1\0" \ 170 "u-boot=u-boot.bin\0" \ 171 "bootfile_addr=1000000\0" \ 172 "keyprogram_addr=3000000\0" \ 173 "keyprogram_file=keyprogram.img\0" \ 174 "fdtfile=controlcenterdc.dtb\0" \ 175 "load=tftpboot ${loadaddr} ${u-boot}\0" \ 176 "mmcdev=0:2\0" \ 177 "update=sf probe 1:0;" \ 178 " sf erase 0 +${filesize};" \ 179 " sf write ${fileaddr} 0 ${filesize}\0" \ 180 "upd=run load update\0" \ 181 "fdt_high=0x10000000\0" \ 182 "initrd_high=0x10000000\0" \ 183 "loadkeyprogram=tpm flush_keys;" \ 184 " mmc rescan;" \ 185 " ext4load mmc ${mmcdev} ${keyprogram_addr} ${keyprogram_file};"\ 186 " source ${keyprogram_addr}:script@1\0" \ 187 "gpio1=gpio@22_25\0" \ 188 "gpio2=A29\0" \ 189 "blinkseq='0 0 0 0 2 0 2 2 3 1 3 1 0 0 2 2 3 1 3 3 2 0 2 2 3 1 1 1 " \ 190 "2 0 2 2 3 1 3 1 0 0 2 0 3 3 3 1 2 0 0 0 3 1 1 1 0 0 0 0'\0" \ 191 "bootfail=for i in ${blinkseq}; do" \ 192 " if test $i -eq 0; then" \ 193 " gpio clear ${gpio1}; gpio set ${gpio2};" \ 194 " elif test $i -eq 1; then" \ 195 " gpio clear ${gpio1}; gpio clear ${gpio2};" \ 196 " elif test $i -eq 2; then" \ 197 " gpio set ${gpio1}; gpio set ${gpio2};" \ 198 " else;" \ 199 " gpio clear ${gpio1}; gpio set ${gpio2};" \ 200 " fi; sleep 0.12; done\0" 201 202 #define CONFIG_NFSBOOTCOMMAND \ 203 "setenv bootargs root=/dev/nfs rw " \ 204 "nfsroot=${serverip}:${rootpath} " \ 205 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off " \ 206 "console=${consoledev},${baudrate} ${othbootargs}; " \ 207 "tftpboot ${bootfile_addr} ${bootfile}; " \ 208 "bootm ${bootfile_addr}" 209 210 #define CONFIG_MMCBOOTCOMMAND \ 211 "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ 212 "console=${consoledev},${baudrate} ${othbootargs}; " \ 213 "ext2load mmc 0:2 ${bootfile_addr} ${bootfile}; " \ 214 "bootm ${bootfile_addr}" 215 216 #define CONFIG_BOOTCOMMAND \ 217 "if env exists keyprogram; then;" \ 218 " setenv keyprogram; run nfsboot;" \ 219 " fi;" \ 220 " run dobootfail" 221 222 /* 223 * mv-common.h should be defined after CMD configs since it used them 224 * to enable certain macros 225 */ 226 #include "mv-common.h" 227 228 #endif /* _CONFIG_CONTROLCENTERDC_H */ 229