1 /* 2 * Copyright (C) 2014 Stefan Roese <sr@denx.de> 3 * Copyright (C) 2016 Mario Six <mario.six@gdsys.cc> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _CONFIG_CONTROLCENTERDC_H 9 #define _CONFIG_CONTROLCENTERDC_H 10 11 /* 12 * High Level Configuration Options (easy to change) 13 */ 14 #define CONFIG_CUSTOMER_BOARD_SUPPORT 15 16 #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ 17 #define CONFIG_DISPLAY_BOARDINFO_LATE 18 #define CONFIG_BOARD_LATE_INIT 19 #define CONFIG_LAST_STAGE_INIT 20 21 /* 22 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed 23 * for DDR ECC byte filling in the SPL before loading the main 24 * U-Boot into it. 25 */ 26 #define CONFIG_SYS_TEXT_BASE 0x00800000 27 28 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 29 30 #define CONFIG_LOADADDR 1000000 31 32 /* 33 * Commands configuration 34 */ 35 #define CONFIG_CMD_ENV 36 #define CONFIG_CMD_I2C 37 #define CONFIG_CMD_PCI 38 #define CONFIG_CMD_SCSI 39 #define CONFIG_CMD_SPI 40 41 /* SPI NOR flash default params, used by sf commands */ 42 #define CONFIG_SF_DEFAULT_BUS 1 43 #define CONFIG_SF_DEFAULT_SPEED 1000000 44 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 45 46 /* 47 * SDIO/MMC Card Configuration 48 */ 49 #define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE 50 51 /* 52 * SATA/SCSI/AHCI configuration 53 */ 54 #define CONFIG_LIBATA 55 #define CONFIG_SCSI 56 #define CONFIG_SCSI_AHCI 57 #define CONFIG_SCSI_AHCI_PLAT 58 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 59 #define CONFIG_SYS_SCSI_MAX_LUN 1 60 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 61 CONFIG_SYS_SCSI_MAX_LUN) 62 63 /* Additional FS support/configuration */ 64 #define CONFIG_SUPPORT_VFAT 65 66 /* USB/EHCI configuration */ 67 #define CONFIG_EHCI_IS_TDI 68 69 /* Environment in SPI NOR flash */ 70 #define CONFIG_ENV_IS_IN_SPI_FLASH 71 #define CONFIG_ENV_SPI_BUS 1 72 #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 73 #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 74 #define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */ 75 76 #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 77 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 78 79 /* PCIe support */ 80 #ifndef CONFIG_SPL_BUILD 81 #define CONFIG_PCI 82 #define CONFIG_PCI_MVEBU 83 #define CONFIG_PCI_PNP 84 #define CONFIG_PCI_SCAN_SHOW 85 #endif 86 87 #define CONFIG_SYS_ALT_MEMTEST 88 89 /* 90 * Software (bit-bang) MII driver configuration 91 */ 92 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ 93 #define CONFIG_BITBANGMII_MULTI 94 95 /* SPL */ 96 /* 97 * Select the boot device here 98 * 99 * Currently supported are: 100 * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash 101 * SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1) 102 */ 103 #define SPL_BOOT_SPI_NOR_FLASH 1 104 #define SPL_BOOT_SDIO_MMC_CARD 2 105 #define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH 106 107 /* Defines for SPL */ 108 #define CONFIG_SPL_FRAMEWORK 109 #define CONFIG_SPL_SIZE (160 << 10) 110 111 #if defined(CONFIG_SECURED_MODE_IMAGE) 112 #define CONFIG_SPL_TEXT_BASE 0x40002614 113 #define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x2614) 114 #else 115 #define CONFIG_SPL_TEXT_BASE 0x40000030 116 #define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x30) 117 #endif 118 119 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) 120 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 121 122 #ifdef CONFIG_SPL_BUILD 123 #define CONFIG_SYS_MALLOC_SIMPLE 124 #endif 125 126 #define CONFIG_SPL_STACK (0x40000000 + ((212 - 16) << 10)) 127 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 128 129 #define CONFIG_SPL_LIBCOMMON_SUPPORT 130 #define CONFIG_SPL_LIBGENERIC_SUPPORT 131 #define CONFIG_SPL_SERIAL_SUPPORT 132 #define CONFIG_SPL_I2C_SUPPORT 133 134 #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH 135 /* SPL related SPI defines */ 136 #define CONFIG_SPL_SPI_LOAD 137 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x30000 138 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS 139 #endif 140 141 #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD 142 /* SPL related MMC defines */ 143 #define CONFIG_SPL_MMC_SUPPORT 144 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1 145 #define CONFIG_SYS_MMC_U_BOOT_OFFS (168 << 10) 146 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS 147 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR (CONFIG_SYS_U_BOOT_OFFS / 512) 148 #ifdef CONFIG_SPL_BUILD 149 #define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ 150 #endif 151 #endif 152 153 /* 154 * Environment Configuration 155 */ 156 #define CONFIG_ENV_OVERWRITE 157 158 #define CONFIG_BAUDRATE 115200 159 160 #define CONFIG_HOSTNAME ccdc 161 #define CONFIG_ROOTPATH "/opt/nfsroot" 162 #define CONFIG_BOOTFILE "ccdc.img" 163 164 #define CONFIG_PREBOOT /* enable preboot variable */ 165 166 #define CONFIG_EXTRA_ENV_SETTINGS \ 167 "netdev=eth1\0" \ 168 "consoledev=ttyS1\0" \ 169 "u-boot=u-boot.bin\0" \ 170 "bootfile_addr=1000000\0" \ 171 "keyprogram_addr=3000000\0" \ 172 "keyprogram_file=keyprogram.img\0" \ 173 "fdtfile=controlcenterdc.dtb\0" \ 174 "load=tftpboot ${loadaddr} ${u-boot}\0" \ 175 "mmcdev=0:2\0" \ 176 "update=sf probe 1:0;" \ 177 " sf erase 0 +${filesize};" \ 178 " sf write ${fileaddr} 0 ${filesize}\0" \ 179 "upd=run load update\0" \ 180 "fdt_high=0x10000000\0" \ 181 "initrd_high=0x10000000\0" \ 182 "loadkeyprogram=tpm flush_keys;" \ 183 " mmc rescan;" \ 184 " ext4load mmc ${mmcdev} ${keyprogram_addr} ${keyprogram_file};"\ 185 " source ${keyprogram_addr}:script@1\0" \ 186 "gpio1=gpio@22_25\0" \ 187 "gpio2=A29\0" \ 188 "blinkseq='0 0 0 0 2 0 2 2 3 1 3 1 0 0 2 2 3 1 3 3 2 0 2 2 3 1 1 1 " \ 189 "2 0 2 2 3 1 3 1 0 0 2 0 3 3 3 1 2 0 0 0 3 1 1 1 0 0 0 0'\0" \ 190 "bootfail=for i in ${blinkseq}; do" \ 191 " if test $i -eq 0; then" \ 192 " gpio clear ${gpio1}; gpio set ${gpio2};" \ 193 " elif test $i -eq 1; then" \ 194 " gpio clear ${gpio1}; gpio clear ${gpio2};" \ 195 " elif test $i -eq 2; then" \ 196 " gpio set ${gpio1}; gpio set ${gpio2};" \ 197 " else;" \ 198 " gpio clear ${gpio1}; gpio set ${gpio2};" \ 199 " fi; sleep 0.12; done\0" 200 201 #define CONFIG_NFSBOOTCOMMAND \ 202 "setenv bootargs root=/dev/nfs rw " \ 203 "nfsroot=${serverip}:${rootpath} " \ 204 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off " \ 205 "console=${consoledev},${baudrate} ${othbootargs}; " \ 206 "tftpboot ${bootfile_addr} ${bootfile}; " \ 207 "bootm ${bootfile_addr}" 208 209 #define CONFIG_MMCBOOTCOMMAND \ 210 "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ 211 "console=${consoledev},${baudrate} ${othbootargs}; " \ 212 "ext2load mmc 0:2 ${bootfile_addr} ${bootfile}; " \ 213 "bootm ${bootfile_addr}" 214 215 #define CONFIG_BOOTCOMMAND \ 216 "if env exists keyprogram; then;" \ 217 " setenv keyprogram; run nfsboot;" \ 218 " fi;" \ 219 " run dobootfail" 220 221 /* 222 * mv-common.h should be defined after CMD configs since it used them 223 * to enable certain macros 224 */ 225 #include "mv-common.h" 226 227 #endif /* _CONFIG_CONTROLCENTERDC_H */ 228