1 /* 2 * (C) Copyright 2013 3 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc 4 * 5 * based on P1022DS.h 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #ifndef __CONFIG_H 27 #define __CONFIG_H 28 29 #ifdef CONFIG_36BIT 30 #define CONFIG_PHYS_64BIT 31 #endif 32 33 #ifdef CONFIG_SDCARD 34 #define CONFIG_RAMBOOT_SDCARD 35 #endif 36 37 #ifdef CONFIG_SPIFLASH 38 #define CONFIG_RAMBOOT_SPIFLASH 39 #endif 40 41 /* High Level Configuration Options */ 42 #define CONFIG_BOOKE /* BOOKE */ 43 #define CONFIG_E500 /* BOOKE e500 family */ 44 #define CONFIG_P1022 45 #define CONFIG_CONTROLCENTERD 46 #define CONFIG_MP /* support multiple processors */ 47 48 #define CONFIG_SYS_NO_FLASH 49 #define CONFIG_ENABLE_36BIT_PHYS 50 #define CONFIG_FSL_LAW /* Use common FSL init code */ 51 52 #ifdef CONFIG_TRAILBLAZER 53 #define CONFIG_IDENT_STRING " controlcenterd trailblazer 0.01" 54 #else 55 #define CONFIG_IDENT_STRING " controlcenterd 0.01" 56 #endif 57 58 #ifdef CONFIG_PHYS_64BIT 59 #define CONFIG_ADDR_MAP 60 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 61 #endif 62 63 #define CONFIG_L2_CACHE 64 #define CONFIG_BTB 65 66 #define CONFIG_SYS_CLK_FREQ 66666600 67 #define CONFIG_DDR_CLK_FREQ 66666600 68 69 #define CONFIG_SYS_RAMBOOT 70 71 #ifdef CONFIG_TRAILBLAZER 72 73 #define CONFIG_SYS_TEXT_BASE 0xf8fc0000 74 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc 75 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 76 77 /* 78 * Config the L2 Cache 79 */ 80 #define CONFIG_SYS_INIT_L2_ADDR 0xf8fc0000 81 #ifdef CONFIG_PHYS_64BIT 82 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8fc0000ull 83 #else 84 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 85 #endif 86 #define CONFIG_SYS_L2_SIZE (256 << 10) 87 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 88 89 #else /* CONFIG_TRAILBLAZER */ 90 91 #define CONFIG_SYS_TEXT_BASE 0x11000000 92 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 93 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 94 95 #endif /* CONFIG_TRAILBLAZER */ 96 97 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 98 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 99 100 101 /* 102 * Memory map 103 * 104 * 0x0000_0000 0x3fff_ffff DDR 1G Cacheable 105 * 0xc000_0000 0xdfff_ffff PCI Express Mem 512M non-cacheable 106 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable 107 * 108 * Localbus non-cacheable 109 * 0xe000_0000 0xe00f_ffff eLBC 1M non-cacheable 110 * 0xf8fc0000 0xf8ff_ffff L2 SRAM 256k Cacheable 111 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 112 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 113 */ 114 115 #define CONFIG_SYS_INIT_RAM_LOCK 116 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 117 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* used area in RAM */ 118 #define CONFIG_SYS_GBL_DATA_OFFSET \ 119 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 120 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 121 122 #ifdef CONFIG_TRAILBLAZER 123 /* leave CCSRBAR at default, because u-boot expects it to be exactly there */ 124 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT 125 #else 126 #define CONFIG_SYS_CCSRBAR 0xffe00000 127 #endif 128 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 129 #define CONFIG_SYS_MPC85xx_GPIO3_ADDR (CONFIG_SYS_CCSRBAR+0xf200) 130 131 /* 132 * DDR Setup 133 */ 134 135 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 136 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 137 #define CONFIG_SYS_SDRAM_SIZE 1024 138 #define CONFIG_VERY_BIG_RAM 139 140 #define CONFIG_SYS_FSL_DDR3 141 #define CONFIG_NUM_DDR_CONTROLLERS 1 142 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 143 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 144 145 #define CONFIG_SYS_MEMTEST_START 0x00000000 146 #define CONFIG_SYS_MEMTEST_END 0x3fffffff 147 148 #ifdef CONFIG_TRAILBLAZER 149 #define CONFIG_SPD_EEPROM 150 #define SPD_EEPROM_ADDRESS 0x52 151 /*#define CONFIG_FSL_DDR_INTERACTIVE*/ 152 #endif 153 154 /* 155 * Local Bus Definitions 156 */ 157 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 158 159 #define CONFIG_SYS_ELBC_BASE 0xe0000000 160 #ifdef CONFIG_PHYS_64BIT 161 #define CONFIG_SYS_ELBC_BASE_PHYS 0xfe0000000ull 162 #else 163 #define CONFIG_SYS_ELBC_BASE_PHYS CONFIG_SYS_ELBC_BASE 164 #endif 165 166 #define CONFIG_UART_BR_PRELIM \ 167 (BR_PHYS_ADDR((CONFIG_SYS_ELBC_BASE_PHYS)) | BR_PS_8 | BR_V) 168 #define CONFIG_UART_OR_PRELIM (OR_AM_32KB | 0xff7) 169 170 #define CONFIG_SYS_BR0_PRELIM 0 /* CS0 was originally intended for FPGA */ 171 #define CONFIG_SYS_OR0_PRELIM 0 /* debugging, was never used */ 172 173 #define CONFIG_SYS_BR1_PRELIM CONFIG_UART_BR_PRELIM 174 #define CONFIG_SYS_OR1_PRELIM CONFIG_UART_OR_PRELIM 175 176 /* 177 * Serial Port 178 */ 179 #define CONFIG_CONS_INDEX 2 180 #define CONFIG_SYS_NS16550 181 #define CONFIG_SYS_NS16550_SERIAL 182 #define CONFIG_SYS_NS16550_REG_SIZE 1 183 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 184 185 #define CONFIG_SYS_BAUDRATE_TABLE \ 186 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 187 188 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 189 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 190 191 /* 192 * I2C 193 */ 194 #define CONFIG_SYS_I2C 195 #define CONFIG_SYS_I2C_FSL 196 #define CONFIG_SYS_FSL_I2C_SPEED 400000 197 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 198 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 199 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 200 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 201 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 202 /* Probing DP501 I2C-Bridge will hang */ 203 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x30}, {0, 0x37}, {0, 0x3a}, \ 204 {0, 0x3b}, {0, 0x50} } 205 206 #define CONFIG_PCA9698 /* NXP PCA9698 */ 207 208 #define CONFIG_CMD_EEPROM 209 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 210 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 211 212 #ifndef CONFIG_TRAILBLAZER 213 /* 214 * eSPI - Enhanced SPI 215 */ 216 #define CONFIG_HARD_SPI 217 #define CONFIG_FSL_ESPI 218 219 #define CONFIG_SPI_FLASH 220 #define CONFIG_SPI_FLASH_STMICRO 221 222 #define CONFIG_CMD_SF 223 #define CONFIG_SF_DEFAULT_SPEED 10000000 224 #define CONFIG_SF_DEFAULT_MODE 0 225 #endif 226 227 /* 228 * TPM 229 */ 230 #define CONFIG_TPM_ATMEL_TWI 231 #define CONFIG_TPM 232 #define CONFIG_TPM_AUTH_SESSIONS 233 #define CONFIG_SHA1 234 #define CONFIG_CMD_TPM 235 236 /* 237 * MMC 238 */ 239 #define CONFIG_MMC 240 #define CONFIG_GENERIC_MMC 241 #define CONFIG_CMD_MMC 242 243 #define CONFIG_FSL_ESDHC 244 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 245 246 247 #ifndef CONFIG_TRAILBLAZER 248 249 /* 250 * Video 251 */ 252 #define CONFIG_FSL_DIU_FB 253 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) 254 #define CONFIG_VIDEO 255 #define CONFIG_CFB_CONSOLE 256 #define CONFIG_VGA_AS_SINGLE_DEVICE 257 #define CONFIG_CMD_BMP 258 259 /* 260 * General PCI 261 * Memory space is mapped 1-1, but I/O space must start from 0. 262 */ 263 #define CONFIG_PCI /* Enable PCI/PCIE */ 264 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 265 #define CONFIG_PCI_INDIRECT_BRIDGE 266 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 267 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 268 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 269 #define CONFIG_CMD_PCI 270 271 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 272 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 273 274 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 275 #ifdef CONFIG_PHYS_64BIT 276 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 277 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 278 #else 279 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 280 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 281 #endif 282 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 283 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 284 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 285 #ifdef CONFIG_PHYS_64BIT 286 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 287 #else 288 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 289 #endif 290 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 291 292 /* 293 * SATA 294 */ 295 #define CONFIG_LIBATA 296 #define CONFIG_LBA48 297 #define CONFIG_CMD_SATA 298 299 #define CONFIG_FSL_SATA 300 #define CONFIG_SYS_SATA_MAX_DEVICE 2 301 #define CONFIG_SATA1 302 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 303 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 304 #define CONFIG_SATA2 305 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 306 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 307 308 /* 309 * Ethernet 310 */ 311 #define CONFIG_TSEC_ENET 312 313 #define CONFIG_TSECV2 314 315 #define CONFIG_MII /* MII PHY management */ 316 #define CONFIG_TSEC1 1 317 #define CONFIG_TSEC1_NAME "eTSEC1" 318 #define CONFIG_TSEC2 1 319 #define CONFIG_TSEC2_NAME "eTSEC2" 320 321 #define TSEC1_PHY_ADDR 0 322 #define TSEC2_PHY_ADDR 1 323 324 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 325 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 326 327 #define TSEC1_PHYIDX 0 328 #define TSEC2_PHYIDX 0 329 330 #define CONFIG_ETHPRIME "eTSEC1" 331 332 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 333 334 /* 335 * USB 336 */ 337 #define CONFIG_USB_EHCI 338 #define CONFIG_CMD_USB 339 #define CONFIG_USB_STORAGE 340 341 #define CONFIG_HAS_FSL_DR_USB 342 #define CONFIG_USB_EHCI_FSL 343 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 344 345 #endif /* CONFIG_TRAILBLAZER */ 346 347 /* 348 * Environment 349 */ 350 #if defined(CONFIG_TRAILBLAZER) 351 #define CONFIG_ENV_IS_NOWHERE 352 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 353 #undef CONFIG_CMD_SAVEENV 354 #elif defined(CONFIG_RAMBOOT_SPIFLASH) 355 #define CONFIG_ENV_IS_IN_SPI_FLASH 356 #define CONFIG_ENV_SPI_BUS 0 357 #define CONFIG_ENV_SPI_CS 0 358 #define CONFIG_ENV_SPI_MAX_HZ 10000000 359 #define CONFIG_ENV_SPI_MODE 0 360 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 361 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 362 #define CONFIG_ENV_SECT_SIZE 0x10000 363 #elif defined(CONFIG_RAMBOOT_SDCARD) 364 #define CONFIG_ENV_IS_IN_MMC 365 #define CONFIG_FSL_FIXED_MMC_LOCATION 366 #define CONFIG_ENV_SIZE 0x2000 367 #define CONFIG_SYS_MMC_ENV_DEV 0 368 #endif 369 370 #define CONFIG_SYS_EXTRA_ENV_RELOC 371 372 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 373 374 /* 375 * Command line configuration. 376 */ 377 #ifndef CONFIG_TRAILBLAZER 378 #define CONFIG_SYS_HUSH_PARSER 379 #define CONFIG_SYS_LONGHELP 380 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 381 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 382 #endif /* CONFIG_TRAILBLAZER */ 383 384 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 385 #ifdef CONFIG_CMD_KGDB 386 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 387 #else 388 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 389 #endif 390 /* Print Buffer Size */ 391 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 392 #define CONFIG_SYS_MAXARGS 16 393 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 394 395 #include <config_cmd_default.h> 396 397 #ifndef CONFIG_TRAILBLAZER 398 399 #define CONFIG_CMD_ELF 400 #define CONFIG_CMD_ERRATA 401 #define CONFIG_CMD_EXT2 402 #define CONFIG_CMD_FAT 403 #define CONFIG_CMD_IRQ 404 #define CONFIG_CMD_MII 405 #define CONFIG_CMD_NET 406 #define CONFIG_CMD_PING 407 #define CONFIG_CMD_SETEXPR 408 #define CONFIG_CMD_REGINFO 409 410 /* 411 * Board initialisation callbacks 412 */ 413 #define CONFIG_BOARD_EARLY_INIT_F 414 #define CONFIG_BOARD_EARLY_INIT_R 415 #define CONFIG_MISC_INIT_R 416 #define CONFIG_LAST_STAGE_INIT 417 418 /* 419 * Pass open firmware flat tree 420 */ 421 #define CONFIG_OF_LIBFDT 422 #define CONFIG_OF_BOARD_SETUP 423 #define CONFIG_OF_STDOUT_VIA_ALIAS 424 425 /* new uImage format support */ 426 #define CONFIG_FIT 427 #define CONFIG_FIT_VERBOSE 428 429 #else /* CONFIG_TRAILBLAZER */ 430 431 #define CONFIG_BOARD_EARLY_INIT_F 432 #define CONFIG_BOARD_EARLY_INIT_R 433 #define CONFIG_LAST_STAGE_INIT 434 #undef CONFIG_CMD_BOOTM 435 436 #endif /* CONFIG_TRAILBLAZER */ 437 438 /* 439 * Miscellaneous configurable options 440 */ 441 #define CONFIG_HW_WATCHDOG 442 #define CONFIG_LOADS_ECHO 443 #define CONFIG_SYS_LOADS_BAUD_CHANGE 444 #define CONFIG_DOS_PARTITION 445 446 /* 447 * For booting Linux, the board info and command line data 448 * have to be in the first 64 MB of memory, since this is 449 * the maximum mapped by the Linux kernel during initialization. 450 */ 451 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Linux Memory map */ 452 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 453 454 /* 455 * Environment Configuration 456 */ 457 458 #ifdef CONFIG_TRAILBLAZER 459 460 #define CONFIG_BOOTDELAY 0 /* -1 disables auto-boot */ 461 #define CONFIG_BAUDRATE 115200 462 463 #define CONFIG_EXTRA_ENV_SETTINGS \ 464 "mp_holdoff=1\0" 465 466 #else 467 468 #define CONFIG_HOSTNAME controlcenterd 469 #define CONFIG_ROOTPATH "/opt/nfsroot" 470 #define CONFIG_BOOTFILE "uImage" 471 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP */ 472 473 #define CONFIG_LOADADDR 1000000 474 475 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 476 477 #define CONFIG_BAUDRATE 115200 478 479 #define CONFIG_EXTRA_ENV_SETTINGS \ 480 "netdev=eth0\0" \ 481 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 482 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 483 "tftpflash=tftpboot $loadaddr $uboot && " \ 484 "protect off $ubootaddr +$filesize && " \ 485 "erase $ubootaddr +$filesize && " \ 486 "cp.b $loadaddr $ubootaddr $filesize && " \ 487 "protect on $ubootaddr +$filesize && " \ 488 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 489 "consoledev=ttyS1\0" \ 490 "ramdiskaddr=2000000\0" \ 491 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 492 "fdtaddr=c00000\0" \ 493 "fdtfile=controlcenterd.dtb\0" \ 494 "bdev=sda3\0" 495 496 /* these are used and NUL-terminated in env_default.h */ 497 #define CONFIG_NFSBOOTCOMMAND \ 498 "setenv bootargs root=/dev/nfs rw " \ 499 "nfsroot=$serverip:$rootpath " \ 500 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 501 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 502 "tftp $loadaddr $bootfile;" \ 503 "tftp $fdtaddr $fdtfile;" \ 504 "bootm $loadaddr - $fdtaddr" 505 506 #define CONFIG_RAMBOOTCOMMAND \ 507 "setenv bootargs root=/dev/ram rw " \ 508 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 509 "tftp $ramdiskaddr $ramdiskfile;" \ 510 "tftp $loadaddr $bootfile;" \ 511 "tftp $fdtaddr $fdtfile;" \ 512 "bootm $loadaddr $ramdiskaddr $fdtaddr" 513 514 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 515 516 #endif /* CONFIG_TRAILBLAZER */ 517 518 #endif 519