1 /* 2 * (C) Copyright 2013 3 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc 4 * 5 * based on P1022DS.h 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #ifndef __CONFIG_H 27 #define __CONFIG_H 28 29 #ifdef CONFIG_36BIT 30 #define CONFIG_PHYS_64BIT 31 #endif 32 33 #ifdef CONFIG_SDCARD 34 #define CONFIG_RAMBOOT_SDCARD 35 #endif 36 37 #ifdef CONFIG_SPIFLASH 38 #define CONFIG_RAMBOOT_SPIFLASH 39 #endif 40 41 /* High Level Configuration Options */ 42 #define CONFIG_BOOKE /* BOOKE */ 43 #define CONFIG_E500 /* BOOKE e500 family */ 44 #define CONFIG_P1022 45 #define CONFIG_CONTROLCENTERD 46 #define CONFIG_MP /* support multiple processors */ 47 48 #define CONFIG_SYS_NO_FLASH 49 #define CONFIG_ENABLE_36BIT_PHYS 50 #define CONFIG_FSL_LAW /* Use common FSL init code */ 51 52 #ifdef CONFIG_TRAILBLAZER 53 #define CONFIG_IDENT_STRING " controlcenterd trailblazer 0.01" 54 #else 55 #define CONFIG_IDENT_STRING " controlcenterd 0.01" 56 #endif 57 58 #ifdef CONFIG_PHYS_64BIT 59 #define CONFIG_ADDR_MAP 60 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 61 #endif 62 63 #define CONFIG_L2_CACHE 64 #define CONFIG_BTB 65 66 #define CONFIG_SYS_CLK_FREQ 66666600 67 #define CONFIG_DDR_CLK_FREQ 66666600 68 69 #define CONFIG_SYS_RAMBOOT 70 71 #ifdef CONFIG_TRAILBLAZER 72 73 #define CONFIG_SYS_TEXT_BASE 0xf8fc0000 74 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc 75 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 76 77 /* 78 * Config the L2 Cache 79 */ 80 #define CONFIG_SYS_INIT_L2_ADDR 0xf8fc0000 81 #ifdef CONFIG_PHYS_64BIT 82 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8fc0000ull 83 #else 84 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 85 #endif 86 #define CONFIG_SYS_L2_SIZE (256 << 10) 87 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 88 89 #else /* CONFIG_TRAILBLAZER */ 90 91 #define CONFIG_SYS_TEXT_BASE 0x11000000 92 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 93 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 94 95 #endif /* CONFIG_TRAILBLAZER */ 96 97 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 98 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 99 100 /* 101 * Memory map 102 * 103 * 0x0000_0000 0x3fff_ffff DDR 1G Cacheable 104 * 0xc000_0000 0xdfff_ffff PCI Express Mem 512M non-cacheable 105 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable 106 * 107 * Localbus non-cacheable 108 * 0xe000_0000 0xe00f_ffff eLBC 1M non-cacheable 109 * 0xf8fc0000 0xf8ff_ffff L2 SRAM 256k Cacheable 110 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 111 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 112 */ 113 114 #define CONFIG_SYS_INIT_RAM_LOCK 115 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 116 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* used area in RAM */ 117 #define CONFIG_SYS_GBL_DATA_OFFSET \ 118 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 119 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 120 121 #ifdef CONFIG_TRAILBLAZER 122 /* leave CCSRBAR at default, because u-boot expects it to be exactly there */ 123 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT 124 #else 125 #define CONFIG_SYS_CCSRBAR 0xffe00000 126 #endif 127 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 128 #define CONFIG_SYS_MPC85xx_GPIO3_ADDR (CONFIG_SYS_CCSRBAR+0xf200) 129 130 /* 131 * DDR Setup 132 */ 133 134 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 135 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 136 #define CONFIG_SYS_SDRAM_SIZE 1024 137 #define CONFIG_VERY_BIG_RAM 138 139 #define CONFIG_SYS_FSL_DDR3 140 #define CONFIG_NUM_DDR_CONTROLLERS 1 141 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 142 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 143 144 #define CONFIG_SYS_MEMTEST_START 0x00000000 145 #define CONFIG_SYS_MEMTEST_END 0x3fffffff 146 147 #ifdef CONFIG_TRAILBLAZER 148 #define CONFIG_SPD_EEPROM 149 #define SPD_EEPROM_ADDRESS 0x52 150 /*#define CONFIG_FSL_DDR_INTERACTIVE*/ 151 #endif 152 153 /* 154 * Local Bus Definitions 155 */ 156 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 157 158 #define CONFIG_SYS_ELBC_BASE 0xe0000000 159 #ifdef CONFIG_PHYS_64BIT 160 #define CONFIG_SYS_ELBC_BASE_PHYS 0xfe0000000ull 161 #else 162 #define CONFIG_SYS_ELBC_BASE_PHYS CONFIG_SYS_ELBC_BASE 163 #endif 164 165 #define CONFIG_UART_BR_PRELIM \ 166 (BR_PHYS_ADDR((CONFIG_SYS_ELBC_BASE_PHYS)) | BR_PS_8 | BR_V) 167 #define CONFIG_UART_OR_PRELIM (OR_AM_32KB | 0xff7) 168 169 #define CONFIG_SYS_BR0_PRELIM 0 /* CS0 was originally intended for FPGA */ 170 #define CONFIG_SYS_OR0_PRELIM 0 /* debugging, was never used */ 171 172 #define CONFIG_SYS_BR1_PRELIM CONFIG_UART_BR_PRELIM 173 #define CONFIG_SYS_OR1_PRELIM CONFIG_UART_OR_PRELIM 174 175 /* 176 * Serial Port 177 */ 178 #define CONFIG_CONS_INDEX 2 179 #define CONFIG_SYS_NS16550_SERIAL 180 #define CONFIG_SYS_NS16550_REG_SIZE 1 181 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 182 183 #define CONFIG_SYS_BAUDRATE_TABLE \ 184 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 185 186 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 187 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 188 189 /* 190 * I2C 191 */ 192 #define CONFIG_SYS_I2C 193 #define CONFIG_SYS_I2C_FSL 194 #define CONFIG_SYS_FSL_I2C_SPEED 400000 195 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 196 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 197 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 198 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 199 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 200 201 #ifndef CONFIG_TRAILBLAZER 202 #endif 203 204 #define CONFIG_PCA9698 /* NXP PCA9698 */ 205 206 #define CONFIG_CMD_EEPROM 207 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 208 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 209 210 #ifndef CONFIG_TRAILBLAZER 211 /* 212 * eSPI - Enhanced SPI 213 */ 214 #define CONFIG_HARD_SPI 215 216 #define CONFIG_SF_DEFAULT_SPEED 10000000 217 #define CONFIG_SF_DEFAULT_MODE 0 218 #endif 219 220 #define CONFIG_SHA1 221 222 /* 223 * MMC 224 */ 225 #define CONFIG_MMC 226 #define CONFIG_GENERIC_MMC 227 228 #define CONFIG_FSL_ESDHC 229 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 230 231 #ifndef CONFIG_TRAILBLAZER 232 233 /* 234 * Video 235 */ 236 #define CONFIG_FSL_DIU_FB 237 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) 238 #define CONFIG_VIDEO 239 #define CONFIG_CFB_CONSOLE 240 #define CONFIG_VGA_AS_SINGLE_DEVICE 241 #define CONFIG_CMD_BMP 242 243 /* 244 * General PCI 245 * Memory space is mapped 1-1, but I/O space must start from 0. 246 */ 247 #define CONFIG_PCI /* Enable PCI/PCIE */ 248 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 249 #define CONFIG_PCI_INDIRECT_BRIDGE 250 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 251 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 252 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 253 #define CONFIG_CMD_PCI 254 255 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 256 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 257 258 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 259 #ifdef CONFIG_PHYS_64BIT 260 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 261 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 262 #else 263 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 264 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 265 #endif 266 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 267 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 268 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 269 #ifdef CONFIG_PHYS_64BIT 270 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 271 #else 272 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 273 #endif 274 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 275 276 /* 277 * SATA 278 */ 279 #define CONFIG_LIBATA 280 #define CONFIG_LBA48 281 #define CONFIG_CMD_SATA 282 283 #define CONFIG_FSL_SATA 284 #define CONFIG_SYS_SATA_MAX_DEVICE 2 285 #define CONFIG_SATA1 286 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 287 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 288 #define CONFIG_SATA2 289 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 290 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 291 292 /* 293 * Ethernet 294 */ 295 #define CONFIG_TSEC_ENET 296 297 #define CONFIG_TSECV2 298 299 #define CONFIG_MII /* MII PHY management */ 300 #define CONFIG_TSEC1 1 301 #define CONFIG_TSEC1_NAME "eTSEC1" 302 #define CONFIG_TSEC2 1 303 #define CONFIG_TSEC2_NAME "eTSEC2" 304 305 #define TSEC1_PHY_ADDR 0 306 #define TSEC2_PHY_ADDR 1 307 308 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 309 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 310 311 #define TSEC1_PHYIDX 0 312 #define TSEC2_PHYIDX 0 313 314 #define CONFIG_ETHPRIME "eTSEC1" 315 316 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 317 318 /* 319 * USB 320 */ 321 #define CONFIG_USB_EHCI 322 #define CONFIG_USB_STORAGE 323 324 #define CONFIG_HAS_FSL_DR_USB 325 #define CONFIG_USB_EHCI_FSL 326 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 327 328 #endif /* CONFIG_TRAILBLAZER */ 329 330 /* 331 * Environment 332 */ 333 #if defined(CONFIG_TRAILBLAZER) 334 #define CONFIG_ENV_IS_NOWHERE 335 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 336 #elif defined(CONFIG_RAMBOOT_SPIFLASH) 337 #define CONFIG_ENV_IS_IN_SPI_FLASH 338 #define CONFIG_ENV_SPI_BUS 0 339 #define CONFIG_ENV_SPI_CS 0 340 #define CONFIG_ENV_SPI_MAX_HZ 10000000 341 #define CONFIG_ENV_SPI_MODE 0 342 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 343 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 344 #define CONFIG_ENV_SECT_SIZE 0x10000 345 #elif defined(CONFIG_RAMBOOT_SDCARD) 346 #define CONFIG_ENV_IS_IN_MMC 347 #define CONFIG_FSL_FIXED_MMC_LOCATION 348 #define CONFIG_ENV_SIZE 0x2000 349 #define CONFIG_SYS_MMC_ENV_DEV 0 350 #endif 351 352 #define CONFIG_SYS_EXTRA_ENV_RELOC 353 354 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 355 356 /* 357 * Command line configuration. 358 */ 359 #ifndef CONFIG_TRAILBLAZER 360 #define CONFIG_SYS_LONGHELP 361 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 362 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 363 #endif /* CONFIG_TRAILBLAZER */ 364 365 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 366 #ifdef CONFIG_CMD_KGDB 367 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 368 #else 369 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 370 #endif 371 /* Print Buffer Size */ 372 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 373 #define CONFIG_SYS_MAXARGS 16 374 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 375 376 #ifndef CONFIG_TRAILBLAZER 377 378 #define CONFIG_CMD_ERRATA 379 #define CONFIG_CMD_IRQ 380 #define CONFIG_CMD_REGINFO 381 382 /* 383 * Board initialisation callbacks 384 */ 385 #define CONFIG_BOARD_EARLY_INIT_F 386 #define CONFIG_BOARD_EARLY_INIT_R 387 #define CONFIG_MISC_INIT_R 388 #define CONFIG_LAST_STAGE_INIT 389 390 #else /* CONFIG_TRAILBLAZER */ 391 392 #define CONFIG_BOARD_EARLY_INIT_F 393 #define CONFIG_BOARD_EARLY_INIT_R 394 #define CONFIG_LAST_STAGE_INIT 395 396 #endif /* CONFIG_TRAILBLAZER */ 397 398 /* 399 * Miscellaneous configurable options 400 */ 401 #define CONFIG_HW_WATCHDOG 402 #define CONFIG_LOADS_ECHO 403 #define CONFIG_SYS_LOADS_BAUD_CHANGE 404 #define CONFIG_DOS_PARTITION 405 406 /* 407 * For booting Linux, the board info and command line data 408 * have to be in the first 64 MB of memory, since this is 409 * the maximum mapped by the Linux kernel during initialization. 410 */ 411 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Linux Memory map */ 412 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 413 414 /* 415 * Environment Configuration 416 */ 417 418 #ifdef CONFIG_TRAILBLAZER 419 420 #define CONFIG_BAUDRATE 115200 421 422 #define CONFIG_EXTRA_ENV_SETTINGS \ 423 "mp_holdoff=1\0" 424 425 #else 426 427 #define CONFIG_HOSTNAME controlcenterd 428 #define CONFIG_ROOTPATH "/opt/nfsroot" 429 #define CONFIG_BOOTFILE "uImage" 430 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP */ 431 432 #define CONFIG_LOADADDR 1000000 433 434 435 #define CONFIG_BAUDRATE 115200 436 437 #define CONFIG_EXTRA_ENV_SETTINGS \ 438 "netdev=eth0\0" \ 439 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 440 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 441 "tftpflash=tftpboot $loadaddr $uboot && " \ 442 "protect off $ubootaddr +$filesize && " \ 443 "erase $ubootaddr +$filesize && " \ 444 "cp.b $loadaddr $ubootaddr $filesize && " \ 445 "protect on $ubootaddr +$filesize && " \ 446 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 447 "consoledev=ttyS1\0" \ 448 "ramdiskaddr=2000000\0" \ 449 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 450 "fdtaddr=1e00000\0" \ 451 "fdtfile=controlcenterd.dtb\0" \ 452 "bdev=sda3\0" 453 454 /* these are used and NUL-terminated in env_default.h */ 455 #define CONFIG_NFSBOOTCOMMAND \ 456 "setenv bootargs root=/dev/nfs rw " \ 457 "nfsroot=$serverip:$rootpath " \ 458 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 459 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 460 "tftp $loadaddr $bootfile;" \ 461 "tftp $fdtaddr $fdtfile;" \ 462 "bootm $loadaddr - $fdtaddr" 463 464 #define CONFIG_RAMBOOTCOMMAND \ 465 "setenv bootargs root=/dev/ram rw " \ 466 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 467 "tftp $ramdiskaddr $ramdiskfile;" \ 468 "tftp $loadaddr $bootfile;" \ 469 "tftp $fdtaddr $fdtfile;" \ 470 "bootm $loadaddr $ramdiskaddr $fdtaddr" 471 472 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 473 474 #endif /* CONFIG_TRAILBLAZER */ 475 476 #endif 477