1 /* 2 * (C) Copyright 2013 3 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc 4 * 5 * based on P1022DS.h 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #ifndef __CONFIG_H 27 #define __CONFIG_H 28 29 #ifdef CONFIG_SDCARD 30 #define CONFIG_RAMBOOT_SDCARD 31 #endif 32 33 #ifdef CONFIG_SPIFLASH 34 #define CONFIG_RAMBOOT_SPIFLASH 35 #endif 36 37 /* High Level Configuration Options */ 38 #define CONFIG_CONTROLCENTERD 39 40 #define CONFIG_ENABLE_36BIT_PHYS 41 42 #ifdef CONFIG_PHYS_64BIT 43 #define CONFIG_ADDR_MAP 44 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 45 #endif 46 47 #define CONFIG_L2_CACHE 48 #define CONFIG_BTB 49 50 #define CONFIG_SYS_CLK_FREQ 66666600 51 #define CONFIG_DDR_CLK_FREQ 66666600 52 53 #define CONFIG_SYS_RAMBOOT 54 55 #ifdef CONFIG_TRAILBLAZER 56 57 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc 58 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 59 60 /* 61 * Config the L2 Cache 62 */ 63 #define CONFIG_SYS_INIT_L2_ADDR 0xf8fc0000 64 #ifdef CONFIG_PHYS_64BIT 65 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8fc0000ull 66 #else 67 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 68 #endif 69 #define CONFIG_SYS_L2_SIZE (256 << 10) 70 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 71 72 #else /* CONFIG_TRAILBLAZER */ 73 74 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 75 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 76 77 #endif /* CONFIG_TRAILBLAZER */ 78 79 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 80 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 81 82 /* 83 * Memory map 84 * 85 * 0x0000_0000 0x3fff_ffff DDR 1G Cacheable 86 * 0xc000_0000 0xdfff_ffff PCI Express Mem 512M non-cacheable 87 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable 88 * 89 * Localbus non-cacheable 90 * 0xe000_0000 0xe00f_ffff eLBC 1M non-cacheable 91 * 0xf8fc0000 0xf8ff_ffff L2 SRAM 256k Cacheable 92 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 93 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 94 */ 95 96 #define CONFIG_SYS_INIT_RAM_LOCK 97 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 98 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* used area in RAM */ 99 #define CONFIG_SYS_GBL_DATA_OFFSET \ 100 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 101 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 102 103 #ifdef CONFIG_TRAILBLAZER 104 /* leave CCSRBAR at default, because u-boot expects it to be exactly there */ 105 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT 106 #else 107 #define CONFIG_SYS_CCSRBAR 0xffe00000 108 #endif 109 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 110 #define CONFIG_SYS_MPC85xx_GPIO3_ADDR (CONFIG_SYS_CCSRBAR+0xf200) 111 112 /* 113 * DDR Setup 114 */ 115 116 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 117 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 118 #define CONFIG_SYS_SDRAM_SIZE 1024 119 #define CONFIG_VERY_BIG_RAM 120 121 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 122 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 123 124 #define CONFIG_SYS_MEMTEST_START 0x00000000 125 #define CONFIG_SYS_MEMTEST_END 0x3fffffff 126 127 #ifdef CONFIG_TRAILBLAZER 128 #define CONFIG_SPD_EEPROM 129 #define SPD_EEPROM_ADDRESS 0x52 130 /*#define CONFIG_FSL_DDR_INTERACTIVE*/ 131 #endif 132 133 /* 134 * Local Bus Definitions 135 */ 136 137 #define CONFIG_SYS_ELBC_BASE 0xe0000000 138 #ifdef CONFIG_PHYS_64BIT 139 #define CONFIG_SYS_ELBC_BASE_PHYS 0xfe0000000ull 140 #else 141 #define CONFIG_SYS_ELBC_BASE_PHYS CONFIG_SYS_ELBC_BASE 142 #endif 143 144 #define CONFIG_UART_BR_PRELIM \ 145 (BR_PHYS_ADDR((CONFIG_SYS_ELBC_BASE_PHYS)) | BR_PS_8 | BR_V) 146 #define CONFIG_UART_OR_PRELIM (OR_AM_32KB | 0xff7) 147 148 #define CONFIG_SYS_BR0_PRELIM 0 /* CS0 was originally intended for FPGA */ 149 #define CONFIG_SYS_OR0_PRELIM 0 /* debugging, was never used */ 150 151 #define CONFIG_SYS_BR1_PRELIM CONFIG_UART_BR_PRELIM 152 #define CONFIG_SYS_OR1_PRELIM CONFIG_UART_OR_PRELIM 153 154 /* 155 * Serial Port 156 */ 157 #define CONFIG_SYS_NS16550_SERIAL 158 #define CONFIG_SYS_NS16550_REG_SIZE 1 159 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 160 161 #define CONFIG_SYS_BAUDRATE_TABLE \ 162 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 163 164 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 165 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 166 167 /* 168 * I2C 169 */ 170 #define CONFIG_SYS_I2C 171 #define CONFIG_SYS_I2C_FSL 172 #define CONFIG_SYS_FSL_I2C_SPEED 400000 173 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 174 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 175 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 176 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 177 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 178 179 #define CONFIG_PCA9698 /* NXP PCA9698 */ 180 181 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 182 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 183 184 /* 185 * MMC 186 */ 187 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 188 189 #ifndef CONFIG_TRAILBLAZER 190 191 /* 192 * Video 193 */ 194 #define CONFIG_FSL_DIU_FB 195 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) 196 197 /* 198 * General PCI 199 * Memory space is mapped 1-1, but I/O space must start from 0. 200 */ 201 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 202 #define CONFIG_PCI_INDIRECT_BRIDGE 203 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 204 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 205 206 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 207 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 208 209 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 210 #ifdef CONFIG_PHYS_64BIT 211 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 212 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 213 #else 214 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 215 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 216 #endif 217 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 218 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 219 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 220 #ifdef CONFIG_PHYS_64BIT 221 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 222 #else 223 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 224 #endif 225 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 226 227 /* 228 * SATA 229 */ 230 #define CONFIG_LBA48 231 232 #define CONFIG_SYS_SATA_MAX_DEVICE 2 233 #define CONFIG_SATA1 234 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 235 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 236 #define CONFIG_SATA2 237 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 238 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 239 240 /* 241 * Ethernet 242 */ 243 244 #define CONFIG_TSECV2 245 246 #define CONFIG_TSEC1 1 247 #define CONFIG_TSEC1_NAME "eTSEC1" 248 #define CONFIG_TSEC2 1 249 #define CONFIG_TSEC2_NAME "eTSEC2" 250 251 #define TSEC1_PHY_ADDR 0 252 #define TSEC2_PHY_ADDR 1 253 254 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 255 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 256 257 #define TSEC1_PHYIDX 0 258 #define TSEC2_PHYIDX 0 259 260 #define CONFIG_ETHPRIME "eTSEC1" 261 262 /* 263 * USB 264 */ 265 266 #define CONFIG_HAS_FSL_DR_USB 267 #define CONFIG_USB_EHCI_FSL 268 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 269 270 #endif /* CONFIG_TRAILBLAZER */ 271 272 /* 273 * Environment 274 */ 275 #if defined(CONFIG_TRAILBLAZER) 276 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 277 #elif defined(CONFIG_RAMBOOT_SPIFLASH) 278 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 279 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 280 #define CONFIG_ENV_SECT_SIZE 0x10000 281 #elif defined(CONFIG_RAMBOOT_SDCARD) 282 #define CONFIG_FSL_FIXED_MMC_LOCATION 283 #define CONFIG_ENV_SIZE 0x2000 284 #define CONFIG_SYS_MMC_ENV_DEV 0 285 #endif 286 287 /* 288 * Command line configuration. 289 */ 290 291 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 292 293 #ifndef CONFIG_TRAILBLAZER 294 /* 295 * Board initialisation callbacks 296 */ 297 #endif /* CONFIG_TRAILBLAZER */ 298 299 /* 300 * Miscellaneous configurable options 301 */ 302 #define CONFIG_HW_WATCHDOG 303 #define CONFIG_LOADS_ECHO 304 #define CONFIG_SYS_LOADS_BAUD_CHANGE 305 306 /* 307 * For booting Linux, the board info and command line data 308 * have to be in the first 64 MB of memory, since this is 309 * the maximum mapped by the Linux kernel during initialization. 310 */ 311 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Linux Memory map */ 312 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 313 314 /* 315 * Environment Configuration 316 */ 317 318 #ifdef CONFIG_TRAILBLAZER 319 #define CONFIG_EXTRA_ENV_SETTINGS \ 320 "mp_holdoff=1\0" 321 322 #else 323 324 #define CONFIG_HOSTNAME "controlcenterd" 325 #define CONFIG_ROOTPATH "/opt/nfsroot" 326 #define CONFIG_BOOTFILE "uImage" 327 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP */ 328 329 #define CONFIG_LOADADDR 1000000 330 331 #define CONFIG_EXTRA_ENV_SETTINGS \ 332 "netdev=eth0\0" \ 333 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 334 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 335 "tftpflash=tftpboot $loadaddr $uboot && " \ 336 "protect off $ubootaddr +$filesize && " \ 337 "erase $ubootaddr +$filesize && " \ 338 "cp.b $loadaddr $ubootaddr $filesize && " \ 339 "protect on $ubootaddr +$filesize && " \ 340 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 341 "consoledev=ttyS1\0" \ 342 "ramdiskaddr=2000000\0" \ 343 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 344 "fdtaddr=1e00000\0" \ 345 "fdtfile=controlcenterd.dtb\0" \ 346 "bdev=sda3\0" 347 348 /* these are used and NUL-terminated in env_default.h */ 349 #define CONFIG_NFSBOOTCOMMAND \ 350 "setenv bootargs root=/dev/nfs rw " \ 351 "nfsroot=$serverip:$rootpath " \ 352 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 353 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 354 "tftp $loadaddr $bootfile;" \ 355 "tftp $fdtaddr $fdtfile;" \ 356 "bootm $loadaddr - $fdtaddr" 357 358 #define CONFIG_RAMBOOTCOMMAND \ 359 "setenv bootargs root=/dev/ram rw " \ 360 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 361 "tftp $ramdiskaddr $ramdiskfile;" \ 362 "tftp $loadaddr $bootfile;" \ 363 "tftp $fdtaddr $fdtfile;" \ 364 "bootm $loadaddr $ramdiskaddr $fdtaddr" 365 366 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 367 368 #endif /* CONFIG_TRAILBLAZER */ 369 370 #endif 371