1 /* 2 * Toradex Colibri PXA270 configuration file 3 * 4 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> 5 * Copyright (C) 2015 Marcel Ziswiler <marcel@ziswiler.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 /* 14 * High Level Board Configuration Options 15 */ 16 #define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ 17 #define CONFIG_SYS_TEXT_BASE 0x0 18 /* Avoid overwriting factory configuration block */ 19 #define CONFIG_BOARD_SIZE_LIMIT 0x40000 20 21 /* We will never enable dcache because we have to setup MMU first */ 22 #define CONFIG_SYS_DCACHE_OFF 23 24 /* 25 * Environment settings 26 */ 27 #define CONFIG_ENV_OVERWRITE 28 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) 29 #define CONFIG_ARCH_CPU_INIT 30 #define CONFIG_BOOTCOMMAND \ 31 "if fatload mmc 0 0xa0000000 uImage; then " \ 32 "bootm 0xa0000000; " \ 33 "fi; " \ 34 "if usb reset && fatload usb 0 0xa0000000 uImage; then " \ 35 "bootm 0xa0000000; " \ 36 "fi; " \ 37 "bootm 0xc0000;" 38 #define CONFIG_BOOTARGS "console=tty0 console=ttyS0,115200" 39 #define CONFIG_TIMESTAMP 40 #define CONFIG_BOOTDELAY 2 /* Autoboot delay */ 41 #define CONFIG_CMDLINE_TAG 42 #define CONFIG_SETUP_MEMORY_TAGS 43 #define CONFIG_LZMA /* LZMA compression support */ 44 45 /* 46 * Serial Console Configuration 47 */ 48 #define CONFIG_PXA_SERIAL 49 #define CONFIG_FFUART 1 50 #define CONFIG_CONS_INDEX 3 51 #define CONFIG_BAUDRATE 115200 52 53 /* 54 * Bootloader Components Configuration 55 */ 56 #define CONFIG_CMD_ENV 57 #define CONFIG_CMD_MMC 58 #define CONFIG_CMD_USB 59 60 /* I2C support */ 61 #ifdef CONFIG_SYS_I2C 62 #define CONFIG_CMD_I2C 63 #define CONFIG_SYS_I2C_PXA 64 #define CONFIG_PXA_STD_I2C 65 #define CONFIG_PXA_PWR_I2C 66 #define CONFIG_SYS_I2C_SPEED 100000 67 #endif 68 69 /* LCD support */ 70 #ifdef CONFIG_LCD 71 #define CONFIG_PXA_LCD 72 #define CONFIG_PXA_VGA 73 #define CONFIG_SYS_WHITE_ON_BLACK 74 #define CONFIG_CONSOLE_SCROLL_LINES 10 75 #define CONFIG_CMD_BMP 76 #define CONFIG_LCD_LOGO 77 #endif 78 79 /* 80 * Networking Configuration 81 */ 82 #ifdef CONFIG_CMD_NET 83 #define CONFIG_CMD_PING 84 #define CONFIG_CMD_DHCP 85 86 #define CONFIG_DRIVER_DM9000 1 87 #define CONFIG_DM9000_BASE 0x08000000 88 #define DM9000_IO (CONFIG_DM9000_BASE) 89 #define DM9000_DATA (CONFIG_DM9000_BASE + 4) 90 #define CONFIG_NET_RETRY_COUNT 10 91 92 #define CONFIG_BOOTP_BOOTFILESIZE 93 #define CONFIG_BOOTP_BOOTPATH 94 #define CONFIG_BOOTP_GATEWAY 95 #define CONFIG_BOOTP_HOSTNAME 96 #endif 97 98 /* 99 * HUSH Shell Configuration 100 */ 101 #define CONFIG_SYS_HUSH_PARSER 1 102 103 #undef CONFIG_SYS_LONGHELP /* Saves 10 KB */ 104 #undef CONFIG_SYS_PROMPT 105 #ifdef CONFIG_SYS_HUSH_PARSER 106 #define CONFIG_SYS_PROMPT "$ " 107 #else 108 #endif 109 #define CONFIG_SYS_CBSIZE 256 110 #define CONFIG_SYS_PBSIZE \ 111 (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 112 #define CONFIG_SYS_MAXARGS 16 113 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 114 #define CONFIG_SYS_DEVICE_NULLDEV 1 115 #define CONFIG_CMDLINE_EDITING 1 116 #define CONFIG_AUTO_COMPLETE 1 117 118 /* 119 * Clock Configuration 120 */ 121 #define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */ 122 123 /* 124 * DRAM Map 125 */ 126 #define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */ 127 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ 128 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ 129 130 #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ 131 #define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */ 132 133 #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ 134 #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ 135 136 #define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 137 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 138 #define CONFIG_SYS_INIT_SP_ADDR 0x5c010000 139 140 /* 141 * NOR FLASH 142 */ 143 #ifdef CONFIG_CMD_FLASH 144 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ 145 #define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ 146 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 147 148 #define CONFIG_SYS_FLASH_CFI 149 #define CONFIG_FLASH_CFI_DRIVER 1 150 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT 151 152 #define CONFIG_SYS_MAX_FLASH_SECT (4 + 255) 153 #define CONFIG_SYS_MAX_FLASH_BANKS 1 154 155 #define CONFIG_SYS_FLASH_ERASE_TOUT (25 * CONFIG_SYS_HZ) 156 #define CONFIG_SYS_FLASH_WRITE_TOUT (25 * CONFIG_SYS_HZ) 157 #define CONFIG_SYS_FLASH_LOCK_TOUT (25 * CONFIG_SYS_HZ) 158 #define CONFIG_SYS_FLASH_UNLOCK_TOUT (25 * CONFIG_SYS_HZ) 159 160 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 161 #define CONFIG_SYS_FLASH_PROTECTION 1 162 163 #define CONFIG_ENV_IS_IN_FLASH 1 164 165 #else /* No flash */ 166 #define CONFIG_SYS_NO_FLASH 167 #define CONFIG_ENV_IS_NOWHERE 168 #endif 169 170 #define CONFIG_SYS_MONITOR_BASE 0x0 171 #define CONFIG_SYS_MONITOR_LEN 0x40000 172 173 /* Skip factory configuration block */ 174 #define CONFIG_ENV_ADDR \ 175 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN + 0x40000) 176 #define CONFIG_ENV_SIZE 0x40000 177 #define CONFIG_ENV_SECT_SIZE 0x40000 178 179 /* 180 * GPIO settings 181 */ 182 #define CONFIG_SYS_GPSR0_VAL 0x00000000 183 #define CONFIG_SYS_GPSR1_VAL 0x00020000 184 #define CONFIG_SYS_GPSR2_VAL 0x0002c000 185 #define CONFIG_SYS_GPSR3_VAL 0x00000000 186 187 #define CONFIG_SYS_GPCR0_VAL 0x00000000 188 #define CONFIG_SYS_GPCR1_VAL 0x00000000 189 #define CONFIG_SYS_GPCR2_VAL 0x00000000 190 #define CONFIG_SYS_GPCR3_VAL 0x00000000 191 192 #define CONFIG_SYS_GPDR0_VAL 0xc8008000 193 #define CONFIG_SYS_GPDR1_VAL 0xfc02a981 194 #define CONFIG_SYS_GPDR2_VAL 0x92c3ffff 195 #define CONFIG_SYS_GPDR3_VAL 0x0061e804 196 197 #define CONFIG_SYS_GAFR0_L_VAL 0x80100000 198 #define CONFIG_SYS_GAFR0_U_VAL 0xa5c00010 199 #define CONFIG_SYS_GAFR1_L_VAL 0x6992901a 200 #define CONFIG_SYS_GAFR1_U_VAL 0xaaa50008 201 #define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa 202 #define CONFIG_SYS_GAFR2_U_VAL 0x4109a002 203 #define CONFIG_SYS_GAFR3_L_VAL 0x54000310 204 #define CONFIG_SYS_GAFR3_U_VAL 0x00005401 205 206 #define CONFIG_SYS_PSSR_VAL 0x30 207 208 /* 209 * Clock settings 210 */ 211 #define CONFIG_SYS_CKEN 0x00500240 212 #define CONFIG_SYS_CCCR 0x02000290 213 214 /* 215 * Memory settings 216 */ 217 #define CONFIG_SYS_MSC0_VAL 0x9ee1c5f2 218 #define CONFIG_SYS_MSC1_VAL 0x9ee1f994 219 #define CONFIG_SYS_MSC2_VAL 0x9ee19ee1 220 #define CONFIG_SYS_MDCNFG_VAL 0x090009c9 221 #define CONFIG_SYS_MDREFR_VAL 0x2003a031 222 #define CONFIG_SYS_MDMRS_VAL 0x00220022 223 #define CONFIG_SYS_FLYCNFG_VAL 0x00010001 224 #define CONFIG_SYS_SXCNFG_VAL 0x40044004 225 226 /* 227 * PCMCIA and CF Interfaces 228 */ 229 #define CONFIG_SYS_MECR_VAL 0x00000000 230 #define CONFIG_SYS_MCMEM0_VAL 0x00028307 231 #define CONFIG_SYS_MCMEM1_VAL 0x00014307 232 #define CONFIG_SYS_MCATT0_VAL 0x00038787 233 #define CONFIG_SYS_MCATT1_VAL 0x0001c787 234 #define CONFIG_SYS_MCIO0_VAL 0x0002830f 235 #define CONFIG_SYS_MCIO1_VAL 0x0001430f 236 237 #include "pxa-common.h" 238 239 #endif /* __CONFIG_H */ 240