1 /* 2 * Toradex Colibri PXA270 configuration file 3 * 4 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> 5 * Copyright (C) 2015-2016 Marcel Ziswiler <marcel@ziswiler.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 /* 14 * High Level Board Configuration Options 15 */ 16 #define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ 17 /* Avoid overwriting factory configuration block */ 18 #define CONFIG_BOARD_SIZE_LIMIT 0x40000 19 20 /* We will never enable dcache because we have to setup MMU first */ 21 #define CONFIG_SYS_DCACHE_OFF 22 23 /* 24 * Environment settings 25 */ 26 #define CONFIG_ENV_OVERWRITE 27 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 28 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) 29 #define CONFIG_ARCH_CPU_INIT 30 #define CONFIG_BOOTCOMMAND \ 31 "if fatload mmc 0 0xa0000000 uImage; then " \ 32 "bootm 0xa0000000; " \ 33 "fi; " \ 34 "if usb reset && fatload usb 0 0xa0000000 uImage; then " \ 35 "bootm 0xa0000000; " \ 36 "fi; " \ 37 "bootm 0xc0000;" 38 #define CONFIG_TIMESTAMP 39 #define CONFIG_CMDLINE_TAG 40 #define CONFIG_SETUP_MEMORY_TAGS 41 42 /* 43 * Serial Console Configuration 44 */ 45 46 /* 47 * Bootloader Components Configuration 48 */ 49 50 /* I2C support */ 51 #ifdef CONFIG_SYS_I2C 52 #define CONFIG_SYS_I2C_PXA 53 #define CONFIG_PXA_STD_I2C 54 #define CONFIG_PXA_PWR_I2C 55 #define CONFIG_SYS_I2C_SPEED 100000 56 #endif 57 58 /* LCD support */ 59 #ifdef CONFIG_LCD 60 #define CONFIG_PXA_LCD 61 #define CONFIG_PXA_VGA 62 #define CONFIG_LCD_LOGO 63 #endif 64 65 /* 66 * Networking Configuration 67 */ 68 #ifdef CONFIG_CMD_NET 69 70 #define CONFIG_DRIVER_DM9000 1 71 #define CONFIG_DM9000_BASE 0x08000000 72 #define DM9000_IO (CONFIG_DM9000_BASE) 73 #define DM9000_DATA (CONFIG_DM9000_BASE + 4) 74 #define CONFIG_NET_RETRY_COUNT 10 75 76 #define CONFIG_BOOTP_BOOTFILESIZE 77 #endif 78 79 #define CONFIG_SYS_DEVICE_NULLDEV 1 80 81 /* 82 * Clock Configuration 83 */ 84 #define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */ 85 86 /* 87 * DRAM Map 88 */ 89 #define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */ 90 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ 91 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ 92 93 #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ 94 #define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */ 95 96 #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ 97 #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ 98 99 #define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 100 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 101 #define CONFIG_SYS_INIT_SP_ADDR 0x5c010000 102 103 /* 104 * NOR FLASH 105 */ 106 #ifdef CONFIG_CMD_FLASH 107 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ 108 #define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ 109 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 110 111 #define CONFIG_SYS_FLASH_CFI 112 #define CONFIG_FLASH_CFI_DRIVER 1 113 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT 114 115 #define CONFIG_SYS_MAX_FLASH_SECT (4 + 255) 116 #define CONFIG_SYS_MAX_FLASH_BANKS 1 117 118 #define CONFIG_SYS_FLASH_ERASE_TOUT (25 * CONFIG_SYS_HZ) 119 #define CONFIG_SYS_FLASH_WRITE_TOUT (25 * CONFIG_SYS_HZ) 120 #define CONFIG_SYS_FLASH_LOCK_TOUT (25 * CONFIG_SYS_HZ) 121 #define CONFIG_SYS_FLASH_UNLOCK_TOUT (25 * CONFIG_SYS_HZ) 122 123 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 124 #define CONFIG_SYS_FLASH_PROTECTION 1 125 #endif 126 127 #define CONFIG_SYS_MONITOR_BASE 0x0 128 #define CONFIG_SYS_MONITOR_LEN 0x40000 129 130 /* Skip factory configuration block */ 131 #define CONFIG_ENV_ADDR \ 132 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN + 0x40000) 133 #define CONFIG_ENV_SIZE 0x40000 134 #define CONFIG_ENV_SECT_SIZE 0x40000 135 136 /* 137 * GPIO settings 138 */ 139 #define CONFIG_SYS_GPSR0_VAL 0x00000000 140 #define CONFIG_SYS_GPSR1_VAL 0x00020000 141 #define CONFIG_SYS_GPSR2_VAL 0x0002c000 142 #define CONFIG_SYS_GPSR3_VAL 0x00000000 143 144 #define CONFIG_SYS_GPCR0_VAL 0x00000000 145 #define CONFIG_SYS_GPCR1_VAL 0x00000000 146 #define CONFIG_SYS_GPCR2_VAL 0x00000000 147 #define CONFIG_SYS_GPCR3_VAL 0x00000000 148 149 #define CONFIG_SYS_GPDR0_VAL 0xc8008000 150 #define CONFIG_SYS_GPDR1_VAL 0xfc02a981 151 #define CONFIG_SYS_GPDR2_VAL 0x92c3ffff 152 #define CONFIG_SYS_GPDR3_VAL 0x0061e804 153 154 #define CONFIG_SYS_GAFR0_L_VAL 0x80100000 155 #define CONFIG_SYS_GAFR0_U_VAL 0xa5c00010 156 #define CONFIG_SYS_GAFR1_L_VAL 0x6992901a 157 #define CONFIG_SYS_GAFR1_U_VAL 0xaaa50008 158 #define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa 159 #define CONFIG_SYS_GAFR2_U_VAL 0x4109a002 160 #define CONFIG_SYS_GAFR3_L_VAL 0x54000310 161 #define CONFIG_SYS_GAFR3_U_VAL 0x00005401 162 163 #define CONFIG_SYS_PSSR_VAL 0x30 164 165 /* 166 * Clock settings 167 */ 168 #define CONFIG_SYS_CKEN 0x00500240 169 #define CONFIG_SYS_CCCR 0x02000290 170 171 /* 172 * Memory settings 173 */ 174 #define CONFIG_SYS_MSC0_VAL 0x9ee1c5f2 175 #define CONFIG_SYS_MSC1_VAL 0x9ee1f994 176 #define CONFIG_SYS_MSC2_VAL 0x9ee19ee1 177 #define CONFIG_SYS_MDCNFG_VAL 0x090009c9 178 #define CONFIG_SYS_MDREFR_VAL 0x2003a031 179 #define CONFIG_SYS_MDMRS_VAL 0x00220022 180 #define CONFIG_SYS_FLYCNFG_VAL 0x00010001 181 #define CONFIG_SYS_SXCNFG_VAL 0x40044004 182 183 /* 184 * PCMCIA and CF Interfaces 185 */ 186 #define CONFIG_SYS_MECR_VAL 0x00000000 187 #define CONFIG_SYS_MCMEM0_VAL 0x00028307 188 #define CONFIG_SYS_MCMEM1_VAL 0x00014307 189 #define CONFIG_SYS_MCATT0_VAL 0x00038787 190 #define CONFIG_SYS_MCATT1_VAL 0x0001c787 191 #define CONFIG_SYS_MCIO0_VAL 0x0002830f 192 #define CONFIG_SYS_MCIO1_VAL 0x0001430f 193 194 #include "pxa-common.h" 195 196 #endif /* __CONFIG_H */ 197