1 /* 2 * Toradex Colibri PXA270 configuration file 3 * 4 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * MA 02111-1307 USA 20 */ 21 22 #ifndef __CONFIG_H 23 #define __CONFIG_H 24 25 /* 26 * High Level Board Configuration Options 27 */ 28 #define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ 29 #define CONFIG_SYS_TEXT_BASE 0x0 30 31 /* 32 * Environment settings 33 */ 34 #define CONFIG_ENV_OVERWRITE 35 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) 36 #define CONFIG_ARCH_CPU_INIT 37 #define CONFIG_BOOTCOMMAND \ 38 "if mmc init && fatload mmc 0 0xa0000000 uImage; then " \ 39 "bootm 0xa0000000; " \ 40 "fi; " \ 41 "if usb reset && fatload usb 0 0xa0000000 uImage; then " \ 42 "bootm 0xa0000000; " \ 43 "fi; " \ 44 "bootm 0x80000;" 45 #define CONFIG_BOOTARGS "console=tty0 console=ttyS0,115200" 46 #define CONFIG_TIMESTAMP 47 #define CONFIG_BOOTDELAY 2 /* Autoboot delay */ 48 #define CONFIG_CMDLINE_TAG 49 #define CONFIG_SETUP_MEMORY_TAGS 50 #define CONFIG_LZMA /* LZMA compression support */ 51 #define CONFIG_OF_LIBFDT 52 53 /* 54 * Serial Console Configuration 55 */ 56 #define CONFIG_PXA_SERIAL 57 #define CONFIG_FFUART 1 58 #define CONFIG_BAUDRATE 115200 59 60 /* 61 * Bootloader Components Configuration 62 */ 63 #include <config_cmd_default.h> 64 65 #define CONFIG_CMD_NET 66 #define CONFIG_CMD_ENV 67 #undef CONFIG_CMD_IMLS 68 #define CONFIG_CMD_MMC 69 #define CONFIG_CMD_USB 70 #define CONFIG_CMD_FLASH 71 72 /* 73 * Networking Configuration 74 * chip on the Voipac PXA270 board 75 */ 76 #ifdef CONFIG_CMD_NET 77 #define CONFIG_CMD_PING 78 #define CONFIG_CMD_DHCP 79 80 #define CONFIG_DRIVER_DM9000 1 81 #define CONFIG_DM9000_BASE 0x08000000 82 #define DM9000_IO (CONFIG_DM9000_BASE) 83 #define DM9000_DATA (CONFIG_DM9000_BASE + 4) 84 #define CONFIG_NET_RETRY_COUNT 10 85 86 #define CONFIG_BOOTP_BOOTFILESIZE 87 #define CONFIG_BOOTP_BOOTPATH 88 #define CONFIG_BOOTP_GATEWAY 89 #define CONFIG_BOOTP_HOSTNAME 90 #endif 91 92 /* 93 * HUSH Shell Configuration 94 */ 95 #define CONFIG_SYS_HUSH_PARSER 1 96 97 #define CONFIG_SYS_LONGHELP 98 #ifdef CONFIG_SYS_HUSH_PARSER 99 #define CONFIG_SYS_PROMPT "$ " 100 #else 101 #define CONFIG_SYS_PROMPT "=> " 102 #endif 103 #define CONFIG_SYS_CBSIZE 256 104 #define CONFIG_SYS_PBSIZE \ 105 (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 106 #define CONFIG_SYS_MAXARGS 16 107 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 108 #define CONFIG_SYS_DEVICE_NULLDEV 1 109 #define CONFIG_CMDLINE_EDITING 1 110 #define CONFIG_AUTO_COMPLETE 1 111 112 113 /* 114 * Clock Configuration 115 */ 116 #define CONFIG_SYS_HZ 1000 /* Timer @ 3250000 Hz */ 117 #define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */ 118 119 /* 120 * Stack sizes 121 * 122 * The stack sizes are set up in start.S using the settings below 123 */ 124 #define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ 125 #ifdef CONFIG_USE_IRQ 126 #define CONFIG_STACKSIZE_IRQ (4 * 1024) /* IRQ stack */ 127 #define CONFIG_STACKSIZE_FIQ (4 * 1024) /* FIQ stack */ 128 #endif 129 130 /* 131 * DRAM Map 132 */ 133 #define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */ 134 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ 135 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ 136 137 #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ 138 #define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */ 139 140 #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ 141 #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ 142 143 #define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 144 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 145 #define CONFIG_SYS_INIT_SP_ADDR 0x5c010000 146 147 /* 148 * NOR FLASH 149 */ 150 #ifdef CONFIG_CMD_FLASH 151 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ 152 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 153 154 #define CONFIG_SYS_FLASH_CFI 155 #define CONFIG_FLASH_CFI_DRIVER 1 156 157 #define CONFIG_SYS_MAX_FLASH_SECT (4 + 255) 158 #define CONFIG_SYS_MAX_FLASH_BANKS 1 159 160 #define CONFIG_SYS_FLASH_ERASE_TOUT (25 * CONFIG_SYS_HZ) 161 #define CONFIG_SYS_FLASH_WRITE_TOUT (25 * CONFIG_SYS_HZ) 162 163 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 164 #define CONFIG_SYS_FLASH_PROTECTION 1 165 166 #define CONFIG_ENV_IS_IN_FLASH 1 167 168 #else /* No flash */ 169 #define CONFIG_SYS_NO_FLASH 170 #define CONFIG_SYS_ENV_IS_NOWHERE 171 #endif 172 173 #define CONFIG_SYS_MONITOR_BASE 0x0 174 #define CONFIG_SYS_MONITOR_LEN 0x80000 175 176 #define CONFIG_ENV_ADDR \ 177 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 178 #define CONFIG_ENV_SIZE 0x40000 179 #define CONFIG_ENV_SECT_SIZE 0x40000 180 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 181 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 182 183 /* 184 * GPIO settings 185 */ 186 #define CONFIG_SYS_GPSR0_VAL 0x00000000 187 #define CONFIG_SYS_GPSR1_VAL 0x00020000 188 #define CONFIG_SYS_GPSR2_VAL 0x0002C000 189 #define CONFIG_SYS_GPSR3_VAL 0x00000000 190 191 #define CONFIG_SYS_GPCR0_VAL 0x00000000 192 #define CONFIG_SYS_GPCR1_VAL 0x00000000 193 #define CONFIG_SYS_GPCR2_VAL 0x00000000 194 #define CONFIG_SYS_GPCR3_VAL 0x00000000 195 196 #define CONFIG_SYS_GPDR0_VAL 0x08000000 197 #define CONFIG_SYS_GPDR1_VAL 0x0002A981 198 #define CONFIG_SYS_GPDR2_VAL 0x0202FC00 199 #define CONFIG_SYS_GPDR3_VAL 0x00000000 200 201 #define CONFIG_SYS_GAFR0_L_VAL 0x00100000 202 #define CONFIG_SYS_GAFR0_U_VAL 0x00C00010 203 #define CONFIG_SYS_GAFR1_L_VAL 0x999A901A 204 #define CONFIG_SYS_GAFR1_U_VAL 0xAAA00008 205 #define CONFIG_SYS_GAFR2_L_VAL 0xAAAAAAAA 206 #define CONFIG_SYS_GAFR2_U_VAL 0x0109A000 207 #define CONFIG_SYS_GAFR3_L_VAL 0x54000300 208 #define CONFIG_SYS_GAFR3_U_VAL 0x00024001 209 210 #define CONFIG_SYS_PSSR_VAL 0x30 211 212 /* 213 * Clock settings 214 */ 215 #define CONFIG_SYS_CKEN 0x00500240 216 #define CONFIG_SYS_CCCR 0x02000290 217 218 /* 219 * Memory settings 220 */ 221 #define CONFIG_SYS_MSC0_VAL 0x000095f2 222 #define CONFIG_SYS_MSC1_VAL 0x00007ff4 223 #define CONFIG_SYS_MSC2_VAL 0x00000000 224 #define CONFIG_SYS_MDCNFG_VAL 0x08000ac9 225 #define CONFIG_SYS_MDREFR_VAL 0x2013e01e 226 #define CONFIG_SYS_MDMRS_VAL 0x00320032 227 #define CONFIG_SYS_FLYCNFG_VAL 0x00000000 228 #define CONFIG_SYS_SXCNFG_VAL 0x40044004 229 230 /* 231 * PCMCIA and CF Interfaces 232 */ 233 #define CONFIG_SYS_MECR_VAL 0x00000001 234 #define CONFIG_SYS_MCMEM0_VAL 0x00014307 235 #define CONFIG_SYS_MCMEM1_VAL 0x00014307 236 #define CONFIG_SYS_MCATT0_VAL 0x0001c787 237 #define CONFIG_SYS_MCATT1_VAL 0x0001c787 238 #define CONFIG_SYS_MCIO0_VAL 0x0001430f 239 #define CONFIG_SYS_MCIO1_VAL 0x0001430f 240 241 #include "pxa-common.h" 242 243 #endif /* __CONFIG_H */ 244