1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Configuation settings for the Sentec Cobra Board. 4 * 5 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> 6 */ 7 8 /* --- 9 * Version: U-Boot 1.0.0 - initial release for Sentec COBRA5272 board 10 * Date: 2004-03-29 11 * Author: Florian Schlote 12 * 13 * For a description of configuration options please refer also to the 14 * general u-boot-1.x.x/README file 15 * --- 16 */ 17 18 /* --- 19 * board/config.h - configuration options, board specific 20 * --- 21 */ 22 23 #ifndef _CONFIG_COBRA5272_H 24 #define _CONFIG_COBRA5272_H 25 26 /* --- 27 * Defines processor clock - important for correct timings concerning serial 28 * interface etc. 29 * --- 30 */ 31 32 #define CONFIG_SYS_CLK 66000000 33 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 34 35 /* --- 36 * Enable use of Ethernet 37 * --- 38 */ 39 #define CONFIG_MCFFEC 40 41 /* Enable Dma Timer */ 42 #define CONFIG_MCFTMR 43 44 /* --- 45 * Define baudrate for UART1 (console output, tftp, ...) 46 * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud 47 * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected in u-boot command 48 * interface 49 * --- 50 */ 51 52 #define CONFIG_MCFUART 53 #define CONFIG_SYS_UART_PORT (0) 54 55 /* --- 56 * set "#if 0" to "#if 1" if (Hardware)-WATCHDOG should be enabled & change 57 * timeout acc. to your needs 58 * #define CONFIG_WATCHDOG_TIMEOUT x , x is timeout in milliseconds, e. g. 10000 59 * for 10 sec 60 * --- 61 */ 62 63 #if 0 64 #define CONFIG_WATCHDOG 65 #define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */ 66 #endif 67 68 /* --- 69 * CONFIG_MONITOR_IS_IN_RAM defines if u-boot is started from a different 70 * bootloader residing in flash ('chainloading'); if you want to use 71 * chainloading or want to compile a u-boot binary that can be loaded into 72 * RAM via BDM set 73 * "#if 0" to "#if 1" 74 * You will need a first stage bootloader then, e. g. colilo or a working BDM 75 * cable (Background Debug Mode) 76 * 77 * Setting #if 0: u-boot will start from flash and relocate itself to RAM 78 * 79 * Please do not forget to modify the setting of CONFIG_SYS_TEXT_BASE 80 * in board/cobra5272/config.mk accordingly (#if 0: 0xffe00000; #if 1: 0x20000) 81 * 82 * --- 83 */ 84 85 #if 0 86 #define CONFIG_MONITOR_IS_IN_RAM /* monitor is started from a preloader */ 87 #endif 88 89 /* --- 90 * Configuration for environment 91 * Environment is embedded in u-boot in the second sector of the flash 92 * --- 93 */ 94 95 #ifndef CONFIG_MONITOR_IS_IN_RAM 96 #define CONFIG_ENV_OFFSET 0x4000 97 #define CONFIG_ENV_SECT_SIZE 0x2000 98 #else 99 #define CONFIG_ENV_ADDR 0xffe04000 100 #define CONFIG_ENV_SECT_SIZE 0x2000 101 #endif 102 103 #define LDS_BOARD_TEXT \ 104 . = DEFINED(env_offset) ? env_offset : .; \ 105 env/embedded.o(.text); 106 107 /* 108 * BOOTP options 109 */ 110 #define CONFIG_BOOTP_BOOTFILESIZE 111 112 /* 113 * Command line configuration. 114 */ 115 116 #ifdef CONFIG_MCFFEC 117 # define CONFIG_MII 1 118 # define CONFIG_MII_INIT 1 119 # define CONFIG_SYS_DISCOVER_PHY 120 # define CONFIG_SYS_RX_ETH_BUFFER 8 121 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 122 123 # define CONFIG_SYS_FEC0_PINMUX 0 124 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 125 # define MCFFEC_TOUT_LOOP 50000 126 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 127 # ifndef CONFIG_SYS_DISCOVER_PHY 128 # define FECDUPLEX FULL 129 # define FECSPEED _100BASET 130 # else 131 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 132 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 133 # endif 134 # endif /* CONFIG_SYS_DISCOVER_PHY */ 135 #endif 136 137 /* 138 *----------------------------------------------------------------------------- 139 * Define user parameters that have to be customized most likely 140 *----------------------------------------------------------------------------- 141 */ 142 143 /*AUTOBOOT settings - booting images automatically by u-boot after power on*/ 144 145 /* The following settings will be contained in the environment block ; if you 146 want to use a neutral environment all those settings can be manually set in 147 u-boot: 'set' command */ 148 149 #if 0 150 151 #define CONFIG_BOOTCOMMAND "bootm 0xffe80000" /*Autoboto command, please 152 enter a valid image address in flash */ 153 154 /* User network settings */ 155 156 #define CONFIG_IPADDR 192.168.100.2 /* default board IP address */ 157 #define CONFIG_SERVERIP 192.168.100.1 /* default tftp server IP address */ 158 159 #endif 160 161 #define CONFIG_SYS_LOAD_ADDR 0x20000 /*Defines default RAM address 162 from which user programs will be started */ 163 164 /*---*/ 165 166 /* 167 *----------------------------------------------------------------------------- 168 * End of user parameters to be customized 169 *----------------------------------------------------------------------------- 170 */ 171 172 /* --- 173 * Defines memory range for test 174 * --- 175 */ 176 177 #define CONFIG_SYS_MEMTEST_START 0x400 178 #define CONFIG_SYS_MEMTEST_END 0x380000 179 180 /* --- 181 * Low Level Configuration Settings 182 * (address mappings, register initial values, etc.) 183 * You should know what you are doing if you make changes here. 184 * --- 185 */ 186 187 /* --- 188 * Base register address 189 * --- 190 */ 191 192 #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ 193 194 /* --- 195 * System Conf. Reg. & System Protection Reg. 196 * --- 197 */ 198 199 #define CONFIG_SYS_SCR 0x0003 200 #define CONFIG_SYS_SPR 0xffff 201 202 /* --- 203 * Ethernet settings 204 * --- 205 */ 206 207 #define CONFIG_SYS_DISCOVER_PHY 208 #define CONFIG_SYS_ENET_BD_BASE 0x780000 209 210 /*----------------------------------------------------------------------- 211 * Definitions for initial stack pointer and data area (in internal SRAM) 212 */ 213 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 214 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ 215 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 216 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 217 218 /*----------------------------------------------------------------------- 219 * Start addresses for the final memory configuration 220 * (Set up by the startup code) 221 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 222 */ 223 #define CONFIG_SYS_SDRAM_BASE 0x00000000 224 225 /* 226 *------------------------------------------------------------------------- 227 * RAM SIZE (is defined above) 228 *----------------------------------------------------------------------- 229 */ 230 231 /* #define CONFIG_SYS_SDRAM_SIZE 16 */ 232 233 /* 234 *----------------------------------------------------------------------- 235 */ 236 237 #define CONFIG_SYS_FLASH_BASE 0xffe00000 238 239 #ifdef CONFIG_MONITOR_IS_IN_RAM 240 #define CONFIG_SYS_MONITOR_BASE 0x20000 241 #else 242 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 243 #endif 244 245 #define CONFIG_SYS_MONITOR_LEN 0x20000 246 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 247 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 248 249 /* 250 * For booting Linux, the board info and command line data 251 * have to be in the first 8 MB of memory, since this is 252 * the maximum mapped by the Linux kernel during initialization ?? 253 */ 254 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 255 256 /*----------------------------------------------------------------------- 257 * FLASH organization 258 */ 259 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 260 #define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ 261 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 /* flash timeout */ 262 263 /*----------------------------------------------------------------------- 264 * Cache Configuration 265 */ 266 #define CONFIG_SYS_CACHELINE_SIZE 16 267 268 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 269 CONFIG_SYS_INIT_RAM_SIZE - 8) 270 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 271 CONFIG_SYS_INIT_RAM_SIZE - 4) 272 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) 273 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 274 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 275 CF_ACR_EN | CF_ACR_SM_ALL) 276 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ 277 CF_CACR_DISD | CF_CACR_INVI | \ 278 CF_CACR_CEIB | CF_CACR_DCM | \ 279 CF_CACR_EUSP) 280 281 /*----------------------------------------------------------------------- 282 * Memory bank definitions 283 * 284 * Please refer also to Motorola Coldfire user manual - Chapter XXX 285 * <http://e-www.motorola.com/files/dsp/doc/ref_manual/MCF5272UM.pdf> 286 */ 287 #define CONFIG_SYS_BR0_PRELIM 0xFFE00201 288 #define CONFIG_SYS_OR0_PRELIM 0xFFE00014 289 290 #define CONFIG_SYS_BR1_PRELIM 0 291 #define CONFIG_SYS_OR1_PRELIM 0 292 293 #define CONFIG_SYS_BR2_PRELIM 0 294 #define CONFIG_SYS_OR2_PRELIM 0 295 296 #define CONFIG_SYS_BR3_PRELIM 0 297 #define CONFIG_SYS_OR3_PRELIM 0 298 299 #define CONFIG_SYS_BR4_PRELIM 0 300 #define CONFIG_SYS_OR4_PRELIM 0 301 302 #define CONFIG_SYS_BR5_PRELIM 0 303 #define CONFIG_SYS_OR5_PRELIM 0 304 305 #define CONFIG_SYS_BR6_PRELIM 0 306 #define CONFIG_SYS_OR6_PRELIM 0 307 308 #define CONFIG_SYS_BR7_PRELIM 0x00000701 309 #define CONFIG_SYS_OR7_PRELIM 0xFF00007C 310 311 /*----------------------------------------------------------------------- 312 * LED config 313 */ 314 #define LED_STAT_0 0xffff /*all LEDs off*/ 315 #define LED_STAT_1 0xfffe 316 #define LED_STAT_2 0xfffd 317 #define LED_STAT_3 0xfffb 318 #define LED_STAT_4 0xfff7 319 #define LED_STAT_5 0xffef 320 #define LED_STAT_6 0xffdf 321 #define LED_STAT_7 0xff00 /*all LEDs on*/ 322 323 /*----------------------------------------------------------------------- 324 * Port configuration (GPIO) 325 */ 326 #define CONFIG_SYS_PACNT 0x00000000 /* PortA control reg.: All pins are external 327 GPIO*/ 328 #define CONFIG_SYS_PADDR 0x00FF /* PortA direction reg.: PA7 to PA0 are outputs 329 (1^=output, 0^=input) */ 330 #define CONFIG_SYS_PADAT LED_STAT_0 /* PortA value reg.: Turn all LED off */ 331 #define CONFIG_SYS_PBCNT 0x55554155 /* PortB control reg.: Ethernet/UART 332 configuration */ 333 #define CONFIG_SYS_PBDDR 0x0000 /* PortB direction: All pins configured as inputs */ 334 #define CONFIG_SYS_PBDAT 0x0000 /* PortB value reg. */ 335 #define CONFIG_SYS_PDCNT 0x00000000 /* PortD control reg. */ 336 337 #endif /* _CONFIG_COBRA5272_H */ 338