1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2a562e1bdSwdenk /* 3a562e1bdSwdenk * Configuation settings for the Sentec Cobra Board. 4a562e1bdSwdenk * 5a562e1bdSwdenk * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> 6a562e1bdSwdenk */ 7a562e1bdSwdenk 8a562e1bdSwdenk /* --- 9a187559eSBin Meng * Version: U-Boot 1.0.0 - initial release for Sentec COBRA5272 board 10a562e1bdSwdenk * Date: 2004-03-29 11a562e1bdSwdenk * Author: Florian Schlote 12a562e1bdSwdenk * 13a562e1bdSwdenk * For a description of configuration options please refer also to the 14a562e1bdSwdenk * general u-boot-1.x.x/README file 15a562e1bdSwdenk * --- 16a562e1bdSwdenk */ 17a562e1bdSwdenk 18a562e1bdSwdenk /* --- 19a562e1bdSwdenk * board/config.h - configuration options, board specific 20a562e1bdSwdenk * --- 21a562e1bdSwdenk */ 22a562e1bdSwdenk 23a562e1bdSwdenk #ifndef _CONFIG_COBRA5272_H 24a562e1bdSwdenk #define _CONFIG_COBRA5272_H 25a562e1bdSwdenk 26a562e1bdSwdenk /* --- 27a562e1bdSwdenk * Defines processor clock - important for correct timings concerning serial 28a562e1bdSwdenk * interface etc. 29a562e1bdSwdenk * --- 30a562e1bdSwdenk */ 31a562e1bdSwdenk 326d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CLK 66000000 336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 34a562e1bdSwdenk 35a562e1bdSwdenk /* --- 36a562e1bdSwdenk * Enable use of Ethernet 37a562e1bdSwdenk * --- 38a562e1bdSwdenk */ 396706424dSTsiChungLiew #define CONFIG_MCFFEC 40a562e1bdSwdenk 416706424dSTsiChungLiew /* Enable Dma Timer */ 426706424dSTsiChungLiew #define CONFIG_MCFTMR 43a562e1bdSwdenk 44a562e1bdSwdenk /* --- 45a562e1bdSwdenk * Define baudrate for UART1 (console output, tftp, ...) 46a562e1bdSwdenk * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud 476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected in u-boot command 48a562e1bdSwdenk * interface 49a562e1bdSwdenk * --- 50a562e1bdSwdenk */ 51a562e1bdSwdenk 526706424dSTsiChungLiew #define CONFIG_MCFUART 536d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_UART_PORT (0) 54a562e1bdSwdenk 55a562e1bdSwdenk /* --- 56a562e1bdSwdenk * set "#if 0" to "#if 1" if (Hardware)-WATCHDOG should be enabled & change 57a562e1bdSwdenk * timeout acc. to your needs 58a562e1bdSwdenk * #define CONFIG_WATCHDOG_TIMEOUT x , x is timeout in milliseconds, e. g. 10000 59a562e1bdSwdenk * for 10 sec 60a562e1bdSwdenk * --- 61a562e1bdSwdenk */ 62a562e1bdSwdenk 63a562e1bdSwdenk #if 0 64a562e1bdSwdenk #define CONFIG_WATCHDOG 65a562e1bdSwdenk #define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */ 66a562e1bdSwdenk #endif 67a562e1bdSwdenk 68a562e1bdSwdenk /* --- 69a562e1bdSwdenk * CONFIG_MONITOR_IS_IN_RAM defines if u-boot is started from a different 70a562e1bdSwdenk * bootloader residing in flash ('chainloading'); if you want to use 71a562e1bdSwdenk * chainloading or want to compile a u-boot binary that can be loaded into 72a562e1bdSwdenk * RAM via BDM set 73a562e1bdSwdenk * "#if 0" to "#if 1" 74a562e1bdSwdenk * You will need a first stage bootloader then, e. g. colilo or a working BDM 75a562e1bdSwdenk * cable (Background Debug Mode) 76a562e1bdSwdenk * 77a562e1bdSwdenk * Setting #if 0: u-boot will start from flash and relocate itself to RAM 78a562e1bdSwdenk * 7914d0a02aSWolfgang Denk * Please do not forget to modify the setting of CONFIG_SYS_TEXT_BASE 80a562e1bdSwdenk * in board/cobra5272/config.mk accordingly (#if 0: 0xffe00000; #if 1: 0x20000) 81a562e1bdSwdenk * 82a562e1bdSwdenk * --- 83a562e1bdSwdenk */ 84a562e1bdSwdenk 85a562e1bdSwdenk #if 0 86a562e1bdSwdenk #define CONFIG_MONITOR_IS_IN_RAM /* monitor is started from a preloader */ 87a562e1bdSwdenk #endif 88a562e1bdSwdenk 89a562e1bdSwdenk /* --- 90a562e1bdSwdenk * Configuration for environment 91a562e1bdSwdenk * Environment is embedded in u-boot in the second sector of the flash 92a562e1bdSwdenk * --- 93a562e1bdSwdenk */ 94a562e1bdSwdenk 95a562e1bdSwdenk #ifndef CONFIG_MONITOR_IS_IN_RAM 960e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_OFFSET 0x4000 970e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE 0x2000 98a562e1bdSwdenk #else 990e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR 0xffe04000 1000e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE 0x2000 101a562e1bdSwdenk #endif 102a562e1bdSwdenk 1035296cb1dSangelo@sysam.it #define LDS_BOARD_TEXT \ 1045296cb1dSangelo@sysam.it . = DEFINED(env_offset) ? env_offset : .; \ 1050649cd0dSSimon Glass env/embedded.o(.text); 10637e4f24bSJon Loeliger 10737e4f24bSJon Loeliger /* 10880ff4f99SJon Loeliger * BOOTP options 10980ff4f99SJon Loeliger */ 11080ff4f99SJon Loeliger #define CONFIG_BOOTP_BOOTFILESIZE 11180ff4f99SJon Loeliger 11280ff4f99SJon Loeliger /* 11337e4f24bSJon Loeliger * Command line configuration. 114a562e1bdSwdenk */ 115a562e1bdSwdenk 1166706424dSTsiChungLiew #ifdef CONFIG_MCFFEC 1176706424dSTsiChungLiew # define CONFIG_MII 1 1180f3ba7e9STsiChung Liew # define CONFIG_MII_INIT 1 1196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD # define CONFIG_SYS_DISCOVER_PHY 1206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD # define CONFIG_SYS_RX_ETH_BUFFER 8 1216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1226706424dSTsiChungLiew 1236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD # define CONFIG_SYS_FEC0_PINMUX 0 1246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 1256706424dSTsiChungLiew # define MCFFEC_TOUT_LOOP 50000 1266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 1276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD # ifndef CONFIG_SYS_DISCOVER_PHY 1286706424dSTsiChungLiew # define FECDUPLEX FULL 1296706424dSTsiChungLiew # define FECSPEED _100BASET 1306706424dSTsiChungLiew # else 1316d0f6bcfSJean-Christophe PLAGNIOL-VILLARD # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1326d0f6bcfSJean-Christophe PLAGNIOL-VILLARD # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1336706424dSTsiChungLiew # endif 1346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD # endif /* CONFIG_SYS_DISCOVER_PHY */ 1356706424dSTsiChungLiew #endif 136a562e1bdSwdenk 137a562e1bdSwdenk /* 138a562e1bdSwdenk *----------------------------------------------------------------------------- 139a562e1bdSwdenk * Define user parameters that have to be customized most likely 140a562e1bdSwdenk *----------------------------------------------------------------------------- 141a562e1bdSwdenk */ 142a562e1bdSwdenk 143a562e1bdSwdenk /*AUTOBOOT settings - booting images automatically by u-boot after power on*/ 144a562e1bdSwdenk 145a562e1bdSwdenk /* The following settings will be contained in the environment block ; if you 146a562e1bdSwdenk want to use a neutral environment all those settings can be manually set in 147a562e1bdSwdenk u-boot: 'set' command */ 148a562e1bdSwdenk 149a562e1bdSwdenk #if 0 150a562e1bdSwdenk 151a562e1bdSwdenk #define CONFIG_BOOTCOMMAND "bootm 0xffe80000" /*Autoboto command, please 152a562e1bdSwdenk enter a valid image address in flash */ 153a562e1bdSwdenk 154a562e1bdSwdenk /* User network settings */ 155a562e1bdSwdenk 156a562e1bdSwdenk #define CONFIG_IPADDR 192.168.100.2 /* default board IP address */ 157a562e1bdSwdenk #define CONFIG_SERVERIP 192.168.100.1 /* default tftp server IP address */ 158a562e1bdSwdenk 159a562e1bdSwdenk #endif 160a562e1bdSwdenk 1616d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR 0x20000 /*Defines default RAM address 162a562e1bdSwdenk from which user programs will be started */ 163a562e1bdSwdenk 164a562e1bdSwdenk /*---*/ 165a562e1bdSwdenk 166a562e1bdSwdenk /* 167a562e1bdSwdenk *----------------------------------------------------------------------------- 168a562e1bdSwdenk * End of user parameters to be customized 169a562e1bdSwdenk *----------------------------------------------------------------------------- 170a562e1bdSwdenk */ 171a562e1bdSwdenk 172a562e1bdSwdenk /* --- 173a562e1bdSwdenk * Defines memory range for test 174a562e1bdSwdenk * --- 175a562e1bdSwdenk */ 176a562e1bdSwdenk 1776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START 0x400 1786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END 0x380000 179a562e1bdSwdenk 180a562e1bdSwdenk /* --- 181a562e1bdSwdenk * Low Level Configuration Settings 182a562e1bdSwdenk * (address mappings, register initial values, etc.) 183a562e1bdSwdenk * You should know what you are doing if you make changes here. 184a562e1bdSwdenk * --- 185a562e1bdSwdenk */ 186a562e1bdSwdenk 187a562e1bdSwdenk /* --- 188a562e1bdSwdenk * Base register address 189a562e1bdSwdenk * --- 190a562e1bdSwdenk */ 191a562e1bdSwdenk 1926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ 193a562e1bdSwdenk 194a562e1bdSwdenk /* --- 195a562e1bdSwdenk * System Conf. Reg. & System Protection Reg. 196a562e1bdSwdenk * --- 197a562e1bdSwdenk */ 198a562e1bdSwdenk 1996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCR 0x0003 2006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPR 0xffff 201a562e1bdSwdenk 202a562e1bdSwdenk /* --- 203a562e1bdSwdenk * Ethernet settings 204a562e1bdSwdenk * --- 205a562e1bdSwdenk */ 206a562e1bdSwdenk 2076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DISCOVER_PHY 2086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ENET_BD_BASE 0x780000 209a562e1bdSwdenk 210a562e1bdSwdenk /*----------------------------------------------------------------------- 211a562e1bdSwdenk * Definitions for initial stack pointer and data area (in internal SRAM) 212a562e1bdSwdenk */ 2136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 214553f0982SWolfgang Denk #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ 21525ddd1fbSWolfgang Denk #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 2166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 217a562e1bdSwdenk 218a562e1bdSwdenk /*----------------------------------------------------------------------- 219a562e1bdSwdenk * Start addresses for the final memory configuration 220a562e1bdSwdenk * (Set up by the startup code) 2216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 222a562e1bdSwdenk */ 2236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE 0x00000000 224a562e1bdSwdenk 225a562e1bdSwdenk /* 226a562e1bdSwdenk *------------------------------------------------------------------------- 227a562e1bdSwdenk * RAM SIZE (is defined above) 228a562e1bdSwdenk *----------------------------------------------------------------------- 229a562e1bdSwdenk */ 230a562e1bdSwdenk 2316d0f6bcfSJean-Christophe PLAGNIOL-VILLARD /* #define CONFIG_SYS_SDRAM_SIZE 16 */ 232a562e1bdSwdenk 233a562e1bdSwdenk /* 234a562e1bdSwdenk *----------------------------------------------------------------------- 235a562e1bdSwdenk */ 236a562e1bdSwdenk 2376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE 0xffe00000 238a562e1bdSwdenk 239a562e1bdSwdenk #ifdef CONFIG_MONITOR_IS_IN_RAM 2406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_BASE 0x20000 241a562e1bdSwdenk #else 2426d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 243a562e1bdSwdenk #endif 244a562e1bdSwdenk 2456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_LEN 0x20000 2466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN (256 << 10) 2476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 248a562e1bdSwdenk 249a562e1bdSwdenk /* 250a562e1bdSwdenk * For booting Linux, the board info and command line data 251a562e1bdSwdenk * have to be in the first 8 MB of memory, since this is 252a562e1bdSwdenk * the maximum mapped by the Linux kernel during initialization ?? 253a562e1bdSwdenk */ 2546d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 255a562e1bdSwdenk 256a562e1bdSwdenk /*----------------------------------------------------------------------- 257a562e1bdSwdenk * FLASH organization 258a562e1bdSwdenk */ 2596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 2606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ 2616d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 /* flash timeout */ 262a562e1bdSwdenk 263a562e1bdSwdenk /*----------------------------------------------------------------------- 264a562e1bdSwdenk * Cache Configuration 265a562e1bdSwdenk */ 2666d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CACHELINE_SIZE 16 267a562e1bdSwdenk 268dd9f054eSTsiChung Liew #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 269553f0982SWolfgang Denk CONFIG_SYS_INIT_RAM_SIZE - 8) 270dd9f054eSTsiChung Liew #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 271553f0982SWolfgang Denk CONFIG_SYS_INIT_RAM_SIZE - 4) 272dd9f054eSTsiChung Liew #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) 273dd9f054eSTsiChung Liew #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 274dd9f054eSTsiChung Liew CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 275dd9f054eSTsiChung Liew CF_ACR_EN | CF_ACR_SM_ALL) 276dd9f054eSTsiChung Liew #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ 277dd9f054eSTsiChung Liew CF_CACR_DISD | CF_CACR_INVI | \ 278dd9f054eSTsiChung Liew CF_CACR_CEIB | CF_CACR_DCM | \ 279dd9f054eSTsiChung Liew CF_CACR_EUSP) 280dd9f054eSTsiChung Liew 281a562e1bdSwdenk /*----------------------------------------------------------------------- 282a562e1bdSwdenk * Memory bank definitions 283a562e1bdSwdenk * 284a562e1bdSwdenk * Please refer also to Motorola Coldfire user manual - Chapter XXX 285a562e1bdSwdenk * <http://e-www.motorola.com/files/dsp/doc/ref_manual/MCF5272UM.pdf> 286a562e1bdSwdenk */ 2876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR0_PRELIM 0xFFE00201 2886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR0_PRELIM 0xFFE00014 289a562e1bdSwdenk 2906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR1_PRELIM 0 2916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR1_PRELIM 0 292a562e1bdSwdenk 2936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR2_PRELIM 0 2946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR2_PRELIM 0 295a562e1bdSwdenk 2966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR3_PRELIM 0 2976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR3_PRELIM 0 298a562e1bdSwdenk 2996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR4_PRELIM 0 3006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR4_PRELIM 0 301a562e1bdSwdenk 3026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR5_PRELIM 0 3036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR5_PRELIM 0 304a562e1bdSwdenk 3056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR6_PRELIM 0 3066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR6_PRELIM 0 307a562e1bdSwdenk 3086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR7_PRELIM 0x00000701 3096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR7_PRELIM 0xFF00007C 310a562e1bdSwdenk 311a562e1bdSwdenk /*----------------------------------------------------------------------- 312a562e1bdSwdenk * LED config 313a562e1bdSwdenk */ 314a562e1bdSwdenk #define LED_STAT_0 0xffff /*all LEDs off*/ 315a562e1bdSwdenk #define LED_STAT_1 0xfffe 316a562e1bdSwdenk #define LED_STAT_2 0xfffd 317a562e1bdSwdenk #define LED_STAT_3 0xfffb 318a562e1bdSwdenk #define LED_STAT_4 0xfff7 319a562e1bdSwdenk #define LED_STAT_5 0xffef 320a562e1bdSwdenk #define LED_STAT_6 0xffdf 321a562e1bdSwdenk #define LED_STAT_7 0xff00 /*all LEDs on*/ 322a562e1bdSwdenk 323a562e1bdSwdenk /*----------------------------------------------------------------------- 324a562e1bdSwdenk * Port configuration (GPIO) 325a562e1bdSwdenk */ 3266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PACNT 0x00000000 /* PortA control reg.: All pins are external 327a562e1bdSwdenk GPIO*/ 3286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PADDR 0x00FF /* PortA direction reg.: PA7 to PA0 are outputs 329a562e1bdSwdenk (1^=output, 0^=input) */ 3306d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PADAT LED_STAT_0 /* PortA value reg.: Turn all LED off */ 3316d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PBCNT 0x55554155 /* PortB control reg.: Ethernet/UART 332a562e1bdSwdenk configuration */ 3336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PBDDR 0x0000 /* PortB direction: All pins configured as inputs */ 3346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PBDAT 0x0000 /* PortB value reg. */ 3356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PDCNT 0x00000000 /* PortD control reg. */ 336a562e1bdSwdenk 337a562e1bdSwdenk #endif /* _CONFIG_COBRA5272_H */ 338