xref: /openbmc/u-boot/include/configs/cobra5272.h (revision 1a459660)
1a562e1bdSwdenk /*
2a562e1bdSwdenk  * Configuation settings for the Sentec Cobra Board.
3a562e1bdSwdenk  *
4a562e1bdSwdenk  * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
5a562e1bdSwdenk  *
6*1a459660SWolfgang Denk  * SPDX-License-Identifier:	GPL-2.0+
7a562e1bdSwdenk  */
8a562e1bdSwdenk 
9a562e1bdSwdenk /* ---
10a562e1bdSwdenk  * Version: U-boot 1.0.0 - initial release for Sentec COBRA5272 board
11a562e1bdSwdenk  * Date: 2004-03-29
12a562e1bdSwdenk  * Author: Florian Schlote
13a562e1bdSwdenk  *
14a562e1bdSwdenk  * For a description of configuration options please refer also to the
15a562e1bdSwdenk  * general u-boot-1.x.x/README file
16a562e1bdSwdenk  * ---
17a562e1bdSwdenk  */
18a562e1bdSwdenk 
19a562e1bdSwdenk /* ---
20a562e1bdSwdenk  * board/config.h - configuration options, board specific
21a562e1bdSwdenk  * ---
22a562e1bdSwdenk  */
23a562e1bdSwdenk 
24a562e1bdSwdenk #ifndef _CONFIG_COBRA5272_H
25a562e1bdSwdenk #define _CONFIG_COBRA5272_H
26a562e1bdSwdenk 
27a562e1bdSwdenk /* ---
28a562e1bdSwdenk  * Define processor
29a562e1bdSwdenk  * possible values for Sentec board: only Coldfire M5272 processor supported
30a562e1bdSwdenk  * (please do not change)
31a562e1bdSwdenk  * ---
32a562e1bdSwdenk  */
33a562e1bdSwdenk 
34a562e1bdSwdenk #define CONFIG_MCF52x2			/* define processor family */
35a562e1bdSwdenk #define CONFIG_M5272			/* define processor type */
36a562e1bdSwdenk 
37a562e1bdSwdenk /* ---
38a562e1bdSwdenk  * Defines processor clock - important for correct timings concerning serial
39a562e1bdSwdenk  * interface etc.
406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD  * CONFIG_SYS_HZ gives unit: 1000 -> 1 Hz ^= 1000 ms
41a562e1bdSwdenk  * ---
42a562e1bdSwdenk  */
43a562e1bdSwdenk 
446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HZ			1000
456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CLK			66000000
466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_SIZE		16		/* SDRAM size in MB */
47a562e1bdSwdenk 
48a562e1bdSwdenk /* ---
49a562e1bdSwdenk  * Enable use of Ethernet
50a562e1bdSwdenk  * ---
51a562e1bdSwdenk  */
526706424dSTsiChungLiew #define CONFIG_MCFFEC
53a562e1bdSwdenk 
546706424dSTsiChungLiew /* Enable Dma Timer */
556706424dSTsiChungLiew #define CONFIG_MCFTMR
56a562e1bdSwdenk 
57a562e1bdSwdenk /* ---
58a562e1bdSwdenk  * Define baudrate for UART1 (console output, tftp, ...)
59a562e1bdSwdenk  * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud
606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD  * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected in u-boot command
61a562e1bdSwdenk  * interface
62a562e1bdSwdenk  * ---
63a562e1bdSwdenk  */
64a562e1bdSwdenk 
656706424dSTsiChungLiew #define CONFIG_MCFUART
666d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_UART_PORT		(0)
67a562e1bdSwdenk #define CONFIG_BAUDRATE		19200
68a562e1bdSwdenk 
69a562e1bdSwdenk /* ---
70a562e1bdSwdenk  * set "#if 0" to "#if 1" if (Hardware)-WATCHDOG should be enabled & change
71a562e1bdSwdenk  * timeout acc. to your needs
72a562e1bdSwdenk  * #define CONFIG_WATCHDOG_TIMEOUT x , x is timeout in milliseconds, e. g. 10000
73a562e1bdSwdenk  * for 10 sec
74a562e1bdSwdenk  * ---
75a562e1bdSwdenk  */
76a562e1bdSwdenk 
77a562e1bdSwdenk #if 0
78a562e1bdSwdenk #define CONFIG_WATCHDOG
79a562e1bdSwdenk #define CONFIG_WATCHDOG_TIMEOUT 10000	/* timeout in milliseconds */
80a562e1bdSwdenk #endif
81a562e1bdSwdenk 
82a562e1bdSwdenk /* ---
83a562e1bdSwdenk  * CONFIG_MONITOR_IS_IN_RAM defines if u-boot is started from a different
84a562e1bdSwdenk  * bootloader residing in flash ('chainloading'); if you want to use
85a562e1bdSwdenk  * chainloading or want to compile a u-boot binary that can be loaded into
86a562e1bdSwdenk  * RAM via BDM set
87a562e1bdSwdenk  *	"#if 0" to "#if 1"
88a562e1bdSwdenk  * You will need a first stage bootloader then, e. g. colilo or a working BDM
89a562e1bdSwdenk  * cable (Background Debug Mode)
90a562e1bdSwdenk  *
91a562e1bdSwdenk  * Setting #if 0: u-boot will start from flash and relocate itself to RAM
92a562e1bdSwdenk  *
9314d0a02aSWolfgang Denk  * Please do not forget to modify the setting of CONFIG_SYS_TEXT_BASE
94a562e1bdSwdenk  * in board/cobra5272/config.mk accordingly (#if 0: 0xffe00000; #if 1: 0x20000)
95a562e1bdSwdenk  *
96a562e1bdSwdenk  * ---
97a562e1bdSwdenk  */
98a562e1bdSwdenk 
99a562e1bdSwdenk #if 0
100a562e1bdSwdenk #define CONFIG_MONITOR_IS_IN_RAM /* monitor is started from a preloader */
101a562e1bdSwdenk #endif
102a562e1bdSwdenk 
103a562e1bdSwdenk /* ---
104a562e1bdSwdenk  * Configuration for environment
105a562e1bdSwdenk  * Environment is embedded in u-boot in the second sector of the flash
106a562e1bdSwdenk  * ---
107a562e1bdSwdenk  */
108a562e1bdSwdenk 
109a562e1bdSwdenk #ifndef CONFIG_MONITOR_IS_IN_RAM
1100e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_OFFSET		0x4000
1110e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE	0x2000
1125a1aceb0SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_FLASH	1
113a562e1bdSwdenk #else
1140e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR		0xffe04000
1150e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE	0x2000
1165a1aceb0SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_FLASH	1
117a562e1bdSwdenk #endif
118a562e1bdSwdenk 
11937e4f24bSJon Loeliger 
12037e4f24bSJon Loeliger /*
12180ff4f99SJon Loeliger  * BOOTP options
12280ff4f99SJon Loeliger  */
12380ff4f99SJon Loeliger #define CONFIG_BOOTP_BOOTFILESIZE
12480ff4f99SJon Loeliger #define CONFIG_BOOTP_BOOTPATH
12580ff4f99SJon Loeliger #define CONFIG_BOOTP_GATEWAY
12680ff4f99SJon Loeliger #define CONFIG_BOOTP_HOSTNAME
12780ff4f99SJon Loeliger 
12880ff4f99SJon Loeliger 
12980ff4f99SJon Loeliger /*
13037e4f24bSJon Loeliger  * Command line configuration.
131a562e1bdSwdenk  */
13237e4f24bSJon Loeliger #include <config_cmd_default.h>
133a562e1bdSwdenk 
13437e4f24bSJon Loeliger #define CONFIG_CMD_PING
135a562e1bdSwdenk 
13637e4f24bSJon Loeliger #undef CONFIG_CMD_LOADS
13737e4f24bSJon Loeliger #undef CONFIG_CMD_LOADB
13837e4f24bSJon Loeliger #undef CONFIG_CMD_MII
13937e4f24bSJon Loeliger 
1406706424dSTsiChungLiew #ifdef CONFIG_MCFFEC
1416706424dSTsiChungLiew #	define CONFIG_MII		1
1420f3ba7e9STsiChung Liew #	define CONFIG_MII_INIT		1
1436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #	define CONFIG_SYS_DISCOVER_PHY
1446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #	define CONFIG_SYS_RX_ETH_BUFFER	8
1456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
1466706424dSTsiChungLiew 
1476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #	define CONFIG_SYS_FEC0_PINMUX		0
1486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
1496706424dSTsiChungLiew #	define MCFFEC_TOUT_LOOP		50000
1506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
1516d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #	ifndef CONFIG_SYS_DISCOVER_PHY
1526706424dSTsiChungLiew #		define FECDUPLEX	FULL
1536706424dSTsiChungLiew #		define FECSPEED		_100BASET
1546706424dSTsiChungLiew #	else
1556d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
1566d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
1576706424dSTsiChungLiew #		endif
1586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #	endif			/* CONFIG_SYS_DISCOVER_PHY */
1596706424dSTsiChungLiew #endif
160a562e1bdSwdenk 
161a562e1bdSwdenk /*
162a562e1bdSwdenk  *-----------------------------------------------------------------------------
163a562e1bdSwdenk  * Define user parameters that have to be customized most likely
164a562e1bdSwdenk  *-----------------------------------------------------------------------------
165a562e1bdSwdenk  */
166a562e1bdSwdenk 
167a562e1bdSwdenk /*AUTOBOOT settings - booting images automatically by u-boot after power on*/
168a562e1bdSwdenk 
169a562e1bdSwdenk #define CONFIG_BOOTDELAY	5		/* used for autoboot, delay in
170a562e1bdSwdenk seconds u-boot will wait before starting defined (auto-)boot command, setting
171a562e1bdSwdenk to -1 disables delay, setting to 0 will too prevent access to u-boot command
172a562e1bdSwdenk interface: u-boot then has to reflashed */
173a562e1bdSwdenk 
174a562e1bdSwdenk 
175a562e1bdSwdenk /* The following settings will be contained in the environment block ; if you
176a562e1bdSwdenk want to use a neutral environment all those settings can be manually set in
177a562e1bdSwdenk u-boot: 'set' command */
178a562e1bdSwdenk 
179a562e1bdSwdenk #if 0
180a562e1bdSwdenk 
181a562e1bdSwdenk #define CONFIG_BOOTCOMMAND	"bootm 0xffe80000"	/*Autoboto command, please
182a562e1bdSwdenk enter a valid image address in flash */
183a562e1bdSwdenk 
184a562e1bdSwdenk #define CONFIG_BOOTARGS		" "			/* default bootargs that are
185a562e1bdSwdenk considered during boot */
186a562e1bdSwdenk 
187a562e1bdSwdenk /* User network settings */
188a562e1bdSwdenk 
189a562e1bdSwdenk #define CONFIG_ETHADDR 00:00:00:00:00:09	/* default ethernet MAC addr. */
190a562e1bdSwdenk #define CONFIG_IPADDR 192.168.100.2		/* default board IP address */
191a562e1bdSwdenk #define CONFIG_SERVERIP 192.168.100.1	/* default tftp server IP address */
192a562e1bdSwdenk 
193a562e1bdSwdenk #endif
194a562e1bdSwdenk 
1956d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT		"COBRA > "	/* Layout of u-boot prompt*/
196a562e1bdSwdenk 
1976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR		0x20000		/*Defines default RAM address
198a562e1bdSwdenk from which user programs will be started */
199a562e1bdSwdenk 
200a562e1bdSwdenk /*---*/
201a562e1bdSwdenk 
2026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
203a562e1bdSwdenk 
20437e4f24bSJon Loeliger #if defined(CONFIG_CMD_KGDB)
2056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size	*/
206a562e1bdSwdenk #else
2076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
208a562e1bdSwdenk #endif
2096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
2106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
2116d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
212a562e1bdSwdenk 
213a562e1bdSwdenk /*
214a562e1bdSwdenk  *-----------------------------------------------------------------------------
215a562e1bdSwdenk  * End of user parameters to be customized
216a562e1bdSwdenk  *-----------------------------------------------------------------------------
217a562e1bdSwdenk  */
218a562e1bdSwdenk 
219a562e1bdSwdenk /* ---
220a562e1bdSwdenk  * Defines memory range for test
221a562e1bdSwdenk  * ---
222a562e1bdSwdenk  */
223a562e1bdSwdenk 
2246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START	0x400
2256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END		0x380000
226a562e1bdSwdenk 
227a562e1bdSwdenk /* ---
228a562e1bdSwdenk  * Low Level Configuration Settings
229a562e1bdSwdenk  * (address mappings, register initial values, etc.)
230a562e1bdSwdenk  * You should know what you are doing if you make changes here.
231a562e1bdSwdenk  * ---
232a562e1bdSwdenk  */
233a562e1bdSwdenk 
234a562e1bdSwdenk /* ---
235a562e1bdSwdenk  * Base register address
236a562e1bdSwdenk  * ---
237a562e1bdSwdenk  */
238a562e1bdSwdenk 
2396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MBAR		0x10000000	/* Register Base Addrs */
240a562e1bdSwdenk 
241a562e1bdSwdenk /* ---
242a562e1bdSwdenk  * System Conf. Reg. & System Protection Reg.
243a562e1bdSwdenk  * ---
244a562e1bdSwdenk  */
245a562e1bdSwdenk 
2466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCR			0x0003
2476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPR			0xffff
248a562e1bdSwdenk 
249a562e1bdSwdenk /* ---
250a562e1bdSwdenk  * Ethernet settings
251a562e1bdSwdenk  * ---
252a562e1bdSwdenk  */
253a562e1bdSwdenk 
2546d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DISCOVER_PHY
2556d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ENET_BD_BASE	0x780000
256a562e1bdSwdenk 
257a562e1bdSwdenk /*-----------------------------------------------------------------------
258a562e1bdSwdenk  * Definitions for initial stack pointer and data area (in internal SRAM)
259a562e1bdSwdenk  */
2606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
261553f0982SWolfgang Denk #define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM	*/
26225ddd1fbSWolfgang Denk #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
2636d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
264a562e1bdSwdenk 
265a562e1bdSwdenk /*-----------------------------------------------------------------------
266a562e1bdSwdenk  * Start addresses for the final memory configuration
267a562e1bdSwdenk  * (Set up by the startup code)
2686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
269a562e1bdSwdenk  */
2706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE		0x00000000
271a562e1bdSwdenk 
272a562e1bdSwdenk /*
273a562e1bdSwdenk  *-------------------------------------------------------------------------
274a562e1bdSwdenk  * RAM SIZE (is defined above)
275a562e1bdSwdenk  *-----------------------------------------------------------------------
276a562e1bdSwdenk  */
277a562e1bdSwdenk 
2786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD /* #define CONFIG_SYS_SDRAM_SIZE		16 */
279a562e1bdSwdenk 
280a562e1bdSwdenk /*
281a562e1bdSwdenk  *-----------------------------------------------------------------------
282a562e1bdSwdenk  */
283a562e1bdSwdenk 
2846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE		0xffe00000
285a562e1bdSwdenk 
286a562e1bdSwdenk #ifdef	CONFIG_MONITOR_IS_IN_RAM
2876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_BASE	0x20000
288a562e1bdSwdenk #else
2896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
290a562e1bdSwdenk #endif
291a562e1bdSwdenk 
2926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_LEN		0x20000
2936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN		(256 << 10)
2946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
295a562e1bdSwdenk 
296a562e1bdSwdenk /*
297a562e1bdSwdenk  * For booting Linux, the board info and command line data
298a562e1bdSwdenk  * have to be in the first 8 MB of memory, since this is
299a562e1bdSwdenk  * the maximum mapped by the Linux kernel during initialization ??
300a562e1bdSwdenk  */
3016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
302a562e1bdSwdenk 
303a562e1bdSwdenk /*-----------------------------------------------------------------------
304a562e1bdSwdenk  * FLASH organization
305a562e1bdSwdenk  */
3066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
3076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_SECT	11	/* max number of sectors on one chip	*/
3086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT	1000	/* flash timeout */
309a562e1bdSwdenk 
310a562e1bdSwdenk /*-----------------------------------------------------------------------
311a562e1bdSwdenk  * Cache Configuration
312a562e1bdSwdenk  */
3136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CACHELINE_SIZE	16
314a562e1bdSwdenk 
315dd9f054eSTsiChung Liew #define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
316553f0982SWolfgang Denk 					 CONFIG_SYS_INIT_RAM_SIZE - 8)
317dd9f054eSTsiChung Liew #define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
318553f0982SWolfgang Denk 					 CONFIG_SYS_INIT_RAM_SIZE - 4)
319dd9f054eSTsiChung Liew #define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
320dd9f054eSTsiChung Liew #define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
321dd9f054eSTsiChung Liew 					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
322dd9f054eSTsiChung Liew 					 CF_ACR_EN | CF_ACR_SM_ALL)
323dd9f054eSTsiChung Liew #define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
324dd9f054eSTsiChung Liew 					 CF_CACR_DISD | CF_CACR_INVI | \
325dd9f054eSTsiChung Liew 					 CF_CACR_CEIB | CF_CACR_DCM | \
326dd9f054eSTsiChung Liew 					 CF_CACR_EUSP)
327dd9f054eSTsiChung Liew 
328a562e1bdSwdenk /*-----------------------------------------------------------------------
329a562e1bdSwdenk  * Memory bank definitions
330a562e1bdSwdenk  *
331a562e1bdSwdenk  * Please refer also to Motorola Coldfire user manual - Chapter XXX
332a562e1bdSwdenk  * <http://e-www.motorola.com/files/dsp/doc/ref_manual/MCF5272UM.pdf>
333a562e1bdSwdenk  */
3346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR0_PRELIM		0xFFE00201
3356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR0_PRELIM		0xFFE00014
336a562e1bdSwdenk 
3376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR1_PRELIM		0
3386d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR1_PRELIM		0
339a562e1bdSwdenk 
3406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR2_PRELIM		0
3416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR2_PRELIM		0
342a562e1bdSwdenk 
3436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR3_PRELIM		0
3446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR3_PRELIM		0
345a562e1bdSwdenk 
3466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR4_PRELIM		0
3476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR4_PRELIM		0
348a562e1bdSwdenk 
3496d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR5_PRELIM		0
3506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR5_PRELIM		0
351a562e1bdSwdenk 
3526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR6_PRELIM		0
3536d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR6_PRELIM		0
354a562e1bdSwdenk 
3556d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR7_PRELIM		0x00000701
3566d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR7_PRELIM		0xFF00007C
357a562e1bdSwdenk 
358a562e1bdSwdenk /*-----------------------------------------------------------------------
359a562e1bdSwdenk  * LED config
360a562e1bdSwdenk  */
361a562e1bdSwdenk #define	LED_STAT_0	0xffff /*all LEDs off*/
362a562e1bdSwdenk #define	LED_STAT_1	0xfffe
363a562e1bdSwdenk #define	LED_STAT_2	0xfffd
364a562e1bdSwdenk #define	LED_STAT_3	0xfffb
365a562e1bdSwdenk #define	LED_STAT_4	0xfff7
366a562e1bdSwdenk #define	LED_STAT_5	0xffef
367a562e1bdSwdenk #define	LED_STAT_6	0xffdf
368a562e1bdSwdenk #define	LED_STAT_7	0xff00 /*all LEDs on*/
369a562e1bdSwdenk 
370a562e1bdSwdenk /*-----------------------------------------------------------------------
371a562e1bdSwdenk  * Port configuration (GPIO)
372a562e1bdSwdenk  */
3736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PACNT		0x00000000		/* PortA control reg.: All pins are external
374a562e1bdSwdenk GPIO*/
3756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PADDR		0x00FF			/* PortA direction reg.: PA7 to PA0 are outputs
376a562e1bdSwdenk (1^=output, 0^=input) */
3776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PADAT		LED_STAT_0		/* PortA value reg.: Turn all LED off */
3786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PBCNT		0x55554155		/* PortB control reg.: Ethernet/UART
379a562e1bdSwdenk configuration */
3806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PBDDR		0x0000			/* PortB direction: All pins configured as inputs */
3816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PBDAT		0x0000			/* PortB value reg. */
3826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PDCNT		0x00000000		/* PortD control reg. */
383a562e1bdSwdenk 
384a562e1bdSwdenk #endif	/* _CONFIG_COBRA5272_H */
385