1 /* 2 * cm_t43.h 3 * 4 * Copyright (C) 2015 Compulab, Ltd. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_CM_T43_H 10 #define __CONFIG_CM_T43_H 11 12 #define CONFIG_CM_T43 13 #define CONFIG_ARCH_CPU_INIT 14 #define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2GB */ 15 #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ 16 17 #include <asm/arch/omap.h> 18 19 /* Serial support */ 20 #define CONFIG_SYS_NS16550_SERIAL 21 #define CONFIG_SYS_NS16550_CLK 48000000 22 #define CONFIG_SYS_NS16550_COM1 0x44e09000 23 #if !defined(CONFIG_SPL_DM) || !defined(CONFIG_DM_SERIAL) 24 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 25 #endif 26 27 /* NAND support */ 28 #define CONFIG_NAND 29 #define CONFIG_NAND_OMAP_ELM 30 #define CONFIG_SYS_NAND_ONFI_DETECTION 31 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 32 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 33 #define CONFIG_SYS_NAND_OOBSIZE 64 34 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 35 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 36 #define CONFIG_SYS_NAND_ECCSIZE 512 37 #define CONFIG_SYS_NAND_ECCBYTES 14 38 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW 39 #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ 40 CONFIG_SYS_NAND_PAGE_SIZE) 41 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 42 10, 11, 12, 13, 14, 15, 16, 17, \ 43 18, 19, 20, 21, 22, 23, 24, 25, \ 44 26, 27, 28, 29, 30, 31, 32, 33, \ 45 34, 35, 36, 37, 38, 39, 40, 41, \ 46 42, 43, 44, 45, 46, 47, 48, 49, \ 47 50, 51, 52, 53, 54, 55, 56, 57, } 48 49 /* CPSW Ethernet support */ 50 #define CONFIG_DRIVER_TI_CPSW 51 #define CONFIG_MII 52 #define CONFIG_BOOTP_DEFAULT 53 #define CONFIG_BOOTP_SEND_HOSTNAME 54 #define CONFIG_BOOTP_GATEWAY 55 #define CONFIG_NET_MULTI 56 #define CONFIG_PHY_ATHEROS 57 #define CONFIG_SYS_RX_ETH_BUFFER 64 58 59 /* USB support */ 60 #define CONFIG_USB_XHCI_OMAP 61 #define CONFIG_OMAP_USB_PHY 62 #define CONFIG_AM437X_USB2PHY2_HOST 63 64 /* SPI Flash support */ 65 #define CONFIG_TI_SPI_MMAP 66 #define CONFIG_SF_DEFAULT_SPEED 48000000 67 #define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3 68 69 /* Power */ 70 #define CONFIG_POWER 71 #define CONFIG_POWER_I2C 72 #define CONFIG_POWER_TPS65218 73 74 /* Enabling L2 Cache */ 75 #define CONFIG_SYS_L2_PL310 76 #define CONFIG_SYS_PL310_BASE 0x48242000 77 78 /* 79 * Since SPL did pll and ddr initialization for us, 80 * we don't need to do it twice. 81 */ 82 #if !defined(CONFIG_SPL_BUILD) 83 #define CONFIG_SKIP_LOWLEVEL_INIT 84 #endif 85 86 #define CONFIG_HSMMC2_8BIT 87 88 #include <configs/ti_armv7_omap.h> 89 #undef CONFIG_SYS_MONITOR_LEN 90 91 #define CONFIG_ENV_SIZE (16 * 1024) 92 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 93 94 #define V_OSCK 24000000 /* Clock output from T2 */ 95 #define V_SCLK (V_OSCK) 96 97 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 98 #define CONFIG_ENV_OFFSET (768 * 1024) 99 #define CONFIG_ENV_SPI_MAX_HZ 48000000 100 101 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 102 103 #define CONFIG_EXTRA_ENV_SETTINGS \ 104 "loadaddr=0x80200000\0" \ 105 "fdtaddr=0x81200000\0" \ 106 "bootm_size=0x8000000\0" \ 107 "autoload=no\0" \ 108 "console=ttyO0,115200n8\0" \ 109 "fdtfile=am437x-sb-som-t43.dtb\0" \ 110 "kernel=zImage-cm-t43\0" \ 111 "bootscr=bootscr.img\0" \ 112 "emmcroot=/dev/mmcblk0p2 rw\0" \ 113 "emmcrootfstype=ext4 rootwait\0" \ 114 "emmcargs=setenv bootargs console=${console} " \ 115 "root=${emmcroot} " \ 116 "rootfstype=${emmcrootfstype}\0" \ 117 "loadbootscript=load mmc 0 ${loadaddr} ${bootscr}\0" \ 118 "bootscript=echo Running bootscript from mmc ...; " \ 119 "source ${loadaddr}\0" \ 120 "emmcboot=echo Booting from emmc ... && " \ 121 "run emmcargs && " \ 122 "load mmc 1 ${loadaddr} ${kernel} && " \ 123 "load mmc 1 ${fdtaddr} ${fdtfile} && " \ 124 "bootz ${loadaddr} - ${fdtaddr}\0" 125 126 #define CONFIG_BOOTCOMMAND \ 127 "mmc dev 0; " \ 128 "if mmc rescan; then " \ 129 "if run loadbootscript; then " \ 130 "run bootscript; " \ 131 "fi; " \ 132 "fi; " \ 133 "mmc dev 1; " \ 134 "if mmc rescan; then " \ 135 "run emmcboot; " \ 136 "fi;" 137 138 #define CONFIG_CONS_INDEX 1 139 140 /* SPL defines. */ 141 #define CONFIG_SPL_TEXT_BASE 0x40300350 142 #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + (128 << 20)) 143 #define CONFIG_SYS_SPI_U_BOOT_OFFS (256 * 1024) 144 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 145 #define CONFIG_SPL_SPI_LOAD 146 147 /* EEPROM */ 148 #define CONFIG_ENV_EEPROM_IS_ON_I2C 149 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 150 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 151 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 152 #define CONFIG_SYS_EEPROM_SIZE 256 153 154 #endif /* __CONFIG_CM_T43_H */ 155