1 /* 2 * (C) Copyright 2013 CompuLab, Ltd. 3 * Author: Igor Grinberg <grinberg@compulab.co.il> 4 * 5 * Configuration settings for the CompuLab CM-T3517 board 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 /* 14 * High Level Configuration Options 15 */ 16 #define CONFIG_OMAP /* in a TI OMAP core */ 17 #define CONFIG_CM_T3517 /* working with CM-T3517 */ 18 #define CONFIG_OMAP_COMMON 19 /* Common ARM Erratas */ 20 #define CONFIG_ARM_ERRATA_454179 21 #define CONFIG_ARM_ERRATA_430973 22 #define CONFIG_ARM_ERRATA_621766 23 24 #define CONFIG_SYS_TEXT_BASE 0x80008000 25 26 /* 27 * This is needed for the DMA stuff. 28 * Although the default iss 64, we still define it 29 * to be on the safe side once the default is changed. 30 */ 31 #define CONFIG_SYS_CACHELINE_SIZE 64 32 33 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 34 35 #include <asm/arch/cpu.h> /* get chip and board defs */ 36 #include <asm/arch/omap.h> 37 38 #define CONFIG_MACH_TYPE MACH_TYPE_CM_T3517 39 40 /* 41 * Display CPU and Board information 42 */ 43 #define CONFIG_DISPLAY_CPUINFO 44 #define CONFIG_DISPLAY_BOARDINFO 45 46 /* Clock Defines */ 47 #define V_OSCK 26000000 /* Clock output from T2 */ 48 #define V_SCLK (V_OSCK >> 1) 49 50 #define CONFIG_MISC_INIT_R 51 52 #define CONFIG_OF_LIBFDT 53 /* 54 * The early kernel mapping on ARM currently only maps from the base of DRAM 55 * to the end of the kernel image. The kernel is loaded at DRAM base + 0x8000. 56 * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000, 57 * so that leaves DRAM base to DRAM base + 0x4000 available. 58 */ 59 #define CONFIG_SYS_BOOTMAPSZ 0x4000 60 61 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 62 #define CONFIG_SETUP_MEMORY_TAGS 63 #define CONFIG_INITRD_TAG 64 #define CONFIG_REVISION_TAG 65 #define CONFIG_SERIAL_TAG 66 67 /* 68 * Size of malloc() pool 69 */ 70 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ 71 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 72 73 /* 74 * Hardware drivers 75 */ 76 77 /* 78 * NS16550 Configuration 79 */ 80 #define CONFIG_SYS_NS16550 81 #define CONFIG_SYS_NS16550_SERIAL 82 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 83 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 84 85 /* 86 * select serial console configuration 87 */ 88 #define CONFIG_CONS_INDEX 3 89 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 90 #define CONFIG_SERIAL3 3 /* UART3 */ 91 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 92 93 /* allow to overwrite serial and ethaddr */ 94 #define CONFIG_ENV_OVERWRITE 95 #define CONFIG_BAUDRATE 115200 96 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 97 115200} 98 99 #define CONFIG_OMAP_GPIO 100 101 #define CONFIG_GENERIC_MMC 102 #define CONFIG_MMC 103 #define CONFIG_OMAP_HSMMC 104 #define CONFIG_DOS_PARTITION 105 106 /* USB */ 107 #define CONFIG_USB_MUSB_AM35X 108 109 #ifndef CONFIG_USB_MUSB_AM35X 110 #define CONFIG_USB_OMAP3 111 #define CONFIG_USB_EHCI 112 #define CONFIG_USB_EHCI_OMAP 113 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 146 114 #define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 147 115 #else /* !CONFIG_USB_MUSB_AM35X */ 116 #define CONFIG_USB_MUSB_HOST 117 #define CONFIG_USB_MUSB_PIO_ONLY 118 #endif /* CONFIG_USB_MUSB_AM35X */ 119 120 #define CONFIG_USB_STORAGE 121 #define CONFIG_CMD_USB 122 123 /* commands to include */ 124 #define CONFIG_CMD_CACHE 125 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 126 #define CONFIG_CMD_FAT /* FAT support */ 127 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 128 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 129 #define CONFIG_MTD_PARTITIONS 130 #define MTDIDS_DEFAULT "nand0=nand" 131 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ 132 "1920k(u-boot),256k(u-boot-env),"\ 133 "4m(kernel),-(fs)" 134 135 #define CONFIG_CMD_I2C /* I2C serial bus support */ 136 #define CONFIG_CMD_MMC /* MMC support */ 137 #define CONFIG_CMD_NAND /* NAND support */ 138 #define CONFIG_CMD_DHCP 139 #define CONFIG_CMD_PING 140 #define CONFIG_CMD_GPIO 141 142 143 #define CONFIG_SYS_NO_FLASH 144 #define CONFIG_SYS_I2C 145 #define CONFIG_SYS_OMAP24_I2C_SPEED 400000 146 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 147 #define CONFIG_SYS_I2C_OMAP34XX 148 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 149 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 150 #define CONFIG_SYS_I2C_EEPROM_BUS 0 151 #define CONFIG_I2C_MULTI_BUS 152 153 /* 154 * Board NAND Info. 155 */ 156 #define CONFIG_NAND_OMAP_GPMC 157 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 158 /* to access nand */ 159 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 160 /* to access nand at */ 161 /* CS0 */ 162 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 163 /* devices */ 164 165 /* Environment information */ 166 #define CONFIG_BOOTDELAY 3 167 #define CONFIG_ZERO_BOOTDELAY_CHECK 168 169 #define CONFIG_EXTRA_ENV_SETTINGS \ 170 "loadaddr=0x82000000\0" \ 171 "baudrate=115200\0" \ 172 "console=ttyO2,115200n8\0" \ 173 "netretry=yes\0" \ 174 "mpurate=auto\0" \ 175 "vram=12M\0" \ 176 "dvimode=1024x768MR-16@60\0" \ 177 "defaultdisplay=dvi\0" \ 178 "mmcdev=0\0" \ 179 "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \ 180 "mmcrootfstype=ext4\0" \ 181 "nandroot=/dev/mtdblock4 rw\0" \ 182 "nandrootfstype=ubifs\0" \ 183 "mmcargs=setenv bootargs console=${console} " \ 184 "mpurate=${mpurate} " \ 185 "vram=${vram} " \ 186 "omapfb.mode=dvi:${dvimode} " \ 187 "omapdss.def_disp=${defaultdisplay} " \ 188 "root=${mmcroot} " \ 189 "rootfstype=${mmcrootfstype}\0" \ 190 "nandargs=setenv bootargs console=${console} " \ 191 "mpurate=${mpurate} " \ 192 "vram=${vram} " \ 193 "omapfb.mode=dvi:${dvimode} " \ 194 "omapdss.def_disp=${defaultdisplay} " \ 195 "root=${nandroot} " \ 196 "rootfstype=${nandrootfstype}\0" \ 197 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 198 "bootscript=echo Running bootscript from mmc ...; " \ 199 "source ${loadaddr}\0" \ 200 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 201 "mmcboot=echo Booting from mmc ...; " \ 202 "run mmcargs; " \ 203 "bootm ${loadaddr}\0" \ 204 "nandboot=echo Booting from nand ...; " \ 205 "run nandargs; " \ 206 "nand read ${loadaddr} 2a0000 400000; " \ 207 "bootm ${loadaddr}\0" \ 208 209 #define CONFIG_CMD_BOOTZ 210 #define CONFIG_BOOTCOMMAND \ 211 "mmc dev ${mmcdev}; if mmc rescan; then " \ 212 "if run loadbootscript; then " \ 213 "run bootscript; " \ 214 "else " \ 215 "if run loaduimage; then " \ 216 "run mmcboot; " \ 217 "else run nandboot; " \ 218 "fi; " \ 219 "fi; " \ 220 "else run nandboot; fi" 221 222 /* 223 * Miscellaneous configurable options 224 */ 225 #define CONFIG_AUTO_COMPLETE 226 #define CONFIG_CMDLINE_EDITING 227 #define CONFIG_TIMESTAMP 228 #define CONFIG_SYS_AUTOLOAD "no" 229 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 230 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 231 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 232 /* Print Buffer Size */ 233 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 234 sizeof(CONFIG_SYS_PROMPT) + 16) 235 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ 236 /* Boot Argument Buffer Size */ 237 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 238 239 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000) 240 241 /* 242 * AM3517 has 12 GP timers, they can be driven by the system clock 243 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 244 * This rate is divided by a local divisor. 245 */ 246 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 247 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 248 #define CONFIG_SYS_HZ 1000 249 250 /*----------------------------------------------------------------------- 251 * Physical Memory Map 252 */ 253 #define CONFIG_NR_DRAM_BANKS 1 /* CM-T3517 DRAM is only on CS0 */ 254 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 255 #define CONFIG_SYS_CS0_SIZE (256 << 20) 256 257 /*----------------------------------------------------------------------- 258 * FLASH and environment organization 259 */ 260 261 /* **** PISMO SUPPORT *** */ 262 /* Monitor at start of flash */ 263 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 264 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 265 266 #define CONFIG_ENV_IS_IN_NAND 267 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 268 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 269 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 270 271 #if defined(CONFIG_CMD_NET) 272 #define CONFIG_DRIVER_TI_EMAC 273 #define CONFIG_DRIVER_TI_EMAC_USE_RMII 274 #define CONFIG_MII 275 #define CONFIG_SMC911X 276 #define CONFIG_SMC911X_32_BIT 277 #define CONFIG_SMC911X_BASE (0x2C000000 + (16 << 20)) 278 #define CONFIG_ARP_TIMEOUT 200UL 279 #define CONFIG_NET_RETRY_COUNT 5 280 #endif /* CONFIG_CMD_NET */ 281 282 /* additions for new relocation code, must be added to all boards */ 283 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 284 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 285 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 286 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 287 CONFIG_SYS_INIT_RAM_SIZE - \ 288 GENERATED_GBL_DATA_SIZE) 289 290 /* Status LED */ 291 #define CONFIG_STATUS_LED /* Status LED enabled */ 292 #define CONFIG_BOARD_SPECIFIC_LED 293 #define CONFIG_GPIO_LED 294 #define GREEN_LED_GPIO 186 /* CM-T3517 Green LED is GPIO186 */ 295 #define GREEN_LED_DEV 0 296 #define STATUS_LED_BIT GREEN_LED_GPIO 297 #define STATUS_LED_STATE STATUS_LED_ON 298 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) 299 #define STATUS_LED_BOOT GREEN_LED_DEV 300 301 /* GPIO banks */ 302 #ifdef CONFIG_STATUS_LED 303 #define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */ 304 #endif 305 306 /* Display Configuration */ 307 #define CONFIG_OMAP3_GPIO_2 308 #define CONFIG_OMAP3_GPIO_5 309 #define CONFIG_VIDEO_OMAP3 310 #define LCD_BPP LCD_COLOR16 311 312 #define CONFIG_LCD 313 #define CONFIG_SPLASH_SCREEN 314 #define CONFIG_SPLASHIMAGE_GUARD 315 #define CONFIG_CMD_BMP 316 #define CONFIG_BMP_16BPP 317 #define CONFIG_SCF0403_LCD 318 319 #define CONFIG_OMAP3_SPI 320 321 #endif /* __CONFIG_H */ 322