1 /* 2 * (C) Copyright 2013 CompuLab, Ltd. 3 * Author: Igor Grinberg <grinberg@compulab.co.il> 4 * 5 * Configuration settings for the CompuLab CM-T3517 board 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 /* 14 * High Level Configuration Options 15 */ 16 #define CONFIG_OMAP /* in a TI OMAP core */ 17 #define CONFIG_CM_T3517 /* working with CM-T3517 */ 18 #define CONFIG_OMAP_COMMON 19 #define CONFIG_SYS_GENERIC_BOARD 20 /* Common ARM Erratas */ 21 #define CONFIG_ARM_ERRATA_454179 22 #define CONFIG_ARM_ERRATA_430973 23 #define CONFIG_ARM_ERRATA_621766 24 25 #define CONFIG_SYS_TEXT_BASE 0x80008000 26 27 /* 28 * This is needed for the DMA stuff. 29 * Although the default iss 64, we still define it 30 * to be on the safe side once the default is changed. 31 */ 32 #define CONFIG_SYS_CACHELINE_SIZE 64 33 34 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 35 36 #include <asm/arch/cpu.h> /* get chip and board defs */ 37 #include <asm/arch/omap.h> 38 39 #define CONFIG_MACH_TYPE MACH_TYPE_CM_T3517 40 41 /* 42 * Display CPU and Board information 43 */ 44 #define CONFIG_DISPLAY_CPUINFO 45 #define CONFIG_DISPLAY_BOARDINFO 46 47 /* Clock Defines */ 48 #define V_OSCK 26000000 /* Clock output from T2 */ 49 #define V_SCLK (V_OSCK >> 1) 50 51 #define CONFIG_MISC_INIT_R 52 53 #define CONFIG_OF_LIBFDT 54 /* 55 * The early kernel mapping on ARM currently only maps from the base of DRAM 56 * to the end of the kernel image. The kernel is loaded at DRAM base + 0x8000. 57 * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000, 58 * so that leaves DRAM base to DRAM base + 0x4000 available. 59 */ 60 #define CONFIG_SYS_BOOTMAPSZ 0x4000 61 62 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 63 #define CONFIG_SETUP_MEMORY_TAGS 64 #define CONFIG_INITRD_TAG 65 #define CONFIG_REVISION_TAG 66 #define CONFIG_SERIAL_TAG 67 68 /* 69 * Size of malloc() pool 70 */ 71 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ 72 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 73 74 /* 75 * Hardware drivers 76 */ 77 78 /* 79 * NS16550 Configuration 80 */ 81 #define CONFIG_SYS_NS16550 82 #define CONFIG_SYS_NS16550_SERIAL 83 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 84 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 85 86 /* 87 * select serial console configuration 88 */ 89 #define CONFIG_CONS_INDEX 3 90 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 91 #define CONFIG_SERIAL3 3 /* UART3 */ 92 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 93 94 /* allow to overwrite serial and ethaddr */ 95 #define CONFIG_ENV_OVERWRITE 96 #define CONFIG_BAUDRATE 115200 97 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 98 115200} 99 100 #define CONFIG_OMAP_GPIO 101 102 #define CONFIG_GENERIC_MMC 103 #define CONFIG_MMC 104 #define CONFIG_OMAP_HSMMC 105 #define CONFIG_DOS_PARTITION 106 107 /* USB */ 108 #define CONFIG_USB_MUSB_AM35X 109 110 #ifndef CONFIG_USB_MUSB_AM35X 111 #define CONFIG_USB_OMAP3 112 #define CONFIG_USB_EHCI 113 #define CONFIG_USB_EHCI_OMAP 114 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 146 115 #define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 147 116 #else /* !CONFIG_USB_MUSB_AM35X */ 117 #define CONFIG_USB_MUSB_HOST 118 #define CONFIG_USB_MUSB_PIO_ONLY 119 #endif /* CONFIG_USB_MUSB_AM35X */ 120 121 #define CONFIG_USB_STORAGE 122 #define CONFIG_CMD_USB 123 124 /* commands to include */ 125 #define CONFIG_CMD_CACHE 126 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 127 #define CONFIG_CMD_FAT /* FAT support */ 128 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 129 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 130 #define CONFIG_MTD_PARTITIONS 131 #define MTDIDS_DEFAULT "nand0=nand" 132 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ 133 "1920k(u-boot),256k(u-boot-env),"\ 134 "4m(kernel),-(fs)" 135 136 #define CONFIG_CMD_I2C /* I2C serial bus support */ 137 #define CONFIG_CMD_MMC /* MMC support */ 138 #define CONFIG_CMD_NAND /* NAND support */ 139 #define CONFIG_CMD_DHCP 140 #define CONFIG_CMD_PING 141 #define CONFIG_CMD_GPIO 142 143 144 #define CONFIG_SYS_NO_FLASH 145 #define CONFIG_SYS_I2C 146 #define CONFIG_SYS_OMAP24_I2C_SPEED 400000 147 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 148 #define CONFIG_SYS_I2C_OMAP34XX 149 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 150 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 151 #define CONFIG_SYS_I2C_EEPROM_BUS 0 152 #define CONFIG_I2C_MULTI_BUS 153 154 /* 155 * Board NAND Info. 156 */ 157 #define CONFIG_NAND_OMAP_GPMC 158 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 159 /* to access nand */ 160 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 161 /* to access nand at */ 162 /* CS0 */ 163 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 164 /* devices */ 165 166 /* Environment information */ 167 #define CONFIG_BOOTDELAY 3 168 #define CONFIG_ZERO_BOOTDELAY_CHECK 169 170 #define CONFIG_EXTRA_ENV_SETTINGS \ 171 "loadaddr=0x82000000\0" \ 172 "baudrate=115200\0" \ 173 "console=ttyO2,115200n8\0" \ 174 "netretry=yes\0" \ 175 "mpurate=auto\0" \ 176 "vram=12M\0" \ 177 "dvimode=1024x768MR-16@60\0" \ 178 "defaultdisplay=dvi\0" \ 179 "mmcdev=0\0" \ 180 "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \ 181 "mmcrootfstype=ext4\0" \ 182 "nandroot=/dev/mtdblock4 rw\0" \ 183 "nandrootfstype=ubifs\0" \ 184 "mmcargs=setenv bootargs console=${console} " \ 185 "mpurate=${mpurate} " \ 186 "vram=${vram} " \ 187 "omapfb.mode=dvi:${dvimode} " \ 188 "omapdss.def_disp=${defaultdisplay} " \ 189 "root=${mmcroot} " \ 190 "rootfstype=${mmcrootfstype}\0" \ 191 "nandargs=setenv bootargs console=${console} " \ 192 "mpurate=${mpurate} " \ 193 "vram=${vram} " \ 194 "omapfb.mode=dvi:${dvimode} " \ 195 "omapdss.def_disp=${defaultdisplay} " \ 196 "root=${nandroot} " \ 197 "rootfstype=${nandrootfstype}\0" \ 198 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 199 "bootscript=echo Running bootscript from mmc ...; " \ 200 "source ${loadaddr}\0" \ 201 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 202 "mmcboot=echo Booting from mmc ...; " \ 203 "run mmcargs; " \ 204 "bootm ${loadaddr}\0" \ 205 "nandboot=echo Booting from nand ...; " \ 206 "run nandargs; " \ 207 "nand read ${loadaddr} 2a0000 400000; " \ 208 "bootm ${loadaddr}\0" \ 209 210 #define CONFIG_CMD_BOOTZ 211 #define CONFIG_BOOTCOMMAND \ 212 "mmc dev ${mmcdev}; if mmc rescan; then " \ 213 "if run loadbootscript; then " \ 214 "run bootscript; " \ 215 "else " \ 216 "if run loaduimage; then " \ 217 "run mmcboot; " \ 218 "else run nandboot; " \ 219 "fi; " \ 220 "fi; " \ 221 "else run nandboot; fi" 222 223 /* 224 * Miscellaneous configurable options 225 */ 226 #define CONFIG_AUTO_COMPLETE 227 #define CONFIG_CMDLINE_EDITING 228 #define CONFIG_TIMESTAMP 229 #define CONFIG_SYS_AUTOLOAD "no" 230 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 231 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 232 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 233 /* Print Buffer Size */ 234 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 235 sizeof(CONFIG_SYS_PROMPT) + 16) 236 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ 237 /* Boot Argument Buffer Size */ 238 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 239 240 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000) 241 242 /* 243 * AM3517 has 12 GP timers, they can be driven by the system clock 244 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 245 * This rate is divided by a local divisor. 246 */ 247 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 248 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 249 #define CONFIG_SYS_HZ 1000 250 251 /*----------------------------------------------------------------------- 252 * Physical Memory Map 253 */ 254 #define CONFIG_NR_DRAM_BANKS 1 /* CM-T3517 DRAM is only on CS0 */ 255 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 256 #define CONFIG_SYS_CS0_SIZE (256 << 20) 257 258 /*----------------------------------------------------------------------- 259 * FLASH and environment organization 260 */ 261 262 /* **** PISMO SUPPORT *** */ 263 /* Monitor at start of flash */ 264 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 265 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 266 267 #define CONFIG_ENV_IS_IN_NAND 268 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 269 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 270 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 271 272 #if defined(CONFIG_CMD_NET) 273 #define CONFIG_DRIVER_TI_EMAC 274 #define CONFIG_DRIVER_TI_EMAC_USE_RMII 275 #define CONFIG_MII 276 #define CONFIG_SMC911X 277 #define CONFIG_SMC911X_32_BIT 278 #define CONFIG_SMC911X_BASE (0x2C000000 + (16 << 20)) 279 #define CONFIG_ARP_TIMEOUT 200UL 280 #define CONFIG_NET_RETRY_COUNT 5 281 #endif /* CONFIG_CMD_NET */ 282 283 /* additions for new relocation code, must be added to all boards */ 284 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 285 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 286 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 287 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 288 CONFIG_SYS_INIT_RAM_SIZE - \ 289 GENERATED_GBL_DATA_SIZE) 290 291 /* Status LED */ 292 #define CONFIG_STATUS_LED /* Status LED enabled */ 293 #define CONFIG_BOARD_SPECIFIC_LED 294 #define CONFIG_GPIO_LED 295 #define GREEN_LED_GPIO 186 /* CM-T3517 Green LED is GPIO186 */ 296 #define GREEN_LED_DEV 0 297 #define STATUS_LED_BIT GREEN_LED_GPIO 298 #define STATUS_LED_STATE STATUS_LED_ON 299 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) 300 #define STATUS_LED_BOOT GREEN_LED_DEV 301 302 /* GPIO banks */ 303 #ifdef CONFIG_STATUS_LED 304 #define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */ 305 #endif 306 307 /* Display Configuration */ 308 #define CONFIG_OMAP3_GPIO_2 309 #define CONFIG_OMAP3_GPIO_5 310 #define CONFIG_VIDEO_OMAP3 311 #define LCD_BPP LCD_COLOR16 312 313 #define CONFIG_LCD 314 #define CONFIG_SPLASH_SCREEN 315 #define CONFIG_SPLASHIMAGE_GUARD 316 #define CONFIG_CMD_BMP 317 #define CONFIG_BMP_16BPP 318 #define CONFIG_SCF0403_LCD 319 320 #define CONFIG_OMAP3_SPI 321 322 #endif /* __CONFIG_H */ 323