xref: /openbmc/u-boot/include/configs/cm_t3517.h (revision 4de512018ba7d57f1672be21c7459281f7c97514)
1 /*
2  * (C) Copyright 2013 CompuLab, Ltd.
3  * Author: Igor Grinberg <grinberg@compulab.co.il>
4  *
5  * Configuration settings for the CompuLab CM-T3517 board
6  *
7  * SPDX-License-Identifier:	GPL-2.0+
8  */
9 
10 #ifndef __CONFIG_H
11 #define __CONFIG_H
12 
13 /*
14  * High Level Configuration Options
15  */
16 #define CONFIG_CM_T3517	/* working with CM-T3517 */
17 
18 #define CONFIG_SYS_TEXT_BASE	0x80008000
19 
20 /*
21  * This is needed for the DMA stuff.
22  * Although the default iss 64, we still define it
23  * to be on the safe side once the default is changed.
24  */
25 
26 #define CONFIG_EMIF4	/* The chip has EMIF4 controller */
27 
28 #include <asm/arch/cpu.h>		/* get chip and board defs */
29 #include <asm/arch/omap.h>
30 
31 #define CONFIG_MACH_TYPE                MACH_TYPE_CM_T3517
32 
33 /* Clock Defines */
34 #define V_OSCK			26000000	/* Clock output from T2 */
35 #define V_SCLK			(V_OSCK >> 1)
36 
37 #define CONFIG_MISC_INIT_R
38 
39 /*
40  * The early kernel mapping on ARM currently only maps from the base of DRAM
41  * to the end of the kernel image.  The kernel is loaded at DRAM base + 0x8000.
42  * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000,
43  * so that leaves DRAM base to DRAM base + 0x4000 available.
44  */
45 #define CONFIG_SYS_BOOTMAPSZ	        0x4000
46 
47 #define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
48 #define CONFIG_SETUP_MEMORY_TAGS
49 #define CONFIG_INITRD_TAG
50 #define CONFIG_REVISION_TAG
51 #define CONFIG_SERIAL_TAG
52 
53 /*
54  * Size of malloc() pool
55  */
56 #define CONFIG_ENV_SIZE		(128 << 10)	/* 128 KiB */
57 #define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + (128 << 10))
58 
59 /*
60  * Hardware drivers
61  */
62 
63 /*
64  * NS16550 Configuration
65  */
66 #define CONFIG_SYS_NS16550_SERIAL
67 #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
68 #define CONFIG_SYS_NS16550_CLK		48000000	/* 48MHz (APLL96/2) */
69 
70 /*
71  * select serial console configuration
72  */
73 #define CONFIG_CONS_INDEX		3
74 #define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
75 #define CONFIG_SERIAL3			3	/* UART3 */
76 
77 /* allow to overwrite serial and ethaddr */
78 #define CONFIG_ENV_OVERWRITE
79 #define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
80 					115200}
81 
82 /* USB */
83 #define CONFIG_USB_MUSB_AM35X
84 
85 #ifndef CONFIG_USB_MUSB_AM35X
86 #define CONFIG_USB_OMAP3
87 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 146
88 #define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 147
89 #else /* !CONFIG_USB_MUSB_AM35X */
90 #define CONFIG_USB_MUSB_PIO_ONLY
91 #endif /* CONFIG_USB_MUSB_AM35X */
92 
93 /* commands to include */
94 #define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
95 #define CONFIG_MTD_PARTITIONS
96 #define MTDIDS_DEFAULT		"nand0=nand"
97 #define MTDPARTS_DEFAULT	"mtdparts=nand:512k(x-loader),"\
98 				"1920k(u-boot),256k(u-boot-env),"\
99 				"4m(kernel),-(fs)"
100 
101 #define CONFIG_CMD_NAND		/* NAND support			*/
102 
103 #define CONFIG_SYS_I2C
104 #define CONFIG_SYS_OMAP24_I2C_SPEED	400000
105 #define CONFIG_SYS_OMAP24_I2C_SLAVE	1
106 #define CONFIG_SYS_I2C_OMAP34XX
107 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
108 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
109 #define CONFIG_SYS_I2C_EEPROM_BUS	0
110 #define CONFIG_I2C_MULTI_BUS
111 
112 /*
113  * Board NAND Info.
114  */
115 #define CONFIG_NAND_OMAP_GPMC
116 #define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
117 							/* to access nand */
118 #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
119 							/* to access nand at */
120 							/* CS0 */
121 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
122 							/* devices */
123 
124 /* Environment information */
125 #define CONFIG_EXTRA_ENV_SETTINGS \
126 	"loadaddr=0x82000000\0" \
127 	"baudrate=115200\0" \
128 	"console=ttyO2,115200n8\0" \
129 	"netretry=yes\0" \
130 	"mpurate=auto\0" \
131 	"vram=12M\0" \
132 	"dvimode=1024x768MR-16@60\0" \
133 	"defaultdisplay=dvi\0" \
134 	"mmcdev=0\0" \
135 	"mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
136 	"mmcrootfstype=ext4\0" \
137 	"nandroot=/dev/mtdblock4 rw\0" \
138 	"nandrootfstype=ubifs\0" \
139 	"mmcargs=setenv bootargs console=${console} " \
140 		"mpurate=${mpurate} " \
141 		"vram=${vram} " \
142 		"omapfb.mode=dvi:${dvimode} " \
143 		"omapdss.def_disp=${defaultdisplay} " \
144 		"root=${mmcroot} " \
145 		"rootfstype=${mmcrootfstype}\0" \
146 	"nandargs=setenv bootargs console=${console} " \
147 		"mpurate=${mpurate} " \
148 		"vram=${vram} " \
149 		"omapfb.mode=dvi:${dvimode} " \
150 		"omapdss.def_disp=${defaultdisplay} " \
151 		"root=${nandroot} " \
152 		"rootfstype=${nandrootfstype}\0" \
153 	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
154 	"bootscript=echo Running bootscript from mmc ...; " \
155 		"source ${loadaddr}\0" \
156 	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
157 	"mmcboot=echo Booting from mmc ...; " \
158 		"run mmcargs; " \
159 		"bootm ${loadaddr}\0" \
160 	"nandboot=echo Booting from nand ...; " \
161 		"run nandargs; " \
162 		"nand read ${loadaddr} 2a0000 400000; " \
163 		"bootm ${loadaddr}\0" \
164 
165 #define CONFIG_BOOTCOMMAND \
166 	"mmc dev ${mmcdev}; if mmc rescan; then " \
167 		"if run loadbootscript; then " \
168 			"run bootscript; " \
169 		"else " \
170 			"if run loaduimage; then " \
171 				"run mmcboot; " \
172 			"else run nandboot; " \
173 			"fi; " \
174 		"fi; " \
175 	"else run nandboot; fi"
176 
177 /*
178  * Miscellaneous configurable options
179  */
180 #define CONFIG_AUTO_COMPLETE
181 #define CONFIG_CMDLINE_EDITING
182 #define CONFIG_TIMESTAMP
183 #define CONFIG_SYS_AUTOLOAD		"no"
184 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
185 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
186 /* Print Buffer Size */
187 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
188 					sizeof(CONFIG_SYS_PROMPT) + 16)
189 #define CONFIG_SYS_MAXARGS		32	/* max number of command args */
190 /* Boot Argument Buffer Size */
191 #define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
192 
193 #define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0 + 0x02000000)
194 
195 /*
196  * AM3517 has 12 GP timers, they can be driven by the system clock
197  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
198  * This rate is divided by a local divisor.
199  */
200 #define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
201 #define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
202 #define CONFIG_SYS_HZ			1000
203 
204 /*-----------------------------------------------------------------------
205  * Physical Memory Map
206  */
207 #define CONFIG_NR_DRAM_BANKS	1	/* CM-T3517 DRAM is only on CS0 */
208 #define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
209 #define CONFIG_SYS_CS0_SIZE		(256 << 20)
210 
211 /*-----------------------------------------------------------------------
212  * FLASH and environment organization
213  */
214 
215 /* **** PISMO SUPPORT *** */
216 /* Monitor at start of flash */
217 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
218 #define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
219 
220 #define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
221 #define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
222 #define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
223 
224 #if defined(CONFIG_CMD_NET)
225 #define CONFIG_DRIVER_TI_EMAC
226 #define CONFIG_DRIVER_TI_EMAC_USE_RMII
227 #define CONFIG_MII
228 #define CONFIG_SMC911X
229 #define CONFIG_SMC911X_32_BIT
230 #define CONFIG_SMC911X_BASE	(0x2C000000 + (16 << 20))
231 #define CONFIG_ARP_TIMEOUT		200UL
232 #define CONFIG_NET_RETRY_COUNT		5
233 #endif /* CONFIG_CMD_NET */
234 
235 /* additions for new relocation code, must be added to all boards */
236 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
237 #define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
238 #define CONFIG_SYS_INIT_RAM_SIZE	0x800
239 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR +	\
240 					 CONFIG_SYS_INIT_RAM_SIZE -	\
241 					 GENERATED_GBL_DATA_SIZE)
242 
243 /* Status LED */
244 #define GREEN_LED_GPIO			186 /* CM-T3517 Green LED is GPIO186 */
245 
246 /* Display Configuration */
247 #define CONFIG_VIDEO_OMAP3
248 #define LCD_BPP		LCD_COLOR16
249 
250 #define CONFIG_SPLASH_SCREEN
251 #define CONFIG_SPLASHIMAGE_GUARD
252 #define CONFIG_BMP_16BPP
253 #define CONFIG_SCF0403_LCD
254 
255 #define CONFIG_OMAP3_SPI
256 
257 /* EEPROM */
258 #define CONFIG_ENV_EEPROM_IS_ON_I2C
259 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
260 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
261 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
262 #define CONFIG_SYS_EEPROM_SIZE			256
263 
264 #endif /* __CONFIG_H */
265