1 /* 2 * (C) Copyright 2011 CompuLab, Ltd. 3 * Mike Rapoport <mike@compulab.co.il> 4 * Igor Grinberg <grinberg@compulab.co.il> 5 * 6 * Based on omap3_beagle.h 7 * (C) Copyright 2006-2008 8 * Texas Instruments. 9 * Richard Woodruff <r-woodruff2@ti.com> 10 * Syed Mohammed Khasim <x0khasim@ti.com> 11 * 12 * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 */ 16 17 #ifndef __CONFIG_H 18 #define __CONFIG_H 19 20 #define CONFIG_SYS_CACHELINE_SIZE 64 21 22 /* 23 * High Level Configuration Options 24 */ 25 #define CONFIG_OMAP /* in a TI OMAP core */ 26 #define CONFIG_OMAP_GPIO 27 #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */ 28 29 #define CONFIG_SDRC /* The chip has SDRC controller */ 30 31 #include <asm/arch/cpu.h> /* get chip and board defs */ 32 #include <asm/arch/omap.h> 33 34 /* Clock Defines */ 35 #define V_OSCK 26000000 /* Clock output from T2 */ 36 #define V_SCLK (V_OSCK >> 1) 37 38 #define CONFIG_MISC_INIT_R 39 40 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 41 #define CONFIG_SETUP_MEMORY_TAGS 42 #define CONFIG_INITRD_TAG 43 #define CONFIG_REVISION_TAG 44 #define CONFIG_SERIAL_TAG 45 46 /* 47 * Size of malloc() pool 48 */ 49 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ 50 /* Sector */ 51 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 52 53 /* 54 * Hardware drivers 55 */ 56 57 /* 58 * NS16550 Configuration 59 */ 60 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 61 62 #define CONFIG_SYS_NS16550_SERIAL 63 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 64 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 65 66 /* 67 * select serial console configuration 68 */ 69 #define CONFIG_CONS_INDEX 3 70 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 71 #define CONFIG_SERIAL3 3 /* UART3 */ 72 73 /* allow to overwrite serial and ethaddr */ 74 #define CONFIG_ENV_OVERWRITE 75 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 76 115200} 77 78 /* USB */ 79 #define CONFIG_USB_OMAP3 80 #define CONFIG_USB_EHCI 81 #define CONFIG_USB_EHCI_OMAP 82 #define CONFIG_USB_MUSB_UDC 83 #define CONFIG_TWL4030_USB 84 85 /* USB device configuration */ 86 #define CONFIG_USB_DEVICE 87 #define CONFIG_USB_TTY 88 89 /* commands to include */ 90 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 91 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 92 #define CONFIG_MTD_PARTITIONS 93 #define MTDIDS_DEFAULT "nand0=nand" 94 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ 95 "1920k(u-boot),256k(u-boot-env),"\ 96 "4m(kernel),-(fs)" 97 98 #define CONFIG_CMD_NAND /* NAND support */ 99 100 #define CONFIG_SYS_I2C 101 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 102 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 103 #define CONFIG_SYS_I2C_OMAP34XX 104 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 105 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 106 #define CONFIG_SYS_I2C_EEPROM_BUS 0 107 #define CONFIG_I2C_MULTI_BUS 108 109 /* 110 * TWL4030 111 */ 112 #define CONFIG_TWL4030_LED 113 114 /* 115 * Board NAND Info. 116 */ 117 #define CONFIG_NAND_OMAP_GPMC 118 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 119 /* to access nand */ 120 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 121 /* to access nand at */ 122 /* CS0 */ 123 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 124 /* devices */ 125 126 /* Environment information */ 127 #define CONFIG_EXTRA_ENV_SETTINGS \ 128 "loadaddr=0x82000000\0" \ 129 "usbtty=cdc_acm\0" \ 130 "console=ttyO2,115200n8\0" \ 131 "mpurate=500\0" \ 132 "vram=12M\0" \ 133 "dvimode=1024x768MR-16@60\0" \ 134 "defaultdisplay=dvi\0" \ 135 "mmcdev=0\0" \ 136 "mmcroot=/dev/mmcblk0p2 rw\0" \ 137 "mmcrootfstype=ext4 rootwait\0" \ 138 "nandroot=/dev/mtdblock4 rw\0" \ 139 "nandrootfstype=ubifs\0" \ 140 "mmcargs=setenv bootargs console=${console} " \ 141 "mpurate=${mpurate} " \ 142 "vram=${vram} " \ 143 "omapfb.mode=dvi:${dvimode} " \ 144 "omapdss.def_disp=${defaultdisplay} " \ 145 "root=${mmcroot} " \ 146 "rootfstype=${mmcrootfstype}\0" \ 147 "nandargs=setenv bootargs console=${console} " \ 148 "mpurate=${mpurate} " \ 149 "vram=${vram} " \ 150 "omapfb.mode=dvi:${dvimode} " \ 151 "omapdss.def_disp=${defaultdisplay} " \ 152 "root=${nandroot} " \ 153 "rootfstype=${nandrootfstype}\0" \ 154 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 155 "bootscript=echo Running bootscript from mmc ...; " \ 156 "source ${loadaddr}\0" \ 157 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 158 "mmcboot=echo Booting from mmc ...; " \ 159 "run mmcargs; " \ 160 "bootm ${loadaddr}\0" \ 161 "nandboot=echo Booting from nand ...; " \ 162 "run nandargs; " \ 163 "nand read ${loadaddr} 2a0000 400000; " \ 164 "bootm ${loadaddr}\0" \ 165 166 #define CONFIG_BOOTCOMMAND \ 167 "mmc dev ${mmcdev}; if mmc rescan; then " \ 168 "if run loadbootscript; then " \ 169 "run bootscript; " \ 170 "else " \ 171 "if run loaduimage; then " \ 172 "run mmcboot; " \ 173 "else run nandboot; " \ 174 "fi; " \ 175 "fi; " \ 176 "else run nandboot; fi" 177 178 /* 179 * Miscellaneous configurable options 180 */ 181 #define CONFIG_AUTO_COMPLETE 182 #define CONFIG_CMDLINE_EDITING 183 #define CONFIG_TIMESTAMP 184 #define CONFIG_SYS_AUTOLOAD "no" 185 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 186 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 187 /* Print Buffer Size */ 188 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 189 sizeof(CONFIG_SYS_PROMPT) + 16) 190 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 191 /* Boot Argument Buffer Size */ 192 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 193 194 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ 195 /* works on */ 196 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 197 0x01F00000) /* 31MB */ 198 199 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 200 /* load address */ 201 202 /* 203 * OMAP3 has 12 GP timers, they can be driven by the system clock 204 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 205 * This rate is divided by a local divisor. 206 */ 207 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 208 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 209 210 /*----------------------------------------------------------------------- 211 * Physical Memory Map 212 */ 213 #define CONFIG_NR_DRAM_BANKS 1 /* CS1 is never populated */ 214 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 215 216 /*----------------------------------------------------------------------- 217 * FLASH and environment organization 218 */ 219 220 /* **** PISMO SUPPORT *** */ 221 /* Monitor at start of flash */ 222 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 223 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 224 225 #define CONFIG_ENV_IS_IN_NAND 226 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 227 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 228 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 229 230 #if defined(CONFIG_CMD_NET) 231 #define CONFIG_SMC911X 232 #define CONFIG_SMC911X_32_BIT 233 #define CM_T3X_SMC911X_BASE 0x2C000000 234 #define SB_T35_SMC911X_BASE (CM_T3X_SMC911X_BASE + (16 << 20)) 235 #define CONFIG_SMC911X_BASE CM_T3X_SMC911X_BASE 236 #endif /* (CONFIG_CMD_NET) */ 237 238 /* additions for new relocation code, must be added to all boards */ 239 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 240 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 241 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 242 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 243 CONFIG_SYS_INIT_RAM_SIZE - \ 244 GENERATED_GBL_DATA_SIZE) 245 246 /* Status LED */ 247 #define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */ 248 249 #define CONFIG_SPLASHIMAGE_GUARD 250 251 /* GPIO banks */ 252 #ifdef CONFIG_LED_STATUS 253 #define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */ 254 #endif 255 256 /* Display Configuration */ 257 #define CONFIG_OMAP3_GPIO_2 258 #define CONFIG_OMAP3_GPIO_5 259 #define CONFIG_VIDEO_OMAP3 260 #define LCD_BPP LCD_COLOR16 261 262 #define CONFIG_SPLASH_SCREEN 263 #define CONFIG_SPLASH_SOURCE 264 #define CONFIG_BMP_16BPP 265 #define CONFIG_SCF0403_LCD 266 267 #define CONFIG_OMAP3_SPI 268 269 /* Defines for SPL */ 270 #define CONFIG_SPL_FRAMEWORK 271 #define CONFIG_SPL_NAND_SIMPLE 272 273 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 274 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 275 276 #define CONFIG_SPL_BOARD_INIT 277 #define CONFIG_SPL_NAND_BASE 278 #define CONFIG_SPL_NAND_DRIVERS 279 #define CONFIG_SPL_NAND_ECC 280 #define CONFIG_SPL_OMAP3_ID_NAND 281 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 282 283 /* NAND boot config */ 284 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 285 #define CONFIG_SYS_NAND_PAGE_COUNT 64 286 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 287 #define CONFIG_SYS_NAND_OOBSIZE 64 288 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 289 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 290 /* 291 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: 292 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT 293 */ 294 #define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \ 295 10, 11, 12 } 296 #define CONFIG_SYS_NAND_ECCSIZE 512 297 #define CONFIG_SYS_NAND_ECCBYTES 3 298 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 299 300 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 301 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 302 303 #define CONFIG_SPL_TEXT_BASE 0x40200800 304 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 305 CONFIG_SPL_TEXT_BASE) 306 307 /* 308 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the 309 * older x-loader implementations. And move the BSS area so that it 310 * doesn't overlap with TEXT_BASE. 311 */ 312 #define CONFIG_SYS_TEXT_BASE 0x80008000 313 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 314 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 315 316 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 317 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 318 319 /* EEPROM */ 320 #define CONFIG_CMD_EEPROM 321 #define CONFIG_ENV_EEPROM_IS_ON_I2C 322 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 323 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 324 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 325 #define CONFIG_SYS_EEPROM_SIZE 256 326 327 #define CONFIG_CMD_EEPROM_LAYOUT 328 #define CONFIG_EEPROM_LAYOUT_HELP_STRING "legacy, v1, v2, v3" 329 330 #endif /* __CONFIG_H */ 331