1 /* 2 * (C) Copyright 2011 CompuLab, Ltd. 3 * Mike Rapoport <mike@compulab.co.il> 4 * Igor Grinberg <grinberg@compulab.co.il> 5 * 6 * Based on omap3_beagle.h 7 * (C) Copyright 2006-2008 8 * Texas Instruments. 9 * Richard Woodruff <r-woodruff2@ti.com> 10 * Syed Mohammed Khasim <x0khasim@ti.com> 11 * 12 * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 */ 16 17 #ifndef __CONFIG_H 18 #define __CONFIG_H 19 20 /* 21 * High Level Configuration Options 22 */ 23 #define CONFIG_OMAP /* in a TI OMAP core */ 24 #define CONFIG_OMAP34XX /* which is a 34XX */ 25 #define CONFIG_OMAP_GPIO 26 #define CONFIG_CMD_GPIO 27 #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */ 28 #define CONFIG_OMAP_COMMON 29 30 #define CONFIG_SDRC /* The chip has SDRC controller */ 31 32 #include <asm/arch/cpu.h> /* get chip and board defs */ 33 #include <asm/arch/omap3.h> 34 35 /* 36 * Display CPU and Board information 37 */ 38 #define CONFIG_DISPLAY_CPUINFO 39 #define CONFIG_DISPLAY_BOARDINFO 40 41 /* Clock Defines */ 42 #define V_OSCK 26000000 /* Clock output from T2 */ 43 #define V_SCLK (V_OSCK >> 1) 44 45 #define CONFIG_MISC_INIT_R 46 47 #define CONFIG_OF_LIBFDT 1 48 49 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 50 #define CONFIG_SETUP_MEMORY_TAGS 51 #define CONFIG_INITRD_TAG 52 #define CONFIG_REVISION_TAG 53 #define CONFIG_SERIAL_TAG 54 55 /* 56 * Size of malloc() pool 57 */ 58 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ 59 /* Sector */ 60 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 61 62 /* 63 * Hardware drivers 64 */ 65 66 /* 67 * NS16550 Configuration 68 */ 69 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 70 71 #define CONFIG_SYS_NS16550 72 #define CONFIG_SYS_NS16550_SERIAL 73 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 74 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 75 76 /* 77 * select serial console configuration 78 */ 79 #define CONFIG_CONS_INDEX 3 80 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 81 #define CONFIG_SERIAL3 3 /* UART3 */ 82 83 /* allow to overwrite serial and ethaddr */ 84 #define CONFIG_ENV_OVERWRITE 85 #define CONFIG_BAUDRATE 115200 86 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 87 115200} 88 89 #define CONFIG_GENERIC_MMC 90 #define CONFIG_MMC 91 #define CONFIG_OMAP_HSMMC 92 #define CONFIG_DOS_PARTITION 93 94 /* USB */ 95 #define CONFIG_USB_OMAP3 96 #define CONFIG_USB_EHCI 97 #define CONFIG_USB_EHCI_OMAP 98 #define CONFIG_USB_STORAGE 99 #define CONFIG_MUSB_UDC 100 #define CONFIG_TWL4030_USB 101 #define CONFIG_CMD_USB 102 103 /* USB device configuration */ 104 #define CONFIG_USB_DEVICE 105 #define CONFIG_USB_TTY 106 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 107 /* This delay is really for slow-to-power-on USB sticks, not the hub */ 108 #define CONFIG_USB_HUB_MIN_POWER_ON_DELAY 500 109 110 /* commands to include */ 111 #include <config_cmd_default.h> 112 113 #define CONFIG_CMD_CACHE 114 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 115 #define CONFIG_CMD_FAT /* FAT support */ 116 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 117 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 118 #define CONFIG_MTD_PARTITIONS 119 #define MTDIDS_DEFAULT "nand0=nand" 120 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ 121 "1920k(u-boot),256k(u-boot-env),"\ 122 "4m(kernel),-(fs)" 123 124 #define CONFIG_CMD_I2C /* I2C serial bus support */ 125 #define CONFIG_CMD_MMC /* MMC support */ 126 #define CONFIG_CMD_NAND /* NAND support */ 127 #define CONFIG_CMD_DHCP 128 #define CONFIG_CMD_PING 129 130 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 131 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 132 #undef CONFIG_CMD_IMLS /* List all found images */ 133 134 #define CONFIG_SYS_NO_FLASH 135 #define CONFIG_SYS_I2C 136 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 137 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 138 #define CONFIG_SYS_I2C_OMAP34XX 139 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 140 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 141 #define CONFIG_I2C_MULTI_BUS 142 143 /* 144 * TWL4030 145 */ 146 #define CONFIG_TWL4030_POWER 147 #define CONFIG_TWL4030_LED 148 149 /* 150 * Board NAND Info. 151 */ 152 #define CONFIG_SYS_NAND_QUIET_TEST 153 #define CONFIG_NAND_OMAP_GPMC 154 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 155 /* to access nand */ 156 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 157 /* to access nand at */ 158 /* CS0 */ 159 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 160 /* devices */ 161 #define GPMC_NAND_ECC_LP_x8_LAYOUT 162 163 /* Environment information */ 164 #define CONFIG_BOOTDELAY 3 165 #define CONFIG_ZERO_BOOTDELAY_CHECK 166 167 #define CONFIG_EXTRA_ENV_SETTINGS \ 168 "loadaddr=0x82000000\0" \ 169 "usbtty=cdc_acm\0" \ 170 "console=ttyO2,115200n8\0" \ 171 "mpurate=500\0" \ 172 "vram=12M\0" \ 173 "dvimode=1024x768MR-16@60\0" \ 174 "defaultdisplay=dvi\0" \ 175 "mmcdev=0\0" \ 176 "mmcroot=/dev/mmcblk0p2 rw\0" \ 177 "mmcrootfstype=ext4 rootwait\0" \ 178 "nandroot=/dev/mtdblock4 rw\0" \ 179 "nandrootfstype=ubifs\0" \ 180 "mmcargs=setenv bootargs console=${console} " \ 181 "mpurate=${mpurate} " \ 182 "vram=${vram} " \ 183 "omapfb.mode=dvi:${dvimode} " \ 184 "omapdss.def_disp=${defaultdisplay} " \ 185 "root=${mmcroot} " \ 186 "rootfstype=${mmcrootfstype}\0" \ 187 "nandargs=setenv bootargs console=${console} " \ 188 "mpurate=${mpurate} " \ 189 "vram=${vram} " \ 190 "omapfb.mode=dvi:${dvimode} " \ 191 "omapdss.def_disp=${defaultdisplay} " \ 192 "root=${nandroot} " \ 193 "rootfstype=${nandrootfstype}\0" \ 194 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 195 "bootscript=echo Running bootscript from mmc ...; " \ 196 "source ${loadaddr}\0" \ 197 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 198 "mmcboot=echo Booting from mmc ...; " \ 199 "run mmcargs; " \ 200 "bootm ${loadaddr}\0" \ 201 "nandboot=echo Booting from nand ...; " \ 202 "run nandargs; " \ 203 "nand read ${loadaddr} 2a0000 400000; " \ 204 "bootm ${loadaddr}\0" \ 205 206 #define CONFIG_CMD_BOOTZ 207 #define CONFIG_BOOTCOMMAND \ 208 "mmc dev ${mmcdev}; if mmc rescan; then " \ 209 "if run loadbootscript; then " \ 210 "run bootscript; " \ 211 "else " \ 212 "if run loaduimage; then " \ 213 "run mmcboot; " \ 214 "else run nandboot; " \ 215 "fi; " \ 216 "fi; " \ 217 "else run nandboot; fi" 218 219 /* 220 * Miscellaneous configurable options 221 */ 222 #define CONFIG_AUTO_COMPLETE 223 #define CONFIG_CMDLINE_EDITING 224 #define CONFIG_TIMESTAMP 225 #define CONFIG_SYS_AUTOLOAD "no" 226 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 227 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 228 #define CONFIG_SYS_PROMPT "CM-T3x # " 229 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 230 /* Print Buffer Size */ 231 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 232 sizeof(CONFIG_SYS_PROMPT) + 16) 233 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 234 /* Boot Argument Buffer Size */ 235 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 236 237 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ 238 /* works on */ 239 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 240 0x01F00000) /* 31MB */ 241 242 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 243 /* load address */ 244 245 /* 246 * OMAP3 has 12 GP timers, they can be driven by the system clock 247 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 248 * This rate is divided by a local divisor. 249 */ 250 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 251 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 252 253 /*----------------------------------------------------------------------- 254 * Physical Memory Map 255 */ 256 #define CONFIG_NR_DRAM_BANKS 1 /* CS1 is never populated */ 257 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 258 259 /*----------------------------------------------------------------------- 260 * FLASH and environment organization 261 */ 262 263 /* **** PISMO SUPPORT *** */ 264 /* Configure the PISMO */ 265 #define PISMO1_NAND_SIZE GPMC_SIZE_128M 266 267 /* Monitor at start of flash */ 268 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 269 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 270 271 #define CONFIG_ENV_IS_IN_NAND 272 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 273 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 274 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 275 276 #if defined(CONFIG_CMD_NET) 277 #define CONFIG_SMC911X 278 #define CONFIG_SMC911X_32_BIT 279 #define CM_T3X_SMC911X_BASE 0x2C000000 280 #define SB_T35_SMC911X_BASE (CM_T3X_SMC911X_BASE + (16 << 20)) 281 #define CONFIG_SMC911X_BASE CM_T3X_SMC911X_BASE 282 #endif /* (CONFIG_CMD_NET) */ 283 284 /* additions for new relocation code, must be added to all boards */ 285 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 286 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 287 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 288 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 289 CONFIG_SYS_INIT_RAM_SIZE - \ 290 GENERATED_GBL_DATA_SIZE) 291 292 /* Status LED */ 293 #define CONFIG_STATUS_LED /* Status LED enabled */ 294 #define CONFIG_BOARD_SPECIFIC_LED 295 #define CONFIG_GPIO_LED 296 #define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */ 297 #define GREEN_LED_DEV 0 298 #define STATUS_LED_BIT GREEN_LED_GPIO 299 #define STATUS_LED_STATE STATUS_LED_ON 300 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) 301 #define STATUS_LED_BOOT GREEN_LED_DEV 302 303 #define CONFIG_SPLASHIMAGE_GUARD 304 305 /* GPIO banks */ 306 #ifdef CONFIG_STATUS_LED 307 #define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */ 308 #endif 309 310 /* Display Configuration */ 311 #define CONFIG_OMAP3_GPIO_2 312 #define CONFIG_OMAP3_GPIO_5 313 #define CONFIG_VIDEO_OMAP3 314 #define LCD_BPP LCD_COLOR16 315 316 #define CONFIG_LCD 317 #define CONFIG_SPLASH_SCREEN 318 #define CONFIG_CMD_BMP 319 #define CONFIG_BMP_16BPP 320 #define CONFIG_SCF0403_LCD 321 322 #define CONFIG_OMAP3_SPI 323 324 /* Defines for SPL */ 325 #define CONFIG_SPL 326 #define CONFIG_SPL_FRAMEWORK 327 #define CONFIG_SPL_NAND_SIMPLE 328 329 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 330 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ 331 #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 332 #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" 333 334 #define CONFIG_SPL_BOARD_INIT 335 #define CONFIG_SPL_LIBCOMMON_SUPPORT 336 #define CONFIG_SPL_LIBDISK_SUPPORT 337 #define CONFIG_SPL_I2C_SUPPORT 338 #define CONFIG_SPL_LIBGENERIC_SUPPORT 339 #define CONFIG_SPL_MMC_SUPPORT 340 #define CONFIG_SPL_FAT_SUPPORT 341 #define CONFIG_SPL_SERIAL_SUPPORT 342 #define CONFIG_SPL_NAND_SUPPORT 343 #define CONFIG_SPL_NAND_BASE 344 #define CONFIG_SPL_NAND_DRIVERS 345 #define CONFIG_SPL_NAND_ECC 346 #define CONFIG_SPL_GPIO_SUPPORT 347 #define CONFIG_SPL_POWER_SUPPORT 348 #define CONFIG_SPL_OMAP3_ID_NAND 349 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 350 351 /* NAND boot config */ 352 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 353 #define CONFIG_SYS_NAND_PAGE_COUNT 64 354 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 355 #define CONFIG_SYS_NAND_OOBSIZE 64 356 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 357 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 358 /* 359 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: 360 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT 361 */ 362 #define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \ 363 10, 11, 12 } 364 #define CONFIG_SYS_NAND_ECCSIZE 512 365 #define CONFIG_SYS_NAND_ECCBYTES 3 366 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 367 368 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 369 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 370 371 #define CONFIG_SPL_TEXT_BASE 0x40200800 372 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 373 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 374 375 /* 376 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the 377 * older x-loader implementations. And move the BSS area so that it 378 * doesn't overlap with TEXT_BASE. 379 */ 380 #define CONFIG_SYS_TEXT_BASE 0x80008000 381 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 382 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 383 384 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 385 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 386 387 #endif /* __CONFIG_H */ 388