xref: /openbmc/u-boot/include/configs/cm_t35.h (revision eb45787b)
1 /*
2  * (C) Copyright 2011 CompuLab, Ltd.
3  * Mike Rapoport <mike@compulab.co.il>
4  * Igor Grinberg <grinberg@compulab.co.il>
5  *
6  * Based on omap3_beagle.h
7  * (C) Copyright 2006-2008
8  * Texas Instruments.
9  * Richard Woodruff <r-woodruff2@ti.com>
10  * Syed Mohammed Khasim <x0khasim@ti.com>
11  *
12  * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards
13  *
14  * SPDX-License-Identifier:	GPL-2.0+
15  */
16 
17 #ifndef __CONFIG_H
18 #define __CONFIG_H
19 
20 #define CONFIG_SYS_CACHELINE_SIZE	64
21 
22 /*
23  * High Level Configuration Options
24  */
25 #define CONFIG_CM_T3X	/* working with CM-T35 and CM-T3730 */
26 
27 #include <asm/arch/cpu.h>		/* get chip and board defs */
28 #include <asm/arch/omap.h>
29 
30 /* Clock Defines */
31 #define V_OSCK			26000000	/* Clock output from T2 */
32 #define V_SCLK			(V_OSCK >> 1)
33 
34 #define CONFIG_MISC_INIT_R
35 
36 #define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
37 #define CONFIG_SETUP_MEMORY_TAGS
38 #define CONFIG_INITRD_TAG
39 #define CONFIG_REVISION_TAG
40 #define CONFIG_SERIAL_TAG
41 
42 /*
43  * Size of malloc() pool
44  */
45 #define CONFIG_ENV_SIZE		(16 << 10)	/* 16 KiB */
46 					/* Sector */
47 #define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + (128 << 10))
48 
49 /*
50  * Hardware drivers
51  */
52 
53 /*
54  * NS16550 Configuration
55  */
56 #define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
57 
58 #define CONFIG_SYS_NS16550_SERIAL
59 #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
60 #define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
61 
62 /*
63  * select serial console configuration
64  */
65 #define CONFIG_CONS_INDEX		3
66 #define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
67 #define CONFIG_SERIAL3			3	/* UART3 */
68 
69 /* allow to overwrite serial and ethaddr */
70 #define CONFIG_ENV_OVERWRITE
71 #define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
72 					115200}
73 
74 /* USB */
75 #define CONFIG_USB_OMAP3
76 #define CONFIG_USB_MUSB_UDC
77 #define CONFIG_TWL4030_USB
78 
79 /* USB device configuration */
80 #define CONFIG_USB_DEVICE
81 #define CONFIG_USB_TTY
82 
83 /* commands to include */
84 #define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
85 #define CONFIG_MTD_PARTITIONS
86 #define MTDIDS_DEFAULT		"nand0=nand"
87 #define MTDPARTS_DEFAULT	"mtdparts=nand:512k(x-loader),"\
88 				"1920k(u-boot),256k(u-boot-env),"\
89 				"4m(kernel),-(fs)"
90 
91 #define CONFIG_SYS_I2C
92 #define CONFIG_SYS_OMAP24_I2C_SPEED	100000
93 #define CONFIG_SYS_OMAP24_I2C_SLAVE	1
94 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
95 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
96 #define CONFIG_SYS_I2C_EEPROM_BUS	0
97 #define CONFIG_I2C_MULTI_BUS
98 
99 /*
100  * TWL4030
101  */
102 #define CONFIG_TWL4030_LED
103 
104 /*
105  * Board NAND Info.
106  */
107 #define CONFIG_NAND_OMAP_GPMC
108 #define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
109 							/* to access nand */
110 #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
111 							/* to access nand at */
112 							/* CS0 */
113 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
114 							/* devices */
115 
116 /* Environment information */
117 #define CONFIG_EXTRA_ENV_SETTINGS \
118 	"loadaddr=0x82000000\0" \
119 	"usbtty=cdc_acm\0" \
120 	"console=ttyO2,115200n8\0" \
121 	"mpurate=500\0" \
122 	"vram=12M\0" \
123 	"dvimode=1024x768MR-16@60\0" \
124 	"defaultdisplay=dvi\0" \
125 	"mmcdev=0\0" \
126 	"mmcroot=/dev/mmcblk0p2 rw\0" \
127 	"mmcrootfstype=ext4 rootwait\0" \
128 	"nandroot=/dev/mtdblock4 rw\0" \
129 	"nandrootfstype=ubifs\0" \
130 	"mmcargs=setenv bootargs console=${console} " \
131 		"mpurate=${mpurate} " \
132 		"vram=${vram} " \
133 		"omapfb.mode=dvi:${dvimode} " \
134 		"omapdss.def_disp=${defaultdisplay} " \
135 		"root=${mmcroot} " \
136 		"rootfstype=${mmcrootfstype}\0" \
137 	"nandargs=setenv bootargs console=${console} " \
138 		"mpurate=${mpurate} " \
139 		"vram=${vram} " \
140 		"omapfb.mode=dvi:${dvimode} " \
141 		"omapdss.def_disp=${defaultdisplay} " \
142 		"root=${nandroot} " \
143 		"rootfstype=${nandrootfstype}\0" \
144 	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
145 	"bootscript=echo Running bootscript from mmc ...; " \
146 		"source ${loadaddr}\0" \
147 	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
148 	"mmcboot=echo Booting from mmc ...; " \
149 		"run mmcargs; " \
150 		"bootm ${loadaddr}\0" \
151 	"nandboot=echo Booting from nand ...; " \
152 		"run nandargs; " \
153 		"nand read ${loadaddr} 2a0000 400000; " \
154 		"bootm ${loadaddr}\0" \
155 
156 #define CONFIG_BOOTCOMMAND \
157 	"mmc dev ${mmcdev}; if mmc rescan; then " \
158 		"if run loadbootscript; then " \
159 			"run bootscript; " \
160 		"else " \
161 			"if run loaduimage; then " \
162 				"run mmcboot; " \
163 			"else run nandboot; " \
164 			"fi; " \
165 		"fi; " \
166 	"else run nandboot; fi"
167 
168 /*
169  * Miscellaneous configurable options
170  */
171 #define CONFIG_AUTO_COMPLETE
172 #define CONFIG_CMDLINE_EDITING
173 #define CONFIG_TIMESTAMP
174 #define CONFIG_SYS_AUTOLOAD		"no"
175 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
176 
177 #define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)	/* memtest */
178 								/* works on */
179 #define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
180 					0x01F00000) /* 31MB */
181 
182 #define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)	/* default */
183 							/* load address */
184 
185 /*
186  * OMAP3 has 12 GP timers, they can be driven by the system clock
187  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
188  * This rate is divided by a local divisor.
189  */
190 #define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
191 #define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
192 
193 /*-----------------------------------------------------------------------
194  * Physical Memory Map
195  */
196 #define CONFIG_NR_DRAM_BANKS	1	/* CS1 is never populated */
197 #define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
198 
199 /*-----------------------------------------------------------------------
200  * FLASH and environment organization
201  */
202 
203 /* **** PISMO SUPPORT *** */
204 /* Monitor at start of flash */
205 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
206 #define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
207 
208 #define CONFIG_ENV_OFFSET		0x260000
209 #define CONFIG_ENV_ADDR			0x260000
210 
211 #if defined(CONFIG_CMD_NET)
212 #define CONFIG_SMC911X
213 #define CONFIG_SMC911X_32_BIT
214 #define CM_T3X_SMC911X_BASE	0x2C000000
215 #define SB_T35_SMC911X_BASE	(CM_T3X_SMC911X_BASE + (16 << 20))
216 #define CONFIG_SMC911X_BASE	CM_T3X_SMC911X_BASE
217 #endif /* (CONFIG_CMD_NET) */
218 
219 /* additions for new relocation code, must be added to all boards */
220 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
221 #define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
222 #define CONFIG_SYS_INIT_RAM_SIZE	0x800
223 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR +	\
224 					 CONFIG_SYS_INIT_RAM_SIZE -	\
225 					 GENERATED_GBL_DATA_SIZE)
226 
227 /* Status LED */
228 #define GREEN_LED_GPIO			186 /* CM-T35 Green LED is GPIO186 */
229 
230 #define CONFIG_SPLASHIMAGE_GUARD
231 
232 /* Display Configuration */
233 #define CONFIG_VIDEO_OMAP3
234 #define LCD_BPP		LCD_COLOR16
235 
236 #define CONFIG_SPLASH_SCREEN
237 #define CONFIG_SPLASH_SOURCE
238 #define CONFIG_BMP_16BPP
239 #define CONFIG_SCF0403_LCD
240 
241 /* Defines for SPL */
242 #define CONFIG_SPL_FRAMEWORK
243 #define CONFIG_SPL_NAND_SIMPLE
244 
245 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
246 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
247 
248 #define CONFIG_SPL_NAND_BASE
249 #define CONFIG_SPL_NAND_DRIVERS
250 #define CONFIG_SPL_NAND_ECC
251 
252 /* NAND boot config */
253 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
254 #define CONFIG_SYS_NAND_PAGE_COUNT	64
255 #define CONFIG_SYS_NAND_PAGE_SIZE	2048
256 #define CONFIG_SYS_NAND_OOBSIZE		64
257 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
258 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
259 /*
260  * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
261  * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
262  */
263 #define CONFIG_SYS_NAND_ECCPOS		{ 1, 2, 3, 4, 5, 6, 7, 8, 9, \
264 					 10, 11, 12 }
265 #define CONFIG_SYS_NAND_ECCSIZE		512
266 #define CONFIG_SYS_NAND_ECCBYTES	3
267 #define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
268 
269 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
270 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
271 
272 #define CONFIG_SPL_TEXT_BASE		0x40200800
273 #define CONFIG_SPL_MAX_SIZE		(SRAM_SCRATCH_SPACE_ADDR - \
274 					 CONFIG_SPL_TEXT_BASE)
275 
276 /*
277  * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
278  * older x-loader implementations. And move the BSS area so that it
279  * doesn't overlap with TEXT_BASE.
280  */
281 #define CONFIG_SYS_TEXT_BASE		0x80008000
282 #define CONFIG_SPL_BSS_START_ADDR	0x80100000
283 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
284 
285 #define CONFIG_SYS_SPL_MALLOC_START	0x80208000
286 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
287 
288 /* EEPROM */
289 #define CONFIG_ENV_EEPROM_IS_ON_I2C
290 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
291 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
292 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
293 #define CONFIG_SYS_EEPROM_SIZE			256
294 
295 #endif /* __CONFIG_H */
296