1 /* 2 * (C) Copyright 2011 CompuLab, Ltd. 3 * Mike Rapoport <mike@compulab.co.il> 4 * Igor Grinberg <grinberg@compulab.co.il> 5 * 6 * Based on omap3_beagle.h 7 * (C) Copyright 2006-2008 8 * Texas Instruments. 9 * Richard Woodruff <r-woodruff2@ti.com> 10 * Syed Mohammed Khasim <x0khasim@ti.com> 11 * 12 * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 */ 16 17 #ifndef __CONFIG_H 18 #define __CONFIG_H 19 20 /* 21 * High Level Configuration Options 22 */ 23 #define CONFIG_OMAP /* in a TI OMAP core */ 24 #define CONFIG_OMAP_GPIO 25 #define CONFIG_CMD_GPIO 26 #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */ 27 #define CONFIG_OMAP_COMMON 28 #define CONFIG_SYS_GENERIC_BOARD 29 /* Common ARM Erratas */ 30 #define CONFIG_ARM_ERRATA_454179 31 #define CONFIG_ARM_ERRATA_430973 32 #define CONFIG_ARM_ERRATA_621766 33 34 #define CONFIG_SDRC /* The chip has SDRC controller */ 35 36 #include <asm/arch/cpu.h> /* get chip and board defs */ 37 #include <asm/arch/omap.h> 38 39 /* 40 * Display CPU and Board information 41 */ 42 #define CONFIG_DISPLAY_CPUINFO 43 #define CONFIG_DISPLAY_BOARDINFO 44 45 /* Clock Defines */ 46 #define V_OSCK 26000000 /* Clock output from T2 */ 47 #define V_SCLK (V_OSCK >> 1) 48 49 #define CONFIG_MISC_INIT_R 50 51 #define CONFIG_OF_LIBFDT 1 52 53 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 54 #define CONFIG_SETUP_MEMORY_TAGS 55 #define CONFIG_INITRD_TAG 56 #define CONFIG_REVISION_TAG 57 #define CONFIG_SERIAL_TAG 58 59 /* 60 * Size of malloc() pool 61 */ 62 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ 63 /* Sector */ 64 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 65 66 /* 67 * Hardware drivers 68 */ 69 70 /* 71 * NS16550 Configuration 72 */ 73 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 74 75 #define CONFIG_SYS_NS16550 76 #define CONFIG_SYS_NS16550_SERIAL 77 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 78 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 79 80 /* 81 * select serial console configuration 82 */ 83 #define CONFIG_CONS_INDEX 3 84 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 85 #define CONFIG_SERIAL3 3 /* UART3 */ 86 87 /* allow to overwrite serial and ethaddr */ 88 #define CONFIG_ENV_OVERWRITE 89 #define CONFIG_BAUDRATE 115200 90 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 91 115200} 92 93 #define CONFIG_GENERIC_MMC 94 #define CONFIG_MMC 95 #define CONFIG_OMAP_HSMMC 96 #define CONFIG_DOS_PARTITION 97 98 /* USB */ 99 #define CONFIG_USB_OMAP3 100 #define CONFIG_USB_EHCI 101 #define CONFIG_USB_EHCI_OMAP 102 #define CONFIG_USB_STORAGE 103 #define CONFIG_MUSB_UDC 104 #define CONFIG_TWL4030_USB 105 #define CONFIG_CMD_USB 106 107 /* USB device configuration */ 108 #define CONFIG_USB_DEVICE 109 #define CONFIG_USB_TTY 110 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 111 112 /* commands to include */ 113 #include <config_cmd_default.h> 114 115 #define CONFIG_CMD_CACHE 116 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 117 #define CONFIG_CMD_FAT /* FAT support */ 118 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 119 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 120 #define CONFIG_MTD_PARTITIONS 121 #define MTDIDS_DEFAULT "nand0=nand" 122 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ 123 "1920k(u-boot),256k(u-boot-env),"\ 124 "4m(kernel),-(fs)" 125 126 #define CONFIG_CMD_I2C /* I2C serial bus support */ 127 #define CONFIG_CMD_MMC /* MMC support */ 128 #define CONFIG_CMD_NAND /* NAND support */ 129 #define CONFIG_CMD_DHCP 130 #define CONFIG_CMD_PING 131 132 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 133 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 134 #undef CONFIG_CMD_IMLS /* List all found images */ 135 136 #define CONFIG_SYS_NO_FLASH 137 #define CONFIG_SYS_I2C 138 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 139 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 140 #define CONFIG_SYS_I2C_OMAP34XX 141 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 142 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 143 #define CONFIG_SYS_I2C_EEPROM_BUS 0 144 #define CONFIG_I2C_MULTI_BUS 145 146 /* 147 * TWL4030 148 */ 149 #define CONFIG_TWL4030_POWER 150 #define CONFIG_TWL4030_LED 151 152 /* 153 * Board NAND Info. 154 */ 155 #define CONFIG_SYS_NAND_QUIET_TEST 156 #define CONFIG_NAND_OMAP_GPMC 157 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 158 /* to access nand */ 159 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 160 /* to access nand at */ 161 /* CS0 */ 162 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 163 /* devices */ 164 165 /* Environment information */ 166 #define CONFIG_BOOTDELAY 3 167 #define CONFIG_ZERO_BOOTDELAY_CHECK 168 169 #define CONFIG_EXTRA_ENV_SETTINGS \ 170 "loadaddr=0x82000000\0" \ 171 "usbtty=cdc_acm\0" \ 172 "console=ttyO2,115200n8\0" \ 173 "mpurate=500\0" \ 174 "vram=12M\0" \ 175 "dvimode=1024x768MR-16@60\0" \ 176 "defaultdisplay=dvi\0" \ 177 "mmcdev=0\0" \ 178 "mmcroot=/dev/mmcblk0p2 rw\0" \ 179 "mmcrootfstype=ext4 rootwait\0" \ 180 "nandroot=/dev/mtdblock4 rw\0" \ 181 "nandrootfstype=ubifs\0" \ 182 "mmcargs=setenv bootargs console=${console} " \ 183 "mpurate=${mpurate} " \ 184 "vram=${vram} " \ 185 "omapfb.mode=dvi:${dvimode} " \ 186 "omapdss.def_disp=${defaultdisplay} " \ 187 "root=${mmcroot} " \ 188 "rootfstype=${mmcrootfstype}\0" \ 189 "nandargs=setenv bootargs console=${console} " \ 190 "mpurate=${mpurate} " \ 191 "vram=${vram} " \ 192 "omapfb.mode=dvi:${dvimode} " \ 193 "omapdss.def_disp=${defaultdisplay} " \ 194 "root=${nandroot} " \ 195 "rootfstype=${nandrootfstype}\0" \ 196 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 197 "bootscript=echo Running bootscript from mmc ...; " \ 198 "source ${loadaddr}\0" \ 199 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 200 "mmcboot=echo Booting from mmc ...; " \ 201 "run mmcargs; " \ 202 "bootm ${loadaddr}\0" \ 203 "nandboot=echo Booting from nand ...; " \ 204 "run nandargs; " \ 205 "nand read ${loadaddr} 2a0000 400000; " \ 206 "bootm ${loadaddr}\0" \ 207 208 #define CONFIG_CMD_BOOTZ 209 #define CONFIG_BOOTCOMMAND \ 210 "mmc dev ${mmcdev}; if mmc rescan; then " \ 211 "if run loadbootscript; then " \ 212 "run bootscript; " \ 213 "else " \ 214 "if run loaduimage; then " \ 215 "run mmcboot; " \ 216 "else run nandboot; " \ 217 "fi; " \ 218 "fi; " \ 219 "else run nandboot; fi" 220 221 /* 222 * Miscellaneous configurable options 223 */ 224 #define CONFIG_AUTO_COMPLETE 225 #define CONFIG_CMDLINE_EDITING 226 #define CONFIG_TIMESTAMP 227 #define CONFIG_SYS_AUTOLOAD "no" 228 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 229 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 230 #define CONFIG_SYS_PROMPT "CM-T3x # " 231 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 232 /* Print Buffer Size */ 233 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 234 sizeof(CONFIG_SYS_PROMPT) + 16) 235 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 236 /* Boot Argument Buffer Size */ 237 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 238 239 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ 240 /* works on */ 241 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 242 0x01F00000) /* 31MB */ 243 244 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 245 /* load address */ 246 247 /* 248 * OMAP3 has 12 GP timers, they can be driven by the system clock 249 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 250 * This rate is divided by a local divisor. 251 */ 252 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 253 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 254 255 /*----------------------------------------------------------------------- 256 * Physical Memory Map 257 */ 258 #define CONFIG_NR_DRAM_BANKS 1 /* CS1 is never populated */ 259 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 260 261 /*----------------------------------------------------------------------- 262 * FLASH and environment organization 263 */ 264 265 /* **** PISMO SUPPORT *** */ 266 /* Monitor at start of flash */ 267 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 268 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 269 270 #define CONFIG_ENV_IS_IN_NAND 271 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 272 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 273 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 274 275 #if defined(CONFIG_CMD_NET) 276 #define CONFIG_SMC911X 277 #define CONFIG_SMC911X_32_BIT 278 #define CM_T3X_SMC911X_BASE 0x2C000000 279 #define SB_T35_SMC911X_BASE (CM_T3X_SMC911X_BASE + (16 << 20)) 280 #define CONFIG_SMC911X_BASE CM_T3X_SMC911X_BASE 281 #endif /* (CONFIG_CMD_NET) */ 282 283 /* additions for new relocation code, must be added to all boards */ 284 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 285 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 286 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 287 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 288 CONFIG_SYS_INIT_RAM_SIZE - \ 289 GENERATED_GBL_DATA_SIZE) 290 291 /* Status LED */ 292 #define CONFIG_STATUS_LED /* Status LED enabled */ 293 #define CONFIG_BOARD_SPECIFIC_LED 294 #define CONFIG_GPIO_LED 295 #define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */ 296 #define GREEN_LED_DEV 0 297 #define STATUS_LED_BIT GREEN_LED_GPIO 298 #define STATUS_LED_STATE STATUS_LED_ON 299 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) 300 #define STATUS_LED_BOOT GREEN_LED_DEV 301 302 #define CONFIG_SPLASHIMAGE_GUARD 303 304 /* GPIO banks */ 305 #ifdef CONFIG_STATUS_LED 306 #define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */ 307 #endif 308 309 /* Display Configuration */ 310 #define CONFIG_OMAP3_GPIO_2 311 #define CONFIG_OMAP3_GPIO_5 312 #define CONFIG_VIDEO_OMAP3 313 #define LCD_BPP LCD_COLOR16 314 315 #define CONFIG_LCD 316 #define CONFIG_SPLASH_SCREEN 317 #define CONFIG_SPLASH_SOURCE 318 #define CONFIG_CMD_BMP 319 #define CONFIG_BMP_16BPP 320 #define CONFIG_SCF0403_LCD 321 322 #define CONFIG_OMAP3_SPI 323 324 /* Defines for SPL */ 325 #define CONFIG_SPL_FRAMEWORK 326 #define CONFIG_SPL_NAND_SIMPLE 327 328 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 329 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ 330 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 331 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 332 333 #define CONFIG_SPL_BOARD_INIT 334 #define CONFIG_SPL_LIBCOMMON_SUPPORT 335 #define CONFIG_SPL_LIBDISK_SUPPORT 336 #define CONFIG_SPL_I2C_SUPPORT 337 #define CONFIG_SPL_LIBGENERIC_SUPPORT 338 #define CONFIG_SPL_MMC_SUPPORT 339 #define CONFIG_SPL_FAT_SUPPORT 340 #define CONFIG_SPL_SERIAL_SUPPORT 341 #define CONFIG_SPL_NAND_SUPPORT 342 #define CONFIG_SPL_NAND_BASE 343 #define CONFIG_SPL_NAND_DRIVERS 344 #define CONFIG_SPL_NAND_ECC 345 #define CONFIG_SPL_GPIO_SUPPORT 346 #define CONFIG_SPL_POWER_SUPPORT 347 #define CONFIG_SPL_OMAP3_ID_NAND 348 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 349 350 /* NAND boot config */ 351 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 352 #define CONFIG_SYS_NAND_PAGE_COUNT 64 353 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 354 #define CONFIG_SYS_NAND_OOBSIZE 64 355 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 356 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 357 /* 358 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: 359 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT 360 */ 361 #define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \ 362 10, 11, 12 } 363 #define CONFIG_SYS_NAND_ECCSIZE 512 364 #define CONFIG_SYS_NAND_ECCBYTES 3 365 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 366 367 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 368 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 369 370 #define CONFIG_SPL_TEXT_BASE 0x40200800 371 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 372 373 /* 374 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the 375 * older x-loader implementations. And move the BSS area so that it 376 * doesn't overlap with TEXT_BASE. 377 */ 378 #define CONFIG_SYS_TEXT_BASE 0x80008000 379 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 380 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 381 382 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 383 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 384 385 #endif /* __CONFIG_H */ 386