1 /* 2 * (C) Copyright 2011 CompuLab, Ltd. 3 * Mike Rapoport <mike@compulab.co.il> 4 * Igor Grinberg <grinberg@compulab.co.il> 5 * 6 * Based on omap3_beagle.h 7 * (C) Copyright 2006-2008 8 * Texas Instruments. 9 * Richard Woodruff <r-woodruff2@ti.com> 10 * Syed Mohammed Khasim <x0khasim@ti.com> 11 * 12 * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 */ 16 17 #ifndef __CONFIG_H 18 #define __CONFIG_H 19 20 #define CONFIG_SYS_CACHELINE_SIZE 64 21 22 /* 23 * High Level Configuration Options 24 */ 25 #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */ 26 27 #define CONFIG_SDRC /* The chip has SDRC controller */ 28 29 #include <asm/arch/cpu.h> /* get chip and board defs */ 30 #include <asm/arch/omap.h> 31 32 /* Clock Defines */ 33 #define V_OSCK 26000000 /* Clock output from T2 */ 34 #define V_SCLK (V_OSCK >> 1) 35 36 #define CONFIG_MISC_INIT_R 37 38 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 39 #define CONFIG_SETUP_MEMORY_TAGS 40 #define CONFIG_INITRD_TAG 41 #define CONFIG_REVISION_TAG 42 #define CONFIG_SERIAL_TAG 43 44 /* 45 * Size of malloc() pool 46 */ 47 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ 48 /* Sector */ 49 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 50 51 /* 52 * Hardware drivers 53 */ 54 55 /* 56 * NS16550 Configuration 57 */ 58 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 59 60 #define CONFIG_SYS_NS16550_SERIAL 61 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 62 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 63 64 /* 65 * select serial console configuration 66 */ 67 #define CONFIG_CONS_INDEX 3 68 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 69 #define CONFIG_SERIAL3 3 /* UART3 */ 70 71 /* allow to overwrite serial and ethaddr */ 72 #define CONFIG_ENV_OVERWRITE 73 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 74 115200} 75 76 /* USB */ 77 #define CONFIG_USB_OMAP3 78 #define CONFIG_USB_EHCI_HCD 79 #define CONFIG_USB_EHCI_OMAP 80 #define CONFIG_USB_MUSB_UDC 81 #define CONFIG_TWL4030_USB 82 83 /* USB device configuration */ 84 #define CONFIG_USB_DEVICE 85 #define CONFIG_USB_TTY 86 87 /* commands to include */ 88 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 89 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 90 #define CONFIG_MTD_PARTITIONS 91 #define MTDIDS_DEFAULT "nand0=nand" 92 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ 93 "1920k(u-boot),256k(u-boot-env),"\ 94 "4m(kernel),-(fs)" 95 96 #define CONFIG_CMD_NAND /* NAND support */ 97 98 #define CONFIG_SYS_I2C 99 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 100 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 101 #define CONFIG_SYS_I2C_OMAP34XX 102 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 103 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 104 #define CONFIG_SYS_I2C_EEPROM_BUS 0 105 #define CONFIG_I2C_MULTI_BUS 106 107 /* 108 * TWL4030 109 */ 110 #define CONFIG_TWL4030_LED 111 112 /* 113 * Board NAND Info. 114 */ 115 #define CONFIG_NAND_OMAP_GPMC 116 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 117 /* to access nand */ 118 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 119 /* to access nand at */ 120 /* CS0 */ 121 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 122 /* devices */ 123 124 /* Environment information */ 125 #define CONFIG_EXTRA_ENV_SETTINGS \ 126 "loadaddr=0x82000000\0" \ 127 "usbtty=cdc_acm\0" \ 128 "console=ttyO2,115200n8\0" \ 129 "mpurate=500\0" \ 130 "vram=12M\0" \ 131 "dvimode=1024x768MR-16@60\0" \ 132 "defaultdisplay=dvi\0" \ 133 "mmcdev=0\0" \ 134 "mmcroot=/dev/mmcblk0p2 rw\0" \ 135 "mmcrootfstype=ext4 rootwait\0" \ 136 "nandroot=/dev/mtdblock4 rw\0" \ 137 "nandrootfstype=ubifs\0" \ 138 "mmcargs=setenv bootargs console=${console} " \ 139 "mpurate=${mpurate} " \ 140 "vram=${vram} " \ 141 "omapfb.mode=dvi:${dvimode} " \ 142 "omapdss.def_disp=${defaultdisplay} " \ 143 "root=${mmcroot} " \ 144 "rootfstype=${mmcrootfstype}\0" \ 145 "nandargs=setenv bootargs console=${console} " \ 146 "mpurate=${mpurate} " \ 147 "vram=${vram} " \ 148 "omapfb.mode=dvi:${dvimode} " \ 149 "omapdss.def_disp=${defaultdisplay} " \ 150 "root=${nandroot} " \ 151 "rootfstype=${nandrootfstype}\0" \ 152 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 153 "bootscript=echo Running bootscript from mmc ...; " \ 154 "source ${loadaddr}\0" \ 155 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 156 "mmcboot=echo Booting from mmc ...; " \ 157 "run mmcargs; " \ 158 "bootm ${loadaddr}\0" \ 159 "nandboot=echo Booting from nand ...; " \ 160 "run nandargs; " \ 161 "nand read ${loadaddr} 2a0000 400000; " \ 162 "bootm ${loadaddr}\0" \ 163 164 #define CONFIG_BOOTCOMMAND \ 165 "mmc dev ${mmcdev}; if mmc rescan; then " \ 166 "if run loadbootscript; then " \ 167 "run bootscript; " \ 168 "else " \ 169 "if run loaduimage; then " \ 170 "run mmcboot; " \ 171 "else run nandboot; " \ 172 "fi; " \ 173 "fi; " \ 174 "else run nandboot; fi" 175 176 /* 177 * Miscellaneous configurable options 178 */ 179 #define CONFIG_AUTO_COMPLETE 180 #define CONFIG_CMDLINE_EDITING 181 #define CONFIG_TIMESTAMP 182 #define CONFIG_SYS_AUTOLOAD "no" 183 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 184 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 185 /* Print Buffer Size */ 186 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 187 sizeof(CONFIG_SYS_PROMPT) + 16) 188 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 189 /* Boot Argument Buffer Size */ 190 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 191 192 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ 193 /* works on */ 194 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 195 0x01F00000) /* 31MB */ 196 197 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 198 /* load address */ 199 200 /* 201 * OMAP3 has 12 GP timers, they can be driven by the system clock 202 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 203 * This rate is divided by a local divisor. 204 */ 205 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 206 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 207 208 /*----------------------------------------------------------------------- 209 * Physical Memory Map 210 */ 211 #define CONFIG_NR_DRAM_BANKS 1 /* CS1 is never populated */ 212 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 213 214 /*----------------------------------------------------------------------- 215 * FLASH and environment organization 216 */ 217 218 /* **** PISMO SUPPORT *** */ 219 /* Monitor at start of flash */ 220 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 221 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 222 223 #define CONFIG_ENV_IS_IN_NAND 224 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 225 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 226 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 227 228 #if defined(CONFIG_CMD_NET) 229 #define CONFIG_SMC911X 230 #define CONFIG_SMC911X_32_BIT 231 #define CM_T3X_SMC911X_BASE 0x2C000000 232 #define SB_T35_SMC911X_BASE (CM_T3X_SMC911X_BASE + (16 << 20)) 233 #define CONFIG_SMC911X_BASE CM_T3X_SMC911X_BASE 234 #endif /* (CONFIG_CMD_NET) */ 235 236 /* additions for new relocation code, must be added to all boards */ 237 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 238 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 239 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 240 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 241 CONFIG_SYS_INIT_RAM_SIZE - \ 242 GENERATED_GBL_DATA_SIZE) 243 244 /* Status LED */ 245 #define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */ 246 247 #define CONFIG_SPLASHIMAGE_GUARD 248 249 /* Display Configuration */ 250 #define CONFIG_VIDEO_OMAP3 251 #define LCD_BPP LCD_COLOR16 252 253 #define CONFIG_SPLASH_SCREEN 254 #define CONFIG_SPLASH_SOURCE 255 #define CONFIG_BMP_16BPP 256 #define CONFIG_SCF0403_LCD 257 258 #define CONFIG_OMAP3_SPI 259 260 /* Defines for SPL */ 261 #define CONFIG_SPL_FRAMEWORK 262 #define CONFIG_SPL_NAND_SIMPLE 263 264 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 265 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 266 267 #define CONFIG_SPL_BOARD_INIT 268 #define CONFIG_SPL_NAND_BASE 269 #define CONFIG_SPL_NAND_DRIVERS 270 #define CONFIG_SPL_NAND_ECC 271 #define CONFIG_SPL_OMAP3_ID_NAND 272 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 273 274 /* NAND boot config */ 275 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 276 #define CONFIG_SYS_NAND_PAGE_COUNT 64 277 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 278 #define CONFIG_SYS_NAND_OOBSIZE 64 279 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 280 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 281 /* 282 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: 283 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT 284 */ 285 #define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \ 286 10, 11, 12 } 287 #define CONFIG_SYS_NAND_ECCSIZE 512 288 #define CONFIG_SYS_NAND_ECCBYTES 3 289 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 290 291 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 292 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 293 294 #define CONFIG_SPL_TEXT_BASE 0x40200800 295 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 296 CONFIG_SPL_TEXT_BASE) 297 298 /* 299 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the 300 * older x-loader implementations. And move the BSS area so that it 301 * doesn't overlap with TEXT_BASE. 302 */ 303 #define CONFIG_SYS_TEXT_BASE 0x80008000 304 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 305 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 306 307 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 308 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 309 310 /* EEPROM */ 311 #define CONFIG_CMD_EEPROM 312 #define CONFIG_ENV_EEPROM_IS_ON_I2C 313 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 314 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 315 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 316 #define CONFIG_SYS_EEPROM_SIZE 256 317 318 #define CONFIG_CMD_EEPROM_LAYOUT 319 #define CONFIG_EEPROM_LAYOUT_HELP_STRING "legacy, v1, v2, v3" 320 321 #endif /* __CONFIG_H */ 322