1 /* 2 * (C) Copyright 2011 CompuLab, Ltd. 3 * Mike Rapoport <mike@compulab.co.il> 4 * Igor Grinberg <grinberg@compulab.co.il> 5 * 6 * Based on omap3_beagle.h 7 * (C) Copyright 2006-2008 8 * Texas Instruments. 9 * Richard Woodruff <r-woodruff2@ti.com> 10 * Syed Mohammed Khasim <x0khasim@ti.com> 11 * 12 * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 */ 16 17 #ifndef __CONFIG_H 18 #define __CONFIG_H 19 20 /* 21 * High Level Configuration Options 22 */ 23 #define CONFIG_OMAP /* in a TI OMAP core */ 24 #define CONFIG_OMAP_GPIO 25 #define CONFIG_CMD_GPIO 26 #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */ 27 #define CONFIG_OMAP_COMMON 28 /* Common ARM Erratas */ 29 #define CONFIG_ARM_ERRATA_454179 30 #define CONFIG_ARM_ERRATA_430973 31 #define CONFIG_ARM_ERRATA_621766 32 33 #define CONFIG_SDRC /* The chip has SDRC controller */ 34 35 #include <asm/arch/cpu.h> /* get chip and board defs */ 36 #include <asm/arch/omap.h> 37 38 /* 39 * Display CPU and Board information 40 */ 41 #define CONFIG_DISPLAY_CPUINFO 42 #define CONFIG_DISPLAY_BOARDINFO 43 44 /* Clock Defines */ 45 #define V_OSCK 26000000 /* Clock output from T2 */ 46 #define V_SCLK (V_OSCK >> 1) 47 48 #define CONFIG_MISC_INIT_R 49 50 #define CONFIG_OF_LIBFDT 1 51 52 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 53 #define CONFIG_SETUP_MEMORY_TAGS 54 #define CONFIG_INITRD_TAG 55 #define CONFIG_REVISION_TAG 56 #define CONFIG_SERIAL_TAG 57 58 /* 59 * Size of malloc() pool 60 */ 61 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ 62 /* Sector */ 63 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 64 65 /* 66 * Hardware drivers 67 */ 68 69 /* 70 * NS16550 Configuration 71 */ 72 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 73 74 #define CONFIG_SYS_NS16550 75 #define CONFIG_SYS_NS16550_SERIAL 76 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 77 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 78 79 /* 80 * select serial console configuration 81 */ 82 #define CONFIG_CONS_INDEX 3 83 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 84 #define CONFIG_SERIAL3 3 /* UART3 */ 85 86 /* allow to overwrite serial and ethaddr */ 87 #define CONFIG_ENV_OVERWRITE 88 #define CONFIG_BAUDRATE 115200 89 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 90 115200} 91 92 #define CONFIG_GENERIC_MMC 93 #define CONFIG_MMC 94 #define CONFIG_OMAP_HSMMC 95 #define CONFIG_DOS_PARTITION 96 97 /* USB */ 98 #define CONFIG_USB_OMAP3 99 #define CONFIG_USB_EHCI 100 #define CONFIG_USB_EHCI_OMAP 101 #define CONFIG_USB_STORAGE 102 #define CONFIG_USB_MUSB_UDC 103 #define CONFIG_TWL4030_USB 104 #define CONFIG_CMD_USB 105 106 /* USB device configuration */ 107 #define CONFIG_USB_DEVICE 108 #define CONFIG_USB_TTY 109 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 110 111 /* commands to include */ 112 #define CONFIG_CMD_CACHE 113 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 114 #define CONFIG_CMD_FAT /* FAT support */ 115 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 116 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 117 #define CONFIG_MTD_PARTITIONS 118 #define MTDIDS_DEFAULT "nand0=nand" 119 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ 120 "1920k(u-boot),256k(u-boot-env),"\ 121 "4m(kernel),-(fs)" 122 123 #define CONFIG_CMD_I2C /* I2C serial bus support */ 124 #define CONFIG_CMD_MMC /* MMC support */ 125 #define CONFIG_CMD_NAND /* NAND support */ 126 #define CONFIG_CMD_DHCP 127 #define CONFIG_CMD_PING 128 129 130 #define CONFIG_SYS_NO_FLASH 131 #define CONFIG_SYS_I2C 132 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 133 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 134 #define CONFIG_SYS_I2C_OMAP34XX 135 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 136 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 137 #define CONFIG_SYS_I2C_EEPROM_BUS 0 138 #define CONFIG_I2C_MULTI_BUS 139 140 /* 141 * TWL4030 142 */ 143 #define CONFIG_TWL4030_POWER 144 #define CONFIG_TWL4030_LED 145 146 /* 147 * Board NAND Info. 148 */ 149 #define CONFIG_NAND_OMAP_GPMC 150 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 151 /* to access nand */ 152 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 153 /* to access nand at */ 154 /* CS0 */ 155 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 156 /* devices */ 157 158 /* Environment information */ 159 #define CONFIG_BOOTDELAY 3 160 #define CONFIG_ZERO_BOOTDELAY_CHECK 161 162 #define CONFIG_EXTRA_ENV_SETTINGS \ 163 "loadaddr=0x82000000\0" \ 164 "usbtty=cdc_acm\0" \ 165 "console=ttyO2,115200n8\0" \ 166 "mpurate=500\0" \ 167 "vram=12M\0" \ 168 "dvimode=1024x768MR-16@60\0" \ 169 "defaultdisplay=dvi\0" \ 170 "mmcdev=0\0" \ 171 "mmcroot=/dev/mmcblk0p2 rw\0" \ 172 "mmcrootfstype=ext4 rootwait\0" \ 173 "nandroot=/dev/mtdblock4 rw\0" \ 174 "nandrootfstype=ubifs\0" \ 175 "mmcargs=setenv bootargs console=${console} " \ 176 "mpurate=${mpurate} " \ 177 "vram=${vram} " \ 178 "omapfb.mode=dvi:${dvimode} " \ 179 "omapdss.def_disp=${defaultdisplay} " \ 180 "root=${mmcroot} " \ 181 "rootfstype=${mmcrootfstype}\0" \ 182 "nandargs=setenv bootargs console=${console} " \ 183 "mpurate=${mpurate} " \ 184 "vram=${vram} " \ 185 "omapfb.mode=dvi:${dvimode} " \ 186 "omapdss.def_disp=${defaultdisplay} " \ 187 "root=${nandroot} " \ 188 "rootfstype=${nandrootfstype}\0" \ 189 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 190 "bootscript=echo Running bootscript from mmc ...; " \ 191 "source ${loadaddr}\0" \ 192 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 193 "mmcboot=echo Booting from mmc ...; " \ 194 "run mmcargs; " \ 195 "bootm ${loadaddr}\0" \ 196 "nandboot=echo Booting from nand ...; " \ 197 "run nandargs; " \ 198 "nand read ${loadaddr} 2a0000 400000; " \ 199 "bootm ${loadaddr}\0" \ 200 201 #define CONFIG_CMD_BOOTZ 202 #define CONFIG_BOOTCOMMAND \ 203 "mmc dev ${mmcdev}; if mmc rescan; then " \ 204 "if run loadbootscript; then " \ 205 "run bootscript; " \ 206 "else " \ 207 "if run loaduimage; then " \ 208 "run mmcboot; " \ 209 "else run nandboot; " \ 210 "fi; " \ 211 "fi; " \ 212 "else run nandboot; fi" 213 214 /* 215 * Miscellaneous configurable options 216 */ 217 #define CONFIG_AUTO_COMPLETE 218 #define CONFIG_CMDLINE_EDITING 219 #define CONFIG_TIMESTAMP 220 #define CONFIG_SYS_AUTOLOAD "no" 221 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 222 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 223 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 224 /* Print Buffer Size */ 225 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 226 sizeof(CONFIG_SYS_PROMPT) + 16) 227 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 228 /* Boot Argument Buffer Size */ 229 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 230 231 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ 232 /* works on */ 233 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 234 0x01F00000) /* 31MB */ 235 236 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 237 /* load address */ 238 239 /* 240 * OMAP3 has 12 GP timers, they can be driven by the system clock 241 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 242 * This rate is divided by a local divisor. 243 */ 244 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 245 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 246 247 /*----------------------------------------------------------------------- 248 * Physical Memory Map 249 */ 250 #define CONFIG_NR_DRAM_BANKS 1 /* CS1 is never populated */ 251 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 252 253 /*----------------------------------------------------------------------- 254 * FLASH and environment organization 255 */ 256 257 /* **** PISMO SUPPORT *** */ 258 /* Monitor at start of flash */ 259 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 260 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 261 262 #define CONFIG_ENV_IS_IN_NAND 263 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 264 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 265 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 266 267 #if defined(CONFIG_CMD_NET) 268 #define CONFIG_SMC911X 269 #define CONFIG_SMC911X_32_BIT 270 #define CM_T3X_SMC911X_BASE 0x2C000000 271 #define SB_T35_SMC911X_BASE (CM_T3X_SMC911X_BASE + (16 << 20)) 272 #define CONFIG_SMC911X_BASE CM_T3X_SMC911X_BASE 273 #endif /* (CONFIG_CMD_NET) */ 274 275 /* additions for new relocation code, must be added to all boards */ 276 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 277 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 278 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 279 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 280 CONFIG_SYS_INIT_RAM_SIZE - \ 281 GENERATED_GBL_DATA_SIZE) 282 283 /* Status LED */ 284 #define CONFIG_STATUS_LED /* Status LED enabled */ 285 #define CONFIG_BOARD_SPECIFIC_LED 286 #define CONFIG_GPIO_LED 287 #define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */ 288 #define GREEN_LED_DEV 0 289 #define STATUS_LED_BIT GREEN_LED_GPIO 290 #define STATUS_LED_STATE STATUS_LED_ON 291 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) 292 #define STATUS_LED_BOOT GREEN_LED_DEV 293 294 #define CONFIG_SPLASHIMAGE_GUARD 295 296 /* GPIO banks */ 297 #ifdef CONFIG_STATUS_LED 298 #define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */ 299 #endif 300 301 /* Display Configuration */ 302 #define CONFIG_OMAP3_GPIO_2 303 #define CONFIG_OMAP3_GPIO_5 304 #define CONFIG_VIDEO_OMAP3 305 #define LCD_BPP LCD_COLOR16 306 307 #define CONFIG_LCD 308 #define CONFIG_SPLASH_SCREEN 309 #define CONFIG_SPLASH_SOURCE 310 #define CONFIG_CMD_BMP 311 #define CONFIG_BMP_16BPP 312 #define CONFIG_SCF0403_LCD 313 314 #define CONFIG_OMAP3_SPI 315 316 /* Defines for SPL */ 317 #define CONFIG_SPL_FRAMEWORK 318 #define CONFIG_SPL_NAND_SIMPLE 319 320 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 321 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ 322 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 323 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 324 325 #define CONFIG_SPL_BOARD_INIT 326 #define CONFIG_SPL_LIBCOMMON_SUPPORT 327 #define CONFIG_SPL_LIBDISK_SUPPORT 328 #define CONFIG_SPL_I2C_SUPPORT 329 #define CONFIG_SPL_LIBGENERIC_SUPPORT 330 #define CONFIG_SPL_MMC_SUPPORT 331 #define CONFIG_SPL_FAT_SUPPORT 332 #define CONFIG_SPL_SERIAL_SUPPORT 333 #define CONFIG_SPL_NAND_SUPPORT 334 #define CONFIG_SPL_NAND_BASE 335 #define CONFIG_SPL_NAND_DRIVERS 336 #define CONFIG_SPL_NAND_ECC 337 #define CONFIG_SPL_GPIO_SUPPORT 338 #define CONFIG_SPL_POWER_SUPPORT 339 #define CONFIG_SPL_OMAP3_ID_NAND 340 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 341 342 /* NAND boot config */ 343 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 344 #define CONFIG_SYS_NAND_PAGE_COUNT 64 345 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 346 #define CONFIG_SYS_NAND_OOBSIZE 64 347 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 348 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 349 /* 350 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: 351 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT 352 */ 353 #define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \ 354 10, 11, 12 } 355 #define CONFIG_SYS_NAND_ECCSIZE 512 356 #define CONFIG_SYS_NAND_ECCBYTES 3 357 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 358 359 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 360 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 361 362 #define CONFIG_SPL_TEXT_BASE 0x40200800 363 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 364 365 /* 366 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the 367 * older x-loader implementations. And move the BSS area so that it 368 * doesn't overlap with TEXT_BASE. 369 */ 370 #define CONFIG_SYS_TEXT_BASE 0x80008000 371 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 372 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 373 374 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 375 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 376 377 #endif /* __CONFIG_H */ 378