1 /* 2 * (C) Copyright 2011 CompuLab, Ltd. 3 * Mike Rapoport <mike@compulab.co.il> 4 * Igor Grinberg <grinberg@compulab.co.il> 5 * 6 * Based on omap3_beagle.h 7 * (C) Copyright 2006-2008 8 * Texas Instruments. 9 * Richard Woodruff <r-woodruff2@ti.com> 10 * Syed Mohammed Khasim <x0khasim@ti.com> 11 * 12 * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 */ 16 17 #ifndef __CONFIG_H 18 #define __CONFIG_H 19 20 #define CONFIG_SYS_CACHELINE_SIZE 64 21 22 /* 23 * High Level Configuration Options 24 */ 25 #define CONFIG_OMAP /* in a TI OMAP core */ 26 #define CONFIG_OMAP_GPIO 27 #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */ 28 #define CONFIG_OMAP_COMMON 29 /* Common ARM Erratas */ 30 #define CONFIG_ARM_ERRATA_454179 31 #define CONFIG_ARM_ERRATA_430973 32 #define CONFIG_ARM_ERRATA_621766 33 34 #define CONFIG_SDRC /* The chip has SDRC controller */ 35 36 #include <asm/arch/cpu.h> /* get chip and board defs */ 37 #include <asm/arch/omap.h> 38 39 /* 40 * Display CPU and Board information 41 */ 42 #define CONFIG_DISPLAY_CPUINFO 43 #define CONFIG_DISPLAY_BOARDINFO 44 45 /* Clock Defines */ 46 #define V_OSCK 26000000 /* Clock output from T2 */ 47 #define V_SCLK (V_OSCK >> 1) 48 49 #define CONFIG_MISC_INIT_R 50 51 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 52 #define CONFIG_SETUP_MEMORY_TAGS 53 #define CONFIG_INITRD_TAG 54 #define CONFIG_REVISION_TAG 55 #define CONFIG_SERIAL_TAG 56 57 /* 58 * Size of malloc() pool 59 */ 60 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ 61 /* Sector */ 62 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 63 64 /* 65 * Hardware drivers 66 */ 67 68 /* 69 * NS16550 Configuration 70 */ 71 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 72 73 #define CONFIG_SYS_NS16550_SERIAL 74 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 75 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 76 77 /* 78 * select serial console configuration 79 */ 80 #define CONFIG_CONS_INDEX 3 81 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 82 #define CONFIG_SERIAL3 3 /* UART3 */ 83 84 /* allow to overwrite serial and ethaddr */ 85 #define CONFIG_ENV_OVERWRITE 86 #define CONFIG_BAUDRATE 115200 87 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 88 115200} 89 90 #define CONFIG_GENERIC_MMC 91 #define CONFIG_MMC 92 #define CONFIG_OMAP_HSMMC 93 #define CONFIG_DOS_PARTITION 94 95 /* USB */ 96 #define CONFIG_USB_OMAP3 97 #define CONFIG_USB_EHCI 98 #define CONFIG_USB_EHCI_OMAP 99 #define CONFIG_USB_STORAGE 100 #define CONFIG_USB_MUSB_UDC 101 #define CONFIG_TWL4030_USB 102 103 /* USB device configuration */ 104 #define CONFIG_USB_DEVICE 105 #define CONFIG_USB_TTY 106 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 107 108 /* commands to include */ 109 #define CONFIG_CMD_CACHE 110 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 111 #define CONFIG_CMD_FAT /* FAT support */ 112 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 113 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 114 #define CONFIG_MTD_PARTITIONS 115 #define MTDIDS_DEFAULT "nand0=nand" 116 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ 117 "1920k(u-boot),256k(u-boot-env),"\ 118 "4m(kernel),-(fs)" 119 120 #define CONFIG_CMD_MMC /* MMC support */ 121 #define CONFIG_CMD_NAND /* NAND support */ 122 123 124 #define CONFIG_SYS_NO_FLASH 125 #define CONFIG_SYS_I2C 126 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 127 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 128 #define CONFIG_SYS_I2C_OMAP34XX 129 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 130 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 131 #define CONFIG_SYS_I2C_EEPROM_BUS 0 132 #define CONFIG_I2C_MULTI_BUS 133 134 /* 135 * TWL4030 136 */ 137 #define CONFIG_TWL4030_POWER 138 #define CONFIG_TWL4030_LED 139 140 /* 141 * Board NAND Info. 142 */ 143 #define CONFIG_NAND_OMAP_GPMC 144 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 145 /* to access nand */ 146 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 147 /* to access nand at */ 148 /* CS0 */ 149 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 150 /* devices */ 151 152 /* Environment information */ 153 #define CONFIG_BOOTDELAY 3 154 #define CONFIG_ZERO_BOOTDELAY_CHECK 155 156 #define CONFIG_EXTRA_ENV_SETTINGS \ 157 "loadaddr=0x82000000\0" \ 158 "usbtty=cdc_acm\0" \ 159 "console=ttyO2,115200n8\0" \ 160 "mpurate=500\0" \ 161 "vram=12M\0" \ 162 "dvimode=1024x768MR-16@60\0" \ 163 "defaultdisplay=dvi\0" \ 164 "mmcdev=0\0" \ 165 "mmcroot=/dev/mmcblk0p2 rw\0" \ 166 "mmcrootfstype=ext4 rootwait\0" \ 167 "nandroot=/dev/mtdblock4 rw\0" \ 168 "nandrootfstype=ubifs\0" \ 169 "mmcargs=setenv bootargs console=${console} " \ 170 "mpurate=${mpurate} " \ 171 "vram=${vram} " \ 172 "omapfb.mode=dvi:${dvimode} " \ 173 "omapdss.def_disp=${defaultdisplay} " \ 174 "root=${mmcroot} " \ 175 "rootfstype=${mmcrootfstype}\0" \ 176 "nandargs=setenv bootargs console=${console} " \ 177 "mpurate=${mpurate} " \ 178 "vram=${vram} " \ 179 "omapfb.mode=dvi:${dvimode} " \ 180 "omapdss.def_disp=${defaultdisplay} " \ 181 "root=${nandroot} " \ 182 "rootfstype=${nandrootfstype}\0" \ 183 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 184 "bootscript=echo Running bootscript from mmc ...; " \ 185 "source ${loadaddr}\0" \ 186 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 187 "mmcboot=echo Booting from mmc ...; " \ 188 "run mmcargs; " \ 189 "bootm ${loadaddr}\0" \ 190 "nandboot=echo Booting from nand ...; " \ 191 "run nandargs; " \ 192 "nand read ${loadaddr} 2a0000 400000; " \ 193 "bootm ${loadaddr}\0" \ 194 195 #define CONFIG_CMD_BOOTZ 196 #define CONFIG_BOOTCOMMAND \ 197 "mmc dev ${mmcdev}; if mmc rescan; then " \ 198 "if run loadbootscript; then " \ 199 "run bootscript; " \ 200 "else " \ 201 "if run loaduimage; then " \ 202 "run mmcboot; " \ 203 "else run nandboot; " \ 204 "fi; " \ 205 "fi; " \ 206 "else run nandboot; fi" 207 208 /* 209 * Miscellaneous configurable options 210 */ 211 #define CONFIG_AUTO_COMPLETE 212 #define CONFIG_CMDLINE_EDITING 213 #define CONFIG_TIMESTAMP 214 #define CONFIG_SYS_AUTOLOAD "no" 215 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 216 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 217 /* Print Buffer Size */ 218 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 219 sizeof(CONFIG_SYS_PROMPT) + 16) 220 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 221 /* Boot Argument Buffer Size */ 222 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 223 224 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ 225 /* works on */ 226 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 227 0x01F00000) /* 31MB */ 228 229 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 230 /* load address */ 231 232 /* 233 * OMAP3 has 12 GP timers, they can be driven by the system clock 234 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 235 * This rate is divided by a local divisor. 236 */ 237 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 238 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 239 240 /*----------------------------------------------------------------------- 241 * Physical Memory Map 242 */ 243 #define CONFIG_NR_DRAM_BANKS 1 /* CS1 is never populated */ 244 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 245 246 /*----------------------------------------------------------------------- 247 * FLASH and environment organization 248 */ 249 250 /* **** PISMO SUPPORT *** */ 251 /* Monitor at start of flash */ 252 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 253 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 254 255 #define CONFIG_ENV_IS_IN_NAND 256 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 257 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 258 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 259 260 #if defined(CONFIG_CMD_NET) 261 #define CONFIG_SMC911X 262 #define CONFIG_SMC911X_32_BIT 263 #define CM_T3X_SMC911X_BASE 0x2C000000 264 #define SB_T35_SMC911X_BASE (CM_T3X_SMC911X_BASE + (16 << 20)) 265 #define CONFIG_SMC911X_BASE CM_T3X_SMC911X_BASE 266 #endif /* (CONFIG_CMD_NET) */ 267 268 /* additions for new relocation code, must be added to all boards */ 269 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 270 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 271 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 272 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 273 CONFIG_SYS_INIT_RAM_SIZE - \ 274 GENERATED_GBL_DATA_SIZE) 275 276 /* Status LED */ 277 #define CONFIG_STATUS_LED /* Status LED enabled */ 278 #define CONFIG_BOARD_SPECIFIC_LED 279 #define CONFIG_GPIO_LED 280 #define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */ 281 #define GREEN_LED_DEV 0 282 #define STATUS_LED_BIT GREEN_LED_GPIO 283 #define STATUS_LED_STATE STATUS_LED_ON 284 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) 285 #define STATUS_LED_BOOT GREEN_LED_DEV 286 287 #define CONFIG_SPLASHIMAGE_GUARD 288 289 /* GPIO banks */ 290 #ifdef CONFIG_STATUS_LED 291 #define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */ 292 #endif 293 294 /* Display Configuration */ 295 #define CONFIG_OMAP3_GPIO_2 296 #define CONFIG_OMAP3_GPIO_5 297 #define CONFIG_VIDEO_OMAP3 298 #define LCD_BPP LCD_COLOR16 299 300 #define CONFIG_LCD 301 #define CONFIG_SPLASH_SCREEN 302 #define CONFIG_SPLASH_SOURCE 303 #define CONFIG_CMD_BMP 304 #define CONFIG_BMP_16BPP 305 #define CONFIG_SCF0403_LCD 306 307 #define CONFIG_OMAP3_SPI 308 309 /* Defines for SPL */ 310 #define CONFIG_SPL_FRAMEWORK 311 #define CONFIG_SPL_NAND_SIMPLE 312 313 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 314 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ 315 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 316 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 317 318 #define CONFIG_SPL_BOARD_INIT 319 #define CONFIG_SPL_LIBCOMMON_SUPPORT 320 #define CONFIG_SPL_LIBDISK_SUPPORT 321 #define CONFIG_SPL_I2C_SUPPORT 322 #define CONFIG_SPL_LIBGENERIC_SUPPORT 323 #define CONFIG_SPL_MMC_SUPPORT 324 #define CONFIG_SPL_FAT_SUPPORT 325 #define CONFIG_SPL_SERIAL_SUPPORT 326 #define CONFIG_SPL_NAND_SUPPORT 327 #define CONFIG_SPL_NAND_BASE 328 #define CONFIG_SPL_NAND_DRIVERS 329 #define CONFIG_SPL_NAND_ECC 330 #define CONFIG_SPL_GPIO_SUPPORT 331 #define CONFIG_SPL_POWER_SUPPORT 332 #define CONFIG_SPL_OMAP3_ID_NAND 333 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 334 335 /* NAND boot config */ 336 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 337 #define CONFIG_SYS_NAND_PAGE_COUNT 64 338 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 339 #define CONFIG_SYS_NAND_OOBSIZE 64 340 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 341 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 342 /* 343 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: 344 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT 345 */ 346 #define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \ 347 10, 11, 12 } 348 #define CONFIG_SYS_NAND_ECCSIZE 512 349 #define CONFIG_SYS_NAND_ECCBYTES 3 350 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 351 352 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 353 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 354 355 #define CONFIG_SPL_TEXT_BASE 0x40200800 356 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 357 358 /* 359 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the 360 * older x-loader implementations. And move the BSS area so that it 361 * doesn't overlap with TEXT_BASE. 362 */ 363 #define CONFIG_SYS_TEXT_BASE 0x80008000 364 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 365 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 366 367 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 368 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 369 370 #endif /* __CONFIG_H */ 371